Merge branch 'qed-get_regs'
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commit
c63ad410a2
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@ -7638,6 +7638,7 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
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#define DRV_MSG_CODE_MCP_RESET 0x00090000
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#define DRV_MSG_CODE_SET_VERSION 0x000f0000
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#define DRV_MSG_CODE_MCP_HALT 0x00100000
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#define DRV_MSG_CODE_GET_STATS 0x00130000
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#define DRV_MSG_CODE_STATS_TYPE_LAN 1
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@ -7645,6 +7646,8 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
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#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
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#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
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#define DRV_MSG_CODE_BIST_TEST 0x001e0000
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#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
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@ -389,6 +389,34 @@ int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
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return 0;
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}
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int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 cmd,
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u32 param,
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u32 *o_mcp_resp,
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u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
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{
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struct qed_mcp_mb_params mb_params;
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union drv_union_data union_data;
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int rc;
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memset(&mb_params, 0, sizeof(mb_params));
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mb_params.cmd = cmd;
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mb_params.param = param;
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mb_params.p_data_dst = &union_data;
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rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
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if (rc)
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return rc;
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*o_mcp_resp = mb_params.mcp_resp;
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*o_mcp_param = mb_params.mcp_param;
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*o_txn_size = *o_mcp_param;
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memcpy(o_buf, &union_data.raw_data, *o_txn_size);
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return 0;
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}
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int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 *p_load_code)
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{
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@ -1168,6 +1196,33 @@ qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
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return rc;
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}
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int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 resp = 0, param = 0;
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int rc;
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rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
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¶m);
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if (rc)
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DP_ERR(p_hwfn, "MCP response failure, aborting\n");
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return rc;
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}
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int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 value, cpu_mode;
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qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
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value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
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value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
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qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
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cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
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return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
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}
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int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, enum qed_led_mode mode)
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{
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@ -1195,6 +1250,27 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
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return rc;
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}
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int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 mask_parities)
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{
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u32 resp = 0, param = 0;
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int rc;
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rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
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mask_parities, &resp, ¶m);
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if (rc) {
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DP_ERR(p_hwfn,
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"MCP response failure for mask parities, aborting\n");
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} else if (resp != FW_MSG_CODE_OK) {
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DP_ERR(p_hwfn,
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"MCP did not acknowledge mask parity request. Old MFW?\n");
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rc = -EINVAL;
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}
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return rc;
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}
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int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 drv_mb_param = 0, rsp, param;
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@ -467,6 +467,29 @@ int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
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int qed_mcp_reset(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt);
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/**
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* @brief - Sends an NVM read command request to the MFW to get
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* a buffer.
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*
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* @param p_hwfn
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* @param p_ptt
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* @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or
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* DRV_MSG_CODE_NVM_READ_NVRAM commands
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* @param param - [0:23] - Offset [24:31] - Size
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* @param o_mcp_resp - MCP response
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* @param o_mcp_param - MCP response param
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* @param o_txn_size - Buffer size output
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* @param o_buf - Pointer to the buffer returned by the MFW.
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*
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* @param return 0 upon success.
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*/
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int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 cmd,
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u32 param,
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u32 *o_mcp_resp,
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u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf);
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/**
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* @brief indicates whether the MFW objects [under mcp_info] are accessible
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*
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@ -489,6 +512,26 @@ bool qed_mcp_is_init(struct qed_hwfn *p_hwfn);
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int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 vf_id, u8 num);
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/**
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* @brief - Halt the MCP.
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @param return 0 upon success.
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*/
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int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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/**
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* @brief - Wake up the MCP.
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*
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* @param p_hwfn
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* @param p_ptt
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*
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* @param return 0 upon success.
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*/
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int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw);
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int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw);
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int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
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@ -500,4 +543,7 @@ int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
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struct qed_mcp_link_state *p_link,
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u8 min_bw);
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int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 mask_parities);
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#endif
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@ -527,4 +527,10 @@
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#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
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#define QM_REG_WFQVPWEIGHT 0x2fa000UL
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#define MCP_REG_CPU_MODE \
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0xe05000UL
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#define MCP_REG_CPU_MODE_SOFT_HALT \
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(0x1 << 10)
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#endif
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