ARM: KVM: move kvm_condition_valid to emulate.c
This is really hardware emulation, and as such it better be with its little friends. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -28,6 +28,7 @@ unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
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int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
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bool kvm_condition_valid(struct kvm_vcpu *vcpu);
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void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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@ -44,7 +44,6 @@
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_coproc.h>
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#include <asm/kvm_psci.h>
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#include <asm/opcodes.h>
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#ifdef REQUIRES_VIRT
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__asm__(".arch_extension virt");
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@ -545,50 +544,6 @@ static exit_handle_fn arm_exit_handlers[] = {
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[HSR_EC_DABT_HYP] = handle_dabt_hyp,
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};
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/*
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* A conditional instruction is allowed to trap, even though it
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* wouldn't be executed. So let's re-implement the hardware, in
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* software!
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*/
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static bool kvm_condition_valid(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr, cond, insn;
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/*
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* Exception Code 0 can only happen if we set HCR.TGE to 1, to
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* catch undefined instructions, and then we won't get past
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* the arm_exit_handlers test anyway.
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*/
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BUG_ON(!kvm_vcpu_trap_get_class(vcpu));
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/* Top two bits non-zero? Unconditional. */
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if (kvm_vcpu_get_hsr(vcpu) >> 30)
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return true;
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cpsr = *vcpu_cpsr(vcpu);
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/* Is condition field valid? */
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if ((kvm_vcpu_get_hsr(vcpu) & HSR_CV) >> HSR_CV_SHIFT)
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cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
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else {
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/* This can happen in Thumb mode: examine IT state. */
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unsigned long it;
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it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
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/* it == 0 => unconditional. */
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if (it == 0)
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return true;
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/* The cond for this insn works out as the top 4 bits. */
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cond = (it >> 4);
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}
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/* Shift makes it look like an ARM-mode instruction */
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insn = cond << 28;
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return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
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}
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/*
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* Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
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* proper exit to QEMU.
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@ -20,6 +20,7 @@
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#include <linux/kvm_host.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/opcodes.h>
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#include <trace/events/kvm.h>
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#include "trace.h"
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@ -176,6 +177,50 @@ int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
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return 1;
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}
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/*
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* A conditional instruction is allowed to trap, even though it
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* wouldn't be executed. So let's re-implement the hardware, in
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* software!
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*/
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bool kvm_condition_valid(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr, cond, insn;
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/*
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* Exception Code 0 can only happen if we set HCR.TGE to 1, to
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* catch undefined instructions, and then we won't get past
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* the arm_exit_handlers test anyway.
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*/
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BUG_ON(!kvm_vcpu_trap_get_class(vcpu));
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/* Top two bits non-zero? Unconditional. */
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if (kvm_vcpu_get_hsr(vcpu) >> 30)
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return true;
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cpsr = *vcpu_cpsr(vcpu);
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/* Is condition field valid? */
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if ((kvm_vcpu_get_hsr(vcpu) & HSR_CV) >> HSR_CV_SHIFT)
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cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
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else {
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/* This can happen in Thumb mode: examine IT state. */
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unsigned long it;
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it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
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/* it == 0 => unconditional. */
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if (it == 0)
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return true;
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/* The cond for this insn works out as the top 4 bits. */
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cond = (it >> 4);
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}
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/* Shift makes it look like an ARM-mode instruction */
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insn = cond << 28;
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return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
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}
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/**
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* adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
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* @vcpu: The VCPU pointer
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