[S390] entry[64].S improvements
Another round of cleanup for entry[64].S, in particular the program check handler looks more reasonable now. The code size for the 31 bit kernel has been reduced by 616 byte and by 528 byte for the 64 bit version. Even better the code is a bit faster as well. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky
parent
3b7f993394
commit
c5328901aa
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@ -97,47 +97,52 @@ struct _lowcore {
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__u32 gpregs_save_area[16]; /* 0x0180 */
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__u32 cregs_save_area[16]; /* 0x01c0 */
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/* Save areas. */
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__u32 save_area_sync[8]; /* 0x0200 */
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__u32 save_area_async[8]; /* 0x0220 */
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__u32 save_area_restart[1]; /* 0x0240 */
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__u8 pad_0x0244[0x0248-0x0244]; /* 0x0244 */
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/* Return psws. */
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__u32 save_area[16]; /* 0x0200 */
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psw_t return_psw; /* 0x0240 */
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psw_t return_mcck_psw; /* 0x0248 */
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psw_t return_psw; /* 0x0248 */
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psw_t return_mcck_psw; /* 0x0250 */
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/* CPU time accounting values */
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__u64 sync_enter_timer; /* 0x0250 */
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__u64 async_enter_timer; /* 0x0258 */
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__u64 mcck_enter_timer; /* 0x0260 */
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__u64 exit_timer; /* 0x0268 */
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__u64 user_timer; /* 0x0270 */
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__u64 system_timer; /* 0x0278 */
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__u64 steal_timer; /* 0x0280 */
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__u64 last_update_timer; /* 0x0288 */
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__u64 last_update_clock; /* 0x0290 */
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__u64 sync_enter_timer; /* 0x0258 */
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__u64 async_enter_timer; /* 0x0260 */
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__u64 mcck_enter_timer; /* 0x0268 */
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__u64 exit_timer; /* 0x0270 */
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__u64 user_timer; /* 0x0278 */
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__u64 system_timer; /* 0x0280 */
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__u64 steal_timer; /* 0x0288 */
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__u64 last_update_timer; /* 0x0290 */
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__u64 last_update_clock; /* 0x0298 */
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/* Current process. */
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__u32 current_task; /* 0x0298 */
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__u32 thread_info; /* 0x029c */
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__u32 kernel_stack; /* 0x02a0 */
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__u32 current_task; /* 0x02a0 */
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__u32 thread_info; /* 0x02a4 */
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__u32 kernel_stack; /* 0x02a8 */
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/* Interrupt and panic stack. */
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__u32 async_stack; /* 0x02a4 */
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__u32 panic_stack; /* 0x02a8 */
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__u32 async_stack; /* 0x02ac */
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__u32 panic_stack; /* 0x02b0 */
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/* Address space pointer. */
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__u32 kernel_asce; /* 0x02ac */
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__u32 user_asce; /* 0x02b0 */
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__u32 current_pid; /* 0x02b4 */
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__u32 kernel_asce; /* 0x02b4 */
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__u32 user_asce; /* 0x02b8 */
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__u32 current_pid; /* 0x02bc */
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/* SMP info area */
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__u32 cpu_nr; /* 0x02b8 */
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__u32 softirq_pending; /* 0x02bc */
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__u32 percpu_offset; /* 0x02c0 */
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__u32 ext_call_fast; /* 0x02c4 */
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__u64 int_clock; /* 0x02c8 */
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__u64 mcck_clock; /* 0x02d0 */
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__u64 clock_comparator; /* 0x02d8 */
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__u32 machine_flags; /* 0x02e0 */
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__u32 ftrace_func; /* 0x02e4 */
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__u8 pad_0x02e8[0x0300-0x02e8]; /* 0x02e8 */
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__u32 cpu_nr; /* 0x02c0 */
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__u32 softirq_pending; /* 0x02c4 */
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__u32 percpu_offset; /* 0x02c8 */
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__u32 ext_call_fast; /* 0x02cc */
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__u64 int_clock; /* 0x02d0 */
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__u64 mcck_clock; /* 0x02d8 */
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__u64 clock_comparator; /* 0x02e0 */
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__u32 machine_flags; /* 0x02e8 */
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__u32 ftrace_func; /* 0x02ec */
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__u8 pad_0x02f8[0x0300-0x02f0]; /* 0x02f0 */
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/* Interrupt response block */
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__u8 irb[64]; /* 0x0300 */
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@ -229,57 +234,62 @@ struct _lowcore {
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psw_t mcck_new_psw; /* 0x01e0 */
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psw_t io_new_psw; /* 0x01f0 */
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/* Entry/exit save area & return psws. */
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__u64 save_area[16]; /* 0x0200 */
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psw_t return_psw; /* 0x0280 */
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psw_t return_mcck_psw; /* 0x0290 */
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/* Save areas. */
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__u64 save_area_sync[8]; /* 0x0200 */
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__u64 save_area_async[8]; /* 0x0240 */
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__u64 save_area_restart[1]; /* 0x0280 */
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__u8 pad_0x0288[0x0290-0x0288]; /* 0x0288 */
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/* Return psws. */
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psw_t return_psw; /* 0x0290 */
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psw_t return_mcck_psw; /* 0x02a0 */
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/* CPU accounting and timing values. */
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__u64 sync_enter_timer; /* 0x02a0 */
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__u64 async_enter_timer; /* 0x02a8 */
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__u64 mcck_enter_timer; /* 0x02b0 */
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__u64 exit_timer; /* 0x02b8 */
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__u64 user_timer; /* 0x02c0 */
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__u64 system_timer; /* 0x02c8 */
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__u64 steal_timer; /* 0x02d0 */
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__u64 last_update_timer; /* 0x02d8 */
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__u64 last_update_clock; /* 0x02e0 */
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__u64 sync_enter_timer; /* 0x02b0 */
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__u64 async_enter_timer; /* 0x02b8 */
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__u64 mcck_enter_timer; /* 0x02c0 */
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__u64 exit_timer; /* 0x02c8 */
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__u64 user_timer; /* 0x02d0 */
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__u64 system_timer; /* 0x02d8 */
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__u64 steal_timer; /* 0x02e0 */
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__u64 last_update_timer; /* 0x02e8 */
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__u64 last_update_clock; /* 0x02f0 */
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/* Current process. */
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__u64 current_task; /* 0x02e8 */
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__u64 thread_info; /* 0x02f0 */
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__u64 kernel_stack; /* 0x02f8 */
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__u64 current_task; /* 0x02f8 */
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__u64 thread_info; /* 0x0300 */
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__u64 kernel_stack; /* 0x0308 */
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/* Interrupt and panic stack. */
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__u64 async_stack; /* 0x0300 */
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__u64 panic_stack; /* 0x0308 */
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__u64 async_stack; /* 0x0310 */
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__u64 panic_stack; /* 0x0318 */
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/* Address space pointer. */
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__u64 kernel_asce; /* 0x0310 */
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__u64 user_asce; /* 0x0318 */
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__u64 current_pid; /* 0x0320 */
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__u64 kernel_asce; /* 0x0320 */
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__u64 user_asce; /* 0x0328 */
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__u64 current_pid; /* 0x0330 */
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/* SMP info area */
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__u32 cpu_nr; /* 0x0328 */
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__u32 softirq_pending; /* 0x032c */
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__u64 percpu_offset; /* 0x0330 */
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__u64 ext_call_fast; /* 0x0338 */
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__u64 int_clock; /* 0x0340 */
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__u64 mcck_clock; /* 0x0348 */
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__u64 clock_comparator; /* 0x0350 */
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__u64 vdso_per_cpu_data; /* 0x0358 */
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__u64 machine_flags; /* 0x0360 */
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__u64 ftrace_func; /* 0x0368 */
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__u64 gmap; /* 0x0370 */
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__u8 pad_0x0378[0x0380-0x0378]; /* 0x0378 */
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__u32 cpu_nr; /* 0x0338 */
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__u32 softirq_pending; /* 0x033c */
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__u64 percpu_offset; /* 0x0340 */
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__u64 ext_call_fast; /* 0x0348 */
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__u64 int_clock; /* 0x0350 */
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__u64 mcck_clock; /* 0x0358 */
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__u64 clock_comparator; /* 0x0360 */
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__u64 vdso_per_cpu_data; /* 0x0368 */
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__u64 machine_flags; /* 0x0370 */
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__u64 ftrace_func; /* 0x0378 */
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__u64 gmap; /* 0x0380 */
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__u8 pad_0x0388[0x0400-0x0388]; /* 0x0388 */
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/* Interrupt response block. */
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__u8 irb[64]; /* 0x0380 */
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__u8 irb[64]; /* 0x0400 */
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/* Per cpu primary space access list */
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__u32 paste[16]; /* 0x03c0 */
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__u32 paste[16]; /* 0x0440 */
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__u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */
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__u8 pad_0x0480[0x0e00-0x0480]; /* 0x0480 */
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/*
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* 0xe00 contains the address of the IPL Parameter Information
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@ -108,7 +108,9 @@ int main(void)
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DEFINE(__LC_PGM_NEW_PSW, offsetof(struct _lowcore, program_new_psw));
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DEFINE(__LC_MCK_NEW_PSW, offsetof(struct _lowcore, mcck_new_psw));
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DEFINE(__LC_IO_NEW_PSW, offsetof(struct _lowcore, io_new_psw));
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DEFINE(__LC_SAVE_AREA, offsetof(struct _lowcore, save_area));
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DEFINE(__LC_SAVE_AREA_SYNC, offsetof(struct _lowcore, save_area_sync));
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DEFINE(__LC_SAVE_AREA_ASYNC, offsetof(struct _lowcore, save_area_async));
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DEFINE(__LC_SAVE_AREA_RESTART, offsetof(struct _lowcore, save_area_restart));
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DEFINE(__LC_RETURN_PSW, offsetof(struct _lowcore, return_psw));
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DEFINE(__LC_RETURN_MCCK_PSW, offsetof(struct _lowcore, return_mcck_psw));
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DEFINE(__LC_SYNC_ENTER_TIMER, offsetof(struct _lowcore, sync_enter_timer));
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@ -33,7 +33,7 @@ s390_base_mcck_handler_fn:
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.previous
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ENTRY(s390_base_ext_handler)
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stmg %r0,%r15,__LC_SAVE_AREA
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stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_ext_handler_fn
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@ -41,7 +41,7 @@ ENTRY(s390_base_ext_handler)
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ltgr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: lmg %r0,%r15,__LC_SAVE_AREA
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1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpswe __LC_EXT_OLD_PSW
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@ -53,7 +53,7 @@ s390_base_ext_handler_fn:
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.previous
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ENTRY(s390_base_pgm_handler)
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stmg %r0,%r15,__LC_SAVE_AREA
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stmg %r0,%r15,__LC_SAVE_AREA_SYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_pgm_handler_fn
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@ -61,7 +61,7 @@ ENTRY(s390_base_pgm_handler)
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ltgr %r1,%r1
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jz 1f
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basr %r14,%r1
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lmg %r0,%r15,__LC_SAVE_AREA
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lmg %r0,%r15,__LC_SAVE_AREA_SYNC
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lpswe __LC_PGM_OLD_PSW
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1: lpswe disabled_wait_psw-0b(%r13)
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@ -142,7 +142,7 @@ s390_base_mcck_handler_fn:
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.previous
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ENTRY(s390_base_ext_handler)
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stm %r0,%r15,__LC_SAVE_AREA
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stm %r0,%r15,__LC_SAVE_AREA_ASYNC
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basr %r13,0
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0: ahi %r15,-STACK_FRAME_OVERHEAD
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l %r1,2f-0b(%r13)
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@ -150,7 +150,7 @@ ENTRY(s390_base_ext_handler)
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ltr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: lm %r0,%r15,__LC_SAVE_AREA
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1: lm %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpsw __LC_EXT_OLD_PSW
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@ -164,7 +164,7 @@ s390_base_ext_handler_fn:
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.previous
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ENTRY(s390_base_pgm_handler)
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stm %r0,%r15,__LC_SAVE_AREA
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stm %r0,%r15,__LC_SAVE_AREA_SYNC
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basr %r13,0
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0: ahi %r15,-STACK_FRAME_OVERHEAD
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l %r1,2f-0b(%r13)
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@ -172,7 +172,7 @@ ENTRY(s390_base_pgm_handler)
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ltr %r1,%r1
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jz 1f
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basr %r14,%r1
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lm %r0,%r15,__LC_SAVE_AREA
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lm %r0,%r15,__LC_SAVE_AREA_SYNC
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lpsw __LC_PGM_OLD_PSW
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1: lpsw disabled_wait_psw-0b(%r13)
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -329,8 +329,8 @@ iplstart:
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#
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# reset files in VM reader
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#
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stidp __LC_SAVE_AREA # store cpuid
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tm __LC_SAVE_AREA,0xff # running VM ?
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stidp __LC_SAVE_AREA_SYNC # store cpuid
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tm __LC_SAVE_AREA_SYNC,0xff# running VM ?
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bno .Lnoreset
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la %r2,.Lreset
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lhi %r3,26
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@ -17,11 +17,11 @@
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#
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ENTRY(store_status)
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/* Save register one and load save area base */
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stg %r1,__LC_SAVE_AREA+120(%r0)
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stg %r1,__LC_SAVE_AREA_RESTART
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lghi %r1,SAVE_AREA_BASE
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/* General purpose registers */
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stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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lg %r2,__LC_SAVE_AREA+120(%r0)
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lg %r2,__LC_SAVE_AREA_RESTART
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stg %r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
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/* Control registers */
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stctg %c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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@ -654,7 +654,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
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- sizeof(struct stack_frame));
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memset(sf, 0, sizeof(struct stack_frame));
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sf->gprs[9] = (unsigned long) sf;
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cpu_lowcore->save_area[15] = (unsigned long) sf;
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cpu_lowcore->gpregs_save_area[15] = (unsigned long) sf;
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__ctl_store(cpu_lowcore->cregs_save_area, 0, 15);
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atomic_inc(&init_mm.context.attach_count);
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asm volatile(
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