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coresight: etm3x: consolidating initial config 

There is really no point in having two functions to take care
of doing the initial tracer configuration.  As such moving
everything to 'etm_set_default()'.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathieu Poirier 2016-02-17 17:51:55 -07:00 committed by Greg Kroah-Hartman
parent e19217299c
commit c528a25ac7
1 changed files with 14 additions and 23 deletions
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37
drivers/hwtracing/coresight/coresight-etm3x.c
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@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO);
/* The number of ETM/PTM currently registered */ /* The number of ETM/PTM currently registered */
static int etm_count; static int etm_count;
static struct etm_drvdata *etmdrvdata[NR_CPUS]; static struct etm_drvdata *etmdrvdata[NR_CPUS];
static void etm_init_default_data(struct etm_config *config);
/* /*
* Memory mapped writes to clear os lock are not supported on some processors * Memory mapped writes to clear os lock are not supported on some processors
@ -194,6 +193,19 @@ void etm_set_default(struct etm_config *config)
if (WARN_ON_ONCE(!config)) if (WARN_ON_ONCE(!config))
return; return;
/*
* Taken verbatim from the TRM:
*
* To trace all memory:
* set bit [24] in register 0x009, the ETMTECR1, to 1
* set all other bits in register 0x009, the ETMTECR1, to 0
* set all bits in register 0x007, the ETMTECR2, to 0
* set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
*/
config->enable_ctrl1 = BIT(24);
config->enable_ctrl2 = 0x0;
config->enable_event = ETM_HARD_WIRE_RES_A;
config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->trigger_event = ETM_DEFAULT_EVENT_VAL;
config->enable_event = ETM_HARD_WIRE_RES_A; config->enable_event = ETM_HARD_WIRE_RES_A;
@ -577,27 +589,6 @@ static void etm_init_arch_data(void *info)
CS_LOCK(drvdata->base); CS_LOCK(drvdata->base);
} }
static void etm_init_default_data(struct etm_config *config)
{
if (WARN_ON_ONCE(!config))
return;
etm_set_default(config);
/*
* Taken verbatim from the TRM:
*
* To trace all memory:
* set bit [24] in register 0x009, the ETMTECR1, to 1
* set all other bits in register 0x009, the ETMTECR1, to 0
* set all bits in register 0x007, the ETMTECR2, to 0
* set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
*/
config->enable_ctrl1 = BIT(24);
config->enable_ctrl2 = 0x0;
config->enable_event = ETM_HARD_WIRE_RES_A;
}
static void etm_init_trace_id(struct etm_drvdata *drvdata) static void etm_init_trace_id(struct etm_drvdata *drvdata)
{ {
/* /*
@ -674,7 +665,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
} }
etm_init_trace_id(drvdata); etm_init_trace_id(drvdata);
etm_init_default_data(&drvdata->config); etm_set_default(&drvdata->config);
desc->type = CORESIGHT_DEV_TYPE_SOURCE; desc->type = CORESIGHT_DEV_TYPE_SOURCE;
desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;