From 4dea6c9b0b64fc4cbd543b5a3b6320218be8ca9c Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Fri, 11 Dec 2015 09:39:57 +0530 Subject: [PATCH 01/13] spi: spi-ti-qspi: add mmap mode read support ti-qspi controller provides mmap port to read data from SPI flashes. mmap port is enabled in QSPI_SPI_SWITCH_REG. ctrl module register may also need to be accessed for some SoCs. The QSPI_SPI_SETUP_REGx needs to be populated with flash specific information like read opcode, read mode(quad, dual, normal), address width and dummy bytes. Once, controller is in mmap mode, the whole flash memory is available as a memory region at SoC specific address. This region can be accessed using normal memcpy() (or mem-to-mem dma copy). The ti-qspi controller hardware will internally communicate with SPI flash over SPI bus and get the requested data. Implement spi_flash_read() callback to support mmap read over SPI flash devices. With this, the read throughput increases from ~100kB/s to ~2.5 MB/s. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- drivers/spi/spi-ti-qspi.c | 137 ++++++++++++++++++++++++++++++-------- 1 file changed, 109 insertions(+), 28 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 64318fcfacf2..eac3c960b2de 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include #include @@ -44,8 +46,9 @@ struct ti_qspi { struct spi_master *master; void __iomem *base; - void __iomem *ctrl_base; void __iomem *mmap_base; + struct regmap *ctrl_base; + unsigned int ctrl_reg; struct clk *fclk; struct device *dev; @@ -55,7 +58,7 @@ struct ti_qspi { u32 cmd; u32 dc; - bool ctrl_mod; + bool mmap_enabled; }; #define QSPI_PID (0x0) @@ -65,11 +68,8 @@ struct ti_qspi { #define QSPI_SPI_CMD_REG (0x48) #define QSPI_SPI_STATUS_REG (0x4c) #define QSPI_SPI_DATA_REG (0x50) -#define QSPI_SPI_SETUP0_REG (0x54) +#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n)) #define QSPI_SPI_SWITCH_REG (0x64) -#define QSPI_SPI_SETUP1_REG (0x58) -#define QSPI_SPI_SETUP2_REG (0x5c) -#define QSPI_SPI_SETUP3_REG (0x60) #define QSPI_SPI_DATA_REG_1 (0x68) #define QSPI_SPI_DATA_REG_2 (0x6c) #define QSPI_SPI_DATA_REG_3 (0x70) @@ -109,6 +109,17 @@ struct ti_qspi { #define QSPI_AUTOSUSPEND_TIMEOUT 2000 +#define MEM_CS_EN(n) ((n + 1) << 8) +#define MEM_CS_MASK (7 << 8) + +#define MM_SWITCH 0x1 + +#define QSPI_SETUP_RD_NORMAL (0x0 << 12) +#define QSPI_SETUP_RD_DUAL (0x1 << 12) +#define QSPI_SETUP_RD_QUAD (0x3 << 12) +#define QSPI_SETUP_ADDR_SHIFT 8 +#define QSPI_SETUP_DUMMY_SHIFT 10 + static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, unsigned long reg) { @@ -366,6 +377,72 @@ static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t) return 0; } +static void ti_qspi_enable_memory_map(struct spi_device *spi) +{ + struct ti_qspi *qspi = spi_master_get_devdata(spi->master); + + ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); + if (qspi->ctrl_base) { + regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, + MEM_CS_EN(spi->chip_select), + MEM_CS_MASK); + } + qspi->mmap_enabled = true; +} + +static void ti_qspi_disable_memory_map(struct spi_device *spi) +{ + struct ti_qspi *qspi = spi_master_get_devdata(spi->master); + + ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); + if (qspi->ctrl_base) + regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, + 0, MEM_CS_MASK); + qspi->mmap_enabled = false; +} + +static void ti_qspi_setup_mmap_read(struct spi_device *spi, + struct spi_flash_read_message *msg) +{ + struct ti_qspi *qspi = spi_master_get_devdata(spi->master); + u32 memval = msg->read_opcode; + + switch (msg->data_nbits) { + case SPI_NBITS_QUAD: + memval |= QSPI_SETUP_RD_QUAD; + break; + case SPI_NBITS_DUAL: + memval |= QSPI_SETUP_RD_DUAL; + break; + default: + memval |= QSPI_SETUP_RD_NORMAL; + break; + } + memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | + msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); + ti_qspi_write(qspi, memval, + QSPI_SPI_SETUP_REG(spi->chip_select)); +} + +static int ti_qspi_spi_flash_read(struct spi_device *spi, + struct spi_flash_read_message *msg) +{ + struct ti_qspi *qspi = spi_master_get_devdata(spi->master); + int ret = 0; + + mutex_lock(&qspi->list_lock); + + if (!qspi->mmap_enabled) + ti_qspi_enable_memory_map(spi); + ti_qspi_setup_mmap_read(spi, msg); + memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len); + msg->retlen = msg->len; + + mutex_unlock(&qspi->list_lock); + + return ret; +} + static int ti_qspi_start_transfer_one(struct spi_master *master, struct spi_message *m) { @@ -398,6 +475,9 @@ static int ti_qspi_start_transfer_one(struct spi_master *master, mutex_lock(&qspi->list_lock); + if (qspi->mmap_enabled) + ti_qspi_disable_memory_map(spi); + list_for_each_entry(t, &m->transfers, transfer_list) { qspi->cmd |= QSPI_WLEN(t->bits_per_word); @@ -441,7 +521,7 @@ static int ti_qspi_probe(struct platform_device *pdev) { struct ti_qspi *qspi; struct spi_master *master; - struct resource *r, *res_ctrl, *res_mmap; + struct resource *r, *res_mmap; struct device_node *np = pdev->dev.of_node; u32 max_freq; int ret = 0, num_cs, irq; @@ -487,16 +567,6 @@ static int ti_qspi_probe(struct platform_device *pdev) } } - res_ctrl = platform_get_resource_byname(pdev, - IORESOURCE_MEM, "qspi_ctrlmod"); - if (res_ctrl == NULL) { - res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2); - if (res_ctrl == NULL) { - dev_dbg(&pdev->dev, - "control module resources not required\n"); - } - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); @@ -511,20 +581,31 @@ static int ti_qspi_probe(struct platform_device *pdev) goto free_master; } - if (res_ctrl) { - qspi->ctrl_mod = true; - qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl); - if (IS_ERR(qspi->ctrl_base)) { - ret = PTR_ERR(qspi->ctrl_base); - goto free_master; + if (res_mmap) { + qspi->mmap_base = devm_ioremap_resource(&pdev->dev, + res_mmap); + master->spi_flash_read = ti_qspi_spi_flash_read; + if (IS_ERR(qspi->mmap_base)) { + dev_err(&pdev->dev, + "falling back to PIO mode\n"); + master->spi_flash_read = NULL; } } + qspi->mmap_enabled = false; - if (res_mmap) { - qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); - if (IS_ERR(qspi->mmap_base)) { - ret = PTR_ERR(qspi->mmap_base); - goto free_master; + if (of_property_read_bool(np, "syscon-chipselects")) { + qspi->ctrl_base = + syscon_regmap_lookup_by_phandle(np, + "syscon-chipselects"); + if (IS_ERR(qspi->ctrl_base)) + return PTR_ERR(qspi->ctrl_base); + ret = of_property_read_u32_index(np, + "syscon-chipselects", + 1, &qspi->ctrl_reg); + if (ret) { + dev_err(&pdev->dev, + "couldn't get ctrl_mod reg index\n"); + return ret; } } From 23366a02bfd3b4d3075aefcfd71600fb1360a02e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 16 Feb 2016 11:23:32 +0800 Subject: [PATCH 02/13] spi: rockchip: remove xfer_completion from rockchip_spi xfer_completion isn't been used anywhere, so it can be removed. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 79a8bc4f6cec..07909ee9b33f 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -192,8 +192,6 @@ struct rockchip_spi { /* protect state */ spinlock_t lock; - struct completion xfer_completion; - u32 use_dma; struct sg_table tx_sg; struct sg_table rx_sg; From 9b7a56221590cad777e56ec40afe7a6a68f9ac01 Mon Sep 17 00:00:00 2001 From: Xu Jianqun Date: Thu, 18 Feb 2016 19:16:31 +0800 Subject: [PATCH 03/13] spi: rockchip: add bindings for rk3399 spi Add devicetree bindings for Rockchip rk3399 spi which found on Rockchip rk3399 SoCs. Signed-off-by: Jianqun Xu Signed-off-by: Heiko Stuebner Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 + drivers/spi/spi-rockchip.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt index 0c491bda4c65..1b14d69d8903 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt @@ -9,6 +9,7 @@ Required Properties: "rockchip,rk3066-spi" for rk3066. "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188. "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288. + "rockchip,rk3399-spi", "rockchip,rk3066-spi" for rk3399. - reg: physical base address of the controller and length of memory mapped region. - interrupts: The interrupt number to the cpu. The interrupt specifier format diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 07909ee9b33f..07c082aa5cff 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -866,6 +866,7 @@ static const struct of_device_id rockchip_spi_dt_match[] = { { .compatible = "rockchip,rk3066-spi", }, { .compatible = "rockchip,rk3188-spi", }, { .compatible = "rockchip,rk3288-spi", }, + { .compatible = "rockchip,rk3399-spi", }, { }, }; MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); From 3aec3166739ee9e49a23b3e7b6bfe5781ade04d4 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 18 Feb 2016 10:47:52 +0900 Subject: [PATCH 04/13] spi: sh-spi, sh-msiof, rspi: Use ARCH_RENESAS Make use of ARCH_RENESAS in place of ARCH_SHMOBILE. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 77064160dd76..496e48131db4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -451,7 +451,7 @@ config SPI_RB4XX config SPI_RSPI tristate "Renesas RSPI/QSPI controller" - depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST + depends on SUPERH || ARCH_RENESAS || COMPILE_TEST help SPI driver for Renesas RSPI and QSPI blocks. @@ -501,7 +501,7 @@ config SPI_SC18IS602 config SPI_SH_MSIOF tristate "SuperH MSIOF SPI controller" depends on HAVE_CLK && HAS_DMA - depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST + depends on SUPERH || ARCH_RENESAS || COMPILE_TEST help SPI driver for SuperH and SH Mobile MSIOF blocks. @@ -520,7 +520,7 @@ config SPI_SH_SCI config SPI_SH_HSPI tristate "SuperH HSPI controller" - depends on ARCH_SHMOBILE || COMPILE_TEST + depends on ARCH_RENESAS || COMPILE_TEST help SPI driver for SuperH HSPI blocks. From d6497816836da321a46c0e8575c4fa3d0c672bda Mon Sep 17 00:00:00 2001 From: Martin Sperl Date: Thu, 18 Feb 2016 15:53:10 +0000 Subject: [PATCH 05/13] spi: docbook: fix parsing error Fixes docbook parsing error because documentation is not directly followed by the structure, but typedef used in structure. Reordering should solve that issue. Signed-off-by: Martin Sperl Signed-off-by: Mark Brown --- include/linux/spi/spi.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 38204b584dc5..5396ee5fc51f 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -586,6 +586,10 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum); * SPI resource management while processing a SPI message */ +typedef void (*spi_res_release_t)(struct spi_master *master, + struct spi_message *msg, + void *res); + /** * struct spi_res - spi resource management structure * @entry: list entry @@ -595,9 +599,6 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum); * this is based on ideas from devres, but focused on life-cycle * management during spi_message processing */ -typedef void (*spi_res_release_t)(struct spi_master *master, - struct spi_message *msg, - void *res); struct spi_res { struct list_head entry; spi_res_release_t release; From b920cc3191d7612f26f36ee494e05b5ffd9044c0 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 24 Feb 2016 18:00:04 +0800 Subject: [PATCH 06/13] spi/rockchip: Make sure spi clk is on in rockchip_spi_set_cs Rockchip_spi_set_cs could be called by spi_setup, but spi_setup may be called by device driver after runtime suspend. Then the spi clock is closed, rockchip_spi_set_cs may access the spi registers, which causes cpu block in some socs. Fixes: 64e36824b32 ("spi/rockchip: add driver for Rockchip RK3xxx") Signed-off-by: Huibin Hong Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 07c082aa5cff..6cdb4d81d66c 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -263,7 +263,10 @@ static inline u32 rx_max(struct rockchip_spi *rs) static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) { u32 ser; - struct rockchip_spi *rs = spi_master_get_devdata(spi->master); + struct spi_master *master = spi->master; + struct rockchip_spi *rs = spi_master_get_devdata(master); + + pm_runtime_get_sync(rs->dev); ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; @@ -288,6 +291,8 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) ser &= ~(1 << spi->chip_select); writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); + + pm_runtime_put_sync(rs->dev); } static int rockchip_spi_prepare_message(struct spi_master *master, From 0277e01aebc8895198a4717ccaf7e4fcf39ada78 Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Sun, 6 Mar 2016 13:04:17 +0300 Subject: [PATCH 07/13] spi/rockchip: fix endian mode for 16-bit transfers 16-bit transfers must be in big endian mode on wire. Signed-off-by: Alexander Kochetkov Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 6cdb4d81d66c..9a5c51764833 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs) int rsd = 0; u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) - | (CR0_SSD_ONE << CR0_SSD_OFFSET); + | (CR0_SSD_ONE << CR0_SSD_OFFSET) + | (CR0_EM_BIG << CR0_EM_OFFSET); cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); From ea98491133439773b69345eb9a314fc5f15e07a4 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 9 Mar 2016 16:11:15 +0800 Subject: [PATCH 08/13] spi: rockchip: check return value of dmaengine_prep_slave_sg We should check return value of dmaengine_prep_slave_sg, otherwise we take risk of null pointer. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 9a5c51764833..aa8528e9840c 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -436,7 +436,7 @@ static void rockchip_spi_dma_txcb(void *data) spin_unlock_irqrestore(&rs->lock, flags); } -static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) +static int rockchip_spi_prepare_dma(struct rockchip_spi *rs) { unsigned long flags; struct dma_slave_config rxconf, txconf; @@ -459,6 +459,8 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) rs->dma_rx.ch, rs->rx_sg.sgl, rs->rx_sg.nents, rs->dma_rx.direction, DMA_PREP_INTERRUPT); + if (!rxdesc) + return -EINVAL; rxdesc->callback = rockchip_spi_dma_rxcb; rxdesc->callback_param = rs; @@ -476,6 +478,11 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) rs->dma_tx.ch, rs->tx_sg.sgl, rs->tx_sg.nents, rs->dma_tx.direction, DMA_PREP_INTERRUPT); + if (!txdesc) { + if (rxdesc) + dmaengine_terminate_sync(rs->dma_rx.ch); + return -EINVAL; + } txdesc->callback = rockchip_spi_dma_txcb; txdesc->callback_param = rs; @@ -497,6 +504,8 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) dmaengine_submit(txdesc); dma_async_issue_pending(rs->dma_tx.ch); } + + return 0; } static void rockchip_spi_config(struct rockchip_spi *rs) @@ -610,12 +619,12 @@ static int rockchip_spi_transfer_one( if (rs->use_dma) { if (rs->tmode == CR0_XFM_RO) { /* rx: dma must be prepared first */ - rockchip_spi_prepare_dma(rs); + ret = rockchip_spi_prepare_dma(rs); spi_enable_chip(rs, 1); } else { /* tx or tr: spi must be enabled first */ spi_enable_chip(rs, 1); - rockchip_spi_prepare_dma(rs); + ret = rockchip_spi_prepare_dma(rs); } } else { spi_enable_chip(rs, 1); From 557b7ea34b9a10a5e13f4d7fd58ac965d801e3bd Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 9 Mar 2016 16:11:23 +0800 Subject: [PATCH 09/13] spi: rockchip: migrate to dmaengine_terminate_async dmaengine_terminate_all is deprecated, let's use dmaengine_terminate_async for interrupt handling. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index aa8528e9840c..b6b8a0bb5b2f 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -322,12 +322,12 @@ static void rockchip_spi_handle_err(struct spi_master *master, */ if (rs->use_dma) { if (rs->state & RXBUSY) { - dmaengine_terminate_all(rs->dma_rx.ch); + dmaengine_terminate_async(rs->dma_rx.ch); flush_fifo(rs); } if (rs->state & TXBUSY) - dmaengine_terminate_all(rs->dma_tx.ch); + dmaengine_terminate_async(rs->dma_tx.ch); } spin_unlock_irqrestore(&rs->lock, flags); From 61cadcf46cfdb9f7eec70527968c2b91e9823786 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 9 Mar 2016 16:11:32 +0800 Subject: [PATCH 10/13] spi: rockchip: check requesting dma channel with EPROBE_DEFER Let's defer probing the driver if the return value of dma_request_slave_channel is ERR_PTR(-EPROBE_DEFER) instead of disabling dma capability directly. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index b6b8a0bb5b2f..795fd191faa7 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -730,8 +730,14 @@ static int rockchip_spi_probe(struct platform_device *pdev) master->handle_err = rockchip_spi_handle_err; rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); - if (!rs->dma_tx.ch) + if (IS_ERR_OR_NULL(rs->dma_tx.ch)) { + /* Check tx to see if we need defer probing driver */ + if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto err_get_fifo_len; + } dev_warn(rs->dev, "Failed to request TX DMA channel\n"); + } rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); if (!rs->dma_rx.ch) { From 82b3aea65f9fee161d8e07602e5a8c7b0b103fa3 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Wed, 9 Mar 2016 14:17:20 +0530 Subject: [PATCH 11/13] spi: xilinx: Add devicetree binding for spi-xilinx Add a binding document for the spi/spi-xilinx Signed-off-by: Shubhrajyoti Datta Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-xilinx.txt | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-xilinx.txt diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt new file mode 100644 index 000000000000..c7b7856bd528 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.txt @@ -0,0 +1,22 @@ +Xilinx SPI controller Device Tree Bindings +------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,xps-spi-2.00.a" or "xlnx,xps-spi-2.00.b" +- reg : Physical base address and size of SPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller + +Optional properties: +- xlnx,num-ss-bits : Number of chip selects used. + +Example: + axi_quad_spi@41e00000 { + compatible = "xlnx,xps-spi-2.00.a"; + interrupt-parent = <&intc>; + interrupts = <0 31 1>; + reg = <0x41e00000 0x10000>; + xlnx,num-ss-bits = <0x1>; + }; + From ec5c5d8ac028cfec4c7c976d93bed1734f1a670a Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 10 Mar 2016 14:51:48 +0800 Subject: [PATCH 12/13] spi: rockchip: header file cleanup Remove some of unused header files and reoder it into alphabetical order. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 795fd191faa7..1b54f2f18021 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -13,20 +13,14 @@ * */ -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include +#include #define DRIVER_NAME "rockchip-spi" From 108b5c8bba6be101100596bf37a165214e1c8458 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 10 Mar 2016 14:52:27 +0800 Subject: [PATCH 13/13] spi: rockchip: covert rsd_nsecs to u32 type rsd_nsecs is defined as u8 memeber of struct rockchip_spi, but using of_property_read_u32. That means we take risk of truncation by type conversion if we pass on big value from dt. Signed-off-by: Shawn Lin Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 1b54f2f18021..5488597cfad4 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -173,7 +173,7 @@ struct rockchip_spi { u8 tmode; u8 bpw; u8 n_bytes; - u8 rsd_nsecs; + u32 rsd_nsecs; unsigned len; u32 speed;