x86_64: add chip_ops and a quirk function for CalIOC2
[akpm@linux-foundation.org>: make calioc2_chip_ops static] Signed-off-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -79,6 +79,9 @@ int use_calgary __read_mostly = 0;
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#define PHB_MEM_2_SIZE_LOW 0x02E0
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#define PHB_DOSHOLE_OFFSET 0x08E0
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/* CalIOC2 specific */
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#define PHB_SAVIOR_L2 0x0DB0
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/* PHB_CONFIG_RW */
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#define PHB_TCE_ENABLE 0x20000000
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#define PHB_SLOT_DISABLE 0x1C000000
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@ -156,12 +159,18 @@ struct calgary_bus_info {
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static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
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static void calgary_tce_cache_blast(struct iommu_table *tbl);
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static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
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static struct cal_chipset_ops calgary_chip_ops = {
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.handle_quirks = calgary_handle_quirks,
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.tce_cache_blast = calgary_tce_cache_blast
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};
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static struct cal_chipset_ops calioc2_chip_ops = {
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.handle_quirks = calioc2_handle_quirks,
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.tce_cache_blast = NULL
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};
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static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
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/* enable this to stress test the chip's TCE cache */
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@ -743,7 +752,12 @@ static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
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tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
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tce_free(tbl, 0, tbl->it_size);
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tbl->chip_ops = &calgary_chip_ops;
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if (is_calgary(dev->device))
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tbl->chip_ops = &calgary_chip_ops;
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else if (is_calioc2(dev->device))
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tbl->chip_ops = &calioc2_chip_ops;
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else
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BUG();
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calgary_reserve_regions(dev);
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@ -894,8 +908,23 @@ static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
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readq(target); /* flush */
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}
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static void __init calgary_handle_quirks(struct iommu_table *tbl,
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struct pci_dev *dev)
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static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
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{
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unsigned char busnum = dev->bus->number;
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void __iomem *bbar = tbl->bbar;
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void __iomem *target;
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u32 val;
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/*
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* CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
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*/
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target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
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val = cpu_to_be32(readl(target));
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val |= 0x00800000;
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writel(cpu_to_be32(val), target);
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}
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static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
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{
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unsigned char busnum = dev->bus->number;
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@ -903,7 +932,7 @@ static void __init calgary_handle_quirks(struct iommu_table *tbl,
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* Give split completion a longer timeout on bus 1 for aic94xx
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* http://bugzilla.kernel.org/show_bug.cgi?id=7180
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*/
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if (busnum == 1)
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if (is_calgary(dev->device) && (busnum == 1))
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calgary_set_split_completion_timeout(tbl->bbar, busnum,
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CCR_2SEC_TIMEOUT);
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}
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