mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Samsung Exynos SoC's extend the dw-mshc controller for additional clock and bus control. Add support for these extensions and include provide device tree based discovery suppory as well. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Thomas Abraham
Chris Ball
parent
800d78bfcc
commit
c3665006ec
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@ -0,0 +1,87 @@
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* Samsung Exynos specific extensions to the Synopsis Designware Mobile
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Storage Host Controller
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The Synopsis designware mobile storage host controller is used to interface
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a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
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differences between the core Synopsis dw mshc controller properties described
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by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific
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extensions to the Synopsis Designware Mobile Storage Host Controller.
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Required Properties:
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* compatible: should be
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- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
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specific extentions.
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- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
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specific extentions.
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- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
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specific extentions.
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* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
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unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
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ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
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* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
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in transmit mode and CIU clock phase shift value in receive mode for single
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data rate mode operation. Refer notes below for the order of the cells and the
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valid values.
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* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
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in transmit mode and CIU clock phase shift value in receive mode for double
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data rate mode operation. Refer notes below for the order of the cells and the
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valid values.
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Notes for the sdr-timing and ddr-timing values:
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The order of the cells should be
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- First Cell: CIU clock phase shift value for tx mode.
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- Second Cell: CIU clock phase shift value for rx mode.
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Valid values for SDR and DDR CIU clock timing for Exynos5250:
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- valid value for tx phase shift and rx phase shift is 0 to 7.
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- when CIU clock divider value is set to 3, all possible 8 phase shift
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values can be used.
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- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
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phase shift clocks should be 0.
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Required properties for a slot:
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* gpios: specifies a list of gpios used for command, clock and data bus. The
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first gpio is the command line and the second gpio is the clock line. The
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rest of the gpios (depending on the bus-width property) are the data lines in
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no particular order. The format of the gpio specifier depends on the gpio
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controller.
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Example:
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The MSHC controller node can be split into two portions, SoC specific and
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board specific portions as listed below.
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dwmmc0@12200000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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dwmmc0@12200000 {
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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fifo-depth = <0x80>;
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card-detect-delay = <200>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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slot@0 {
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reg = <0>;
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bus-width = <8>;
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gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
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<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
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<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
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<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
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<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
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};
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};
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@ -540,6 +540,15 @@ config MMC_DW_PLTFM
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If unsure, say Y.
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config MMC_DW_EXYNOS
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tristate "Exynos specific extentions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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select MMC_DW_PLTFM
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help
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This selects support for Samsung Exynos SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on Exynos4 and Exynos5 SoC's.
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config MMC_DW_PCI
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tristate "Synopsys Designware MCI support on PCI bus"
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depends on MMC_DW && PCI
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@ -39,6 +39,7 @@ obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
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obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o
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obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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@ -0,0 +1,253 @@
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/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define NUM_PINS(x) (x + 2)
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#define SDMMC_CLKSEL 0x09C
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
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SDMMC_CLKSEL_CCLK_DRIVE(y) | \
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SDMMC_CLKSEL_CCLK_DIVIDER(z))
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#define SDMMC_CMD_USE_HOLD_REG BIT(29)
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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};
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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enum dw_mci_exynos_type ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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};
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static struct dw_mci_exynos_compatible {
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char *compatible;
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enum dw_mci_exynos_type ctrl_type;
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} exynos_compat[] = {
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{
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.compatible = "samsung,exynos4210-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
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}, {
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.compatible = "samsung,exynos4412-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
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}, {
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.compatible = "samsung,exynos5250-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
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},
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};
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv;
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int idx;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(host->dev, "mem alloc failed for private data\n");
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return -ENOMEM;
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}
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for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
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if (of_device_is_compatible(host->dev->of_node,
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exynos_compat[idx].compatible))
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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}
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host->priv = priv;
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return 0;
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}
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static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
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host->bus_hz /= (priv->ciu_div + 1);
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
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return 0;
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}
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static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
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{
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/*
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* Exynos4412 and Exynos5250 extends the use of CMD register with the
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* use of bit 29 (which is reserved on standard MSHC controllers) for
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* optionally bypassing the HOLD register for command and data. The
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (ios->timing == MMC_TIMING_UHS_DDR50)
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mci_writel(host, CLKSEL, priv->ddr_timing);
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else
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mci_writel(host, CLKSEL, priv->sdr_timing);
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct device_node *np = host->dev->of_node;
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u32 timing[2];
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u32 div = 0;
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int ret;
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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priv->ciu_div = div;
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-sdr-timing", timing, 2);
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if (ret)
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return ret;
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priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-ddr-timing", timing, 2);
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if (ret)
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return ret;
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priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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return 0;
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}
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static int dw_mci_exynos_setup_bus(struct dw_mci *host,
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struct device_node *slot_np, u8 bus_width)
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{
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int idx, gpio, ret;
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if (!slot_np)
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return -EINVAL;
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/* cmd + clock + bus-width pins */
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for (idx = 0; idx < NUM_PINS(bus_width); idx++) {
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gpio = of_get_gpio(slot_np, idx);
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if (!gpio_is_valid(gpio)) {
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dev_err(host->dev, "invalid gpio: %d\n", gpio);
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return -EINVAL;
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}
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ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
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if (ret) {
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dev_err(host->dev, "gpio [%d] request failed\n", gpio);
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return -EBUSY;
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}
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}
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gpio = of_get_named_gpio(slot_np, "wp-gpios", 0);
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if (gpio_is_valid(gpio)) {
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if (devm_gpio_request(host->dev, gpio, "dw-mci-wp"))
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dev_info(host->dev, "gpio [%d] request failed\n",
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gpio);
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} else {
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dev_info(host->dev, "wp gpio not available");
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host->pdata->quirks |= DW_MCI_QUIRK_NO_WRITE_PROTECT;
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}
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if (host->pdata->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
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return 0;
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gpio = of_get_named_gpio(slot_np, "samsung,cd-pinmux-gpio", 0);
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if (gpio_is_valid(gpio)) {
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if (devm_gpio_request(host->dev, gpio, "dw-mci-cd"))
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dev_err(host->dev, "gpio [%d] request failed\n", gpio);
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} else {
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dev_info(host->dev, "cd gpio not available");
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}
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return 0;
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}
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/* Exynos5250 controller specific capabilities */
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static unsigned long exynos5250_dwmmc_caps[4] = {
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MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
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MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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MMC_CAP_CMD23,
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};
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static struct dw_mci_drv_data exynos5250_drv_data = {
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.caps = exynos5250_dwmmc_caps,
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.init = dw_mci_exynos_priv_init,
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.setup_clock = dw_mci_exynos_setup_clock,
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.prepare_command = dw_mci_exynos_prepare_command,
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.set_ios = dw_mci_exynos_set_ios,
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.parse_dt = dw_mci_exynos_parse_dt,
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.setup_bus = dw_mci_exynos_setup_bus,
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};
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static const struct of_device_id dw_mci_exynos_match[] = {
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{ .compatible = "samsung,exynos5250-dw-mshc",
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.data = (void *)&exynos5250_drv_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
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int dw_mci_exynos_probe(struct platform_device *pdev)
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{
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struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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static struct platform_driver dw_mci_exynos_pltfm_driver = {
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.probe = dw_mci_exynos_probe,
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.remove = __exit_p(dw_mci_pltfm_remove),
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.driver = {
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.name = "dwmmc_exynos",
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.of_match_table = of_match_ptr(dw_mci_exynos_match),
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.pm = &dw_mci_pltfm_pmops,
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},
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};
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module_platform_driver(dw_mci_exynos_pltfm_driver);
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MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
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MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dwmmc-exynos");
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@ -227,7 +227,7 @@ struct dw_mci_board {
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u32 num_slots;
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u32 quirks; /* Workaround / Quirk flags */
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unsigned int bus_hz; /* Bus speed */
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unsigned int bus_hz; /* Clock speed at the cclk_in pad */
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unsigned int caps; /* Capabilities */
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unsigned int caps2; /* More capabilities */
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