From 6d2d419ffd83502d105014288e6af171a0a89544 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Thu, 6 Dec 2007 15:35:54 +0000 Subject: [PATCH 1/5] [MIPS] Don't byteswap writes to display when running bigendian Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/mips-boards/generic/display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c index 5d600054090a..2a0057cfc30d 100644 --- a/arch/mips/mips-boards/generic/display.c +++ b/arch/mips/mips-boards/generic/display.c @@ -37,9 +37,9 @@ void mips_display_message(const char *str) for (i = 0; i <= 14; i=i+2) { if (*str) - writel(*str++, display + i); + __raw_writel(*str++, display + i); else - writel(' ', display + i); + __raw_writel(' ', display + i); } } From 0f5e49a2e2de69ee05ad8783274b0672247fd18f Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 6 Dec 2007 08:11:56 +0100 Subject: [PATCH 2/5] [MIPS] Alchemy: Fix Au1x SD controller IRQ With the introduction of MIPS_CPU_IRQ_BASE, the hardcoded IRQ number of the au1100/au1200 SD controller(s) is no longer valid. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1100_mmc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h index 9e7d1ba21b55..9e0028f60a43 100644 --- a/include/asm-mips/mach-au1x00/au1100_mmc.h +++ b/include/asm-mips/mach-au1x00/au1100_mmc.h @@ -41,8 +41,11 @@ #define NUM_AU1100_MMC_CONTROLLERS 2 - -#define AU1100_SD_IRQ 2 +#if defined(CONFIG_SOC_AU1100) +#define AU1100_SD_IRQ AU1100_SD_INT +#elif defined(CONFIG_SOC_AU1200) +#define AU1100_SD_IRQ AU1200_SD_INT +#endif #define SD0_BASE 0xB0600000 From 8f7e7d67cbcbcfd2c72d496f01f5e4c78853ef7d Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 23 Nov 2007 00:44:06 +0900 Subject: [PATCH 3/5] qemu: do not enable IP7 blindly IP7 will be enabled automatically in mips_clockevent_init(), if available. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/qemu/q-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c index 11f984767880..7df36dbe65c7 100644 --- a/arch/mips/qemu/q-irq.c +++ b/arch/mips/qemu/q-irq.c @@ -33,5 +33,5 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); init_i8259_irqs(); - set_c0_status(0x8400); + set_c0_status(0x400); } From 5ef1b9a0f6cbb1269fc8b8d7704d146f22bf7aa6 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 16 Nov 2007 23:15:51 +0000 Subject: [PATCH 4/5] [MIPS] Bigsur: Enable tickless and and highres timers. Signed-off-by: Ralf Baechle --- arch/mips/configs/bigsur_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 80b0c99c2cfb..3c70c9d16d01 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_BCM1480=y +CONFIG_CSRC_BCM1480=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set @@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set From ba0f00b9fcb02b10cc9929fec660f86d1af6a41a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 16 Nov 2007 14:54:46 +0000 Subject: [PATCH 5/5] [MIPS] Malta: Enable tickless and highres timers. Most Malta use an FPGA CPU card which rarely is good for more than 40MHz. So the performance penalta of the regular timer interrupt, especially for the VSMP kernel model is significant, even at a mere 100Hz. Signed-off-by: Ralf Baechle --- arch/mips/configs/malta_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index fbd2d802fdfd..4b7e43c9f69a 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_CEVT_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y @@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y +CONFIG_I8253=y # # PCCARD (PCMCIA/CardBus) support