ARM: i.MX27 clk: Use of_clk_init() for DT case
Replace .init_time() hook with of_clk_init() for DT targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -1,32 +1,31 @@
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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#include "common.h"
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#include "hardware.h"
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#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
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static void __iomem *ccm __initdata;
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/* Register offsets */
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#define CCM_CSCR IO_ADDR_CCM(0x0)
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#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
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#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
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#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
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#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
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#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
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#define CCM_PCDR0 IO_ADDR_CCM(0x18)
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#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
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#define CCM_PCCR0 IO_ADDR_CCM(0x20)
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#define CCM_PCCR1 IO_ADDR_CCM(0x24)
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#define CCM_CCSR IO_ADDR_CCM(0x28)
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#define CCM_PMCTL IO_ADDR_CCM(0x2c)
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#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
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#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
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#define CCM_CSCR (ccm + 0x00)
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#define CCM_MPCTL0 (ccm + 0x04)
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#define CCM_MPCTL1 (ccm + 0x08)
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#define CCM_SPCTL0 (ccm + 0x0c)
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#define CCM_SPCTL1 (ccm + 0x10)
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#define CCM_OSC26MCTL (ccm + 0x14)
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#define CCM_PCDR0 (ccm + 0x18)
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#define CCM_PCDR1 (ccm + 0x1c)
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#define CCM_PCCR0 (ccm + 0x20)
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#define CCM_PCCR1 (ccm + 0x24)
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#define CCM_CCSR (ccm + 0x28)
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#define CCM_PMCTL (ccm + 0x2c)
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#define CCM_PMCOUNT (ccm + 0x30)
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#define CCM_WKGDCTL (ccm + 0x34)
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#define CCM_CSCR_UPDATE_DIS (1 << 31)
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#define CCM_CSCR_SSI2 (1 << 23)
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@ -93,6 +92,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
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{
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unsigned i;
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BUG_ON(!ccm);
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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@ -214,6 +215,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
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int __init mx27_clocks_init(unsigned long fref)
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{
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ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
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_mx27_clocks_init(fref);
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clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
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@ -283,29 +286,27 @@ int __init mx27_clocks_init(unsigned long fref)
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return 0;
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}
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int __init mx27_clocks_init_dt(void)
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static void __init mx27_clocks_init_dt(struct device_node *np)
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{
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struct device_node *np;
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struct device_node *refnp;
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u32 fref = 26000000; /* default */
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for_each_compatible_node(np, NULL, "fixed-clock") {
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if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
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for_each_compatible_node(refnp, NULL, "fixed-clock") {
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if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
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continue;
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if (!of_property_read_u32(np, "clock-frequency", &fref))
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if (!of_property_read_u32(refnp, "clock-frequency", &fref))
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break;
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}
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_mx27_clocks_init(fref);
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ccm = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
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BUG_ON(!np);
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_mx27_clocks_init(fref);
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
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return 0;
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}
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CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
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@ -56,7 +56,6 @@ int mx27_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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int mx35_clocks_init(void);
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int mx25_clocks_init_dt(void);
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int mx27_clocks_init_dt(void);
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int mx31_clocks_init_dt(void);
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struct platform_device *mxc_register_gpio(char *name, int id,
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resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = {
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NULL
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};
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static void __init imx27_timer_init(void)
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{
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mx27_clocks_init_dt();
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}
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DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
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.map_io = mx27_map_io,
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.init_early = imx27_init_early,
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.init_irq = mx27_init_irq,
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.init_time = imx27_timer_init,
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.init_machine = imx27_dt_init,
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.dt_compat = imx27_dt_board_compat,
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.restart = mxc_restart,
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