dt-bindings: phy: tegra: Add Tegra194 support
Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -37,6 +37,7 @@ Required properties:
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- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
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- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
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- Tegra210: "nvidia,tegra210-xusb-padctl"
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- Tegra210: "nvidia,tegra210-xusb-padctl"
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- Tegra186: "nvidia,tegra186-xusb-padctl"
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- Tegra186: "nvidia,tegra186-xusb-padctl"
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- Tegra194: "nvidia,tegra194-xusb-padctl"
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- reg: Physical base address and length of the controller's registers.
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- reg: Physical base address and length of the controller's registers.
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- resets: Must contain an entry for each entry in reset-names.
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must include the following entries:
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- reset-names: Must include the following entries:
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@ -62,6 +63,10 @@ For Tegra186:
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- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
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- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
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- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
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- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
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For Tegra194:
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- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
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3.3 V.
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- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
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Pad nodes:
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Pad nodes:
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==========
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==========
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@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
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- sata: sata-0
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- sata: sata-0
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- functions: "usb3-ss", "sata"
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- functions: "usb3-ss", "sata"
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For Tegra194, the list of valid PHY nodes is given below:
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- usb2: usb2-0, usb2-1, usb2-2, usb2-3
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- functions: "xusb"
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- usb3: usb3-0, usb3-1, usb3-2, usb3-3
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- functions: "xusb"
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Port nodes:
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Port nodes:
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===========
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===========
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@ -221,6 +231,11 @@ Optional properties:
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is internal. In the absence of this property the port is considered to be
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is internal. In the absence of this property the port is considered to be
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external.
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external.
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- maximum-speed: Only for Tegra194. A string property that specifies maximum
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supported speed of a usb3 port. Valid values are:
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- "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
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- "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
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For Tegra124 and Tegra132, the XUSB pad controller exposes the following
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For Tegra124 and Tegra132, the XUSB pad controller exposes the following
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ports:
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ports:
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- 3x USB2: usb2-0, usb2-1, usb2-2
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- 3x USB2: usb2-0, usb2-1, usb2-2
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@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
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- 2x HSIC: hsic-0, hsic-1
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- 2x HSIC: hsic-0, hsic-1
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- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
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- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
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For Tegra194, the XUSB pad controller exposes the following ports:
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- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
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- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
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Examples:
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Examples:
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=========
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=========
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