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linux-sg2042
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Merge ../linux-2.6

This commit is contained in:
Mauro Carvalho Chehab 2008-07-27 22:23:18 -03:00
parent f3409f71a7 c9272c4f9f
commit c2f90e9536
81 changed files with 807 additions and 965 deletions
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10
Documentation/arm/Interrupts
View File

@ -138,14 +138,8 @@ So, what's changed?
Set active the IRQ edge(s)/level. This replaces the
SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()
function. Type should be one of the following:
#define IRQT_NOEDGE (0)
#define IRQT_RISING (__IRQT_RISEDGE)
#define IRQT_FALLING (__IRQT_FALEDGE)
#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
#define IRQT_LOW (__IRQT_LOWLVL)
#define IRQT_HIGH (__IRQT_HIGHLVL)
function. Type should be one of IRQ_TYPE_xxx defined in
<linux/irq.h>
3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.

6
arch/arm/Kconfig
View File

@ -314,7 +314,7 @@ config ARCH_IOP32X
select PLAT_IOP
select PCI
select GENERIC_GPIO
select HAVE_GPIO_LIB
select ARCH_REQUIRE_GPIOLIB
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
@ -325,7 +325,7 @@ config ARCH_IOP33X
select PLAT_IOP
select PCI
select GENERIC_GPIO
select HAVE_GPIO_LIB
select ARCH_REQUIRE_GPIOLIB
help
Support for Intel's IOP33X (XScale) family of processors.
@ -418,7 +418,7 @@ config ARCH_MXC
select GENERIC_CLOCKEVENTS
select ARCH_MTD_XIP
select GENERIC_GPIO
select HAVE_GPIO_LIB
select ARCH_REQUIRE_GPIOLIB
help
Support for Freescale MXC/iMX-based family of processors

2
arch/arm/Makefile
View File

@ -67,7 +67,7 @@ tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM946T) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
tune-$(CONFIG_CPU_ARM946E) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi

10
arch/arm/common/locomo.c
View File

@ -331,17 +331,17 @@ static int locomo_gpio_type(unsigned int irq, unsigned int type)
mask = 1 << (irq - LOCOMO_IRQ_GPIO_START);
if (type == IRQT_PROBE) {
if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = __IRQT_RISEDGE | __IRQT_FALEDGE;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & __IRQT_RISEDGE)
if (type & IRQ_TYPE_EDGE_RISING)
GPIO_IRQ_rising_edge |= mask;
else
GPIO_IRQ_rising_edge &= ~mask;
if (type & __IRQT_FALEDGE)
if (type & IRQ_TYPE_EDGE_FALLING)
GPIO_IRQ_falling_edge |= mask;
else
GPIO_IRQ_falling_edge &= ~mask;
@ -473,7 +473,7 @@ static void locomo_setup_irq(struct locomo *lchip)
/*
* Install handler for IRQ_LOCOMO_HW.
*/
set_irq_type(lchip->irq, IRQT_FALLING);
set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_chip_data(lchip->irq, irqbase);
set_irq_chained_handler(lchip->irq, locomo_handler);

14
arch/arm/common/sa1111.c
View File

@ -241,14 +241,14 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip0;
if (flags == IRQT_PROBE)
if (flags == IRQ_TYPE_PROBE)
return 0;
if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0)
if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
return -EINVAL;
ip0 = sa1111_readl(mapbase + SA1111_INTPOL0);
if (flags & __IRQT_RISEDGE)
if (flags & IRQ_TYPE_EDGE_RISING)
ip0 &= ~mask;
else
ip0 |= mask;
@ -338,14 +338,14 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
void __iomem *mapbase = get_irq_chip_data(irq);
unsigned long ip1;
if (flags == IRQT_PROBE)
if (flags == IRQ_TYPE_PROBE)
return 0;
if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0)
if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
return -EINVAL;
ip1 = sa1111_readl(mapbase + SA1111_INTPOL1);
if (flags & __IRQT_RISEDGE)
if (flags & IRQ_TYPE_EDGE_RISING)
ip1 &= ~mask;
else
ip1 |= mask;
@ -427,7 +427,7 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
/*
* Register SA1111 interrupt
*/
set_irq_type(sachip->irq, IRQT_RISING);
set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
set_irq_data(sachip->irq, irqbase);
set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
}

1113
arch/arm/configs/eseries_pxa_defconfig
View File

File diff suppressed because it is too large Load Diff

6
arch/arm/mach-at91/board-cap9adk.c
View File

@ -330,10 +330,10 @@ static void __init cap9adk_board_init(void)
/* Serial */
at91_add_device_serial();
/* USB Host */
set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_usbh(&cap9adk_usbh_data);
/* USB HS */
set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_usba(&cap9adk_usba_udc_data);
/* SPI */
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
@ -350,7 +350,7 @@ static void __init cap9adk_board_init(void)
/* I2C */
at91_add_device_i2c(NULL, 0);
/* LCD Controller */
set_irq_type(AT91CAP9_ID_LCDC, IRQT_HIGH);
set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
at91_add_device_lcdc(&cap9adk_lcdc_data);
/* AC97 */
at91_add_device_ac97(&cap9adk_ac97_data);

0
arch/arm/mach-at91/board-yl-9200.c Executable file → Normal file
View File

8
arch/arm/mach-at91/irq.c
View File

@ -56,19 +56,19 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
unsigned int smr, srctype;
switch (type) {
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
srctype = AT91_AIC_SRCTYPE_HIGH;
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
srctype = AT91_AIC_SRCTYPE_RISING;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_LOW;
else
return -EINVAL;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_FALLING;
else

14
arch/arm/mach-ep93xx/core.c
View File

@ -226,7 +226,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
int port = line >> 3;
int port_mask = 1 << (line & 7);
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
ep93xx_gpio_update_int_params(port);
}
@ -240,7 +240,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
int port = line >> 3;
int port_mask = 1 << (line & 7);
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE)
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
gpio_int_unmasked[port] &= ~port_mask;
@ -283,27 +283,27 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
gpio_direction_input(gpio);
switch (type) {
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
gpio_int_type1[port] |= port_mask;
gpio_int_type2[port] |= port_mask;
desc->handle_irq = handle_edge_irq;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
gpio_int_type1[port] |= port_mask;
gpio_int_type2[port] &= ~port_mask;
desc->handle_irq = handle_edge_irq;
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
gpio_int_type1[port] &= ~port_mask;
gpio_int_type2[port] |= port_mask;
desc->handle_irq = handle_level_irq;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
gpio_int_type1[port] &= ~port_mask;
gpio_int_type2[port] &= ~port_mask;
desc->handle_irq = handle_level_irq;
break;
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
gpio_int_type1[port] |= port_mask;
/* set initial polarity based on current input level */
if (gpio_get_value(gpio))

12
arch/arm/mach-imx/irq.c
View File

@ -111,7 +111,7 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type)
reg = irq >> 5;
bit = 1 << (irq % 32);
if (type == IRQT_PROBE) {
if (type == IRQ_TYPE_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or
GPIOs set to alternate function during probe */
/* TODO: support probe */
@ -120,7 +120,7 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type)
// return 0;
// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
// return 0;
// type = __IRQT_RISEDGE | __IRQT_FALEDGE;
// type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
GIUS(reg) |= bit;
@ -128,19 +128,19 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type)
DEBUG_IRQ("setting type of irq %d to ", _irq);
if (type & __IRQT_RISEDGE) {
if (type & IRQ_TYPE_EDGE_RISING) {
DEBUG_IRQ("rising edges\n");
irq_type = 0x0;
}
if (type & __IRQT_FALEDGE) {
if (type & IRQ_TYPE_EDGE_FALLING) {
DEBUG_IRQ("falling edges\n");
irq_type = 0x1;
}
if (type & __IRQT_LOWLVL) {
if (type & IRQ_TYPE_LEVEL_LOW) {
DEBUG_IRQ("low level\n");
irq_type = 0x3;
}
if (type & __IRQT_HIGHLVL) {
if (type & IRQ_TYPE_LEVEL_HIGH) {
DEBUG_IRQ("high level\n");
irq_type = 0x2;
}

8
arch/arm/mach-ixp2000/core.c
View File

@ -329,19 +329,19 @@ static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
/*
* Then, set the proper trigger type.
*/
if (type & IRQT_FALLING)
if (type & IRQ_TYPE_EDGE_FALLING)
GPIO_IRQ_falling_edge |= 1 << line;
else
GPIO_IRQ_falling_edge &= ~(1 << line);
if (type & IRQT_RISING)
if (type & IRQ_TYPE_EDGE_RISING)
GPIO_IRQ_rising_edge |= 1 << line;
else
GPIO_IRQ_rising_edge &= ~(1 << line);
if (type & IRQT_LOW)
if (type & IRQ_TYPE_LEVEL_LOW)
GPIO_IRQ_level_low |= 1 << line;
else
GPIO_IRQ_level_low &= ~(1 << line);
if (type & IRQT_HIGH)
if (type & IRQ_TYPE_LEVEL_HIGH)
GPIO_IRQ_level_high |= 1 << line;
else
GPIO_IRQ_level_high &= ~(1 << line);

10
arch/arm/mach-ixp23xx/core.c
View File

@ -126,23 +126,23 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
return -EINVAL;
switch (type) {
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
irq_type = IXP23XX_IRQ_EDGE;
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
irq_type = IXP23XX_IRQ_EDGE;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
irq_type = IXP23XX_IRQ_EDGE;
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
irq_type = IXP23XX_IRQ_LEVEL;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
irq_type = IXP23XX_IRQ_LEVEL;
break;

4
arch/arm/mach-ixp23xx/roadrunner.c
View File

@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
static void __init roadrunner_pci_preinit(void)
{
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp23xx_pci_preinit();
}

8
arch/arm/mach-ixp4xx/avila-pci.c
View File

@ -30,10 +30,10 @@
void __init avila_pci_preinit(void)
{
set_irq_type(IRQ_AVILA_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_AVILA_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_AVILA_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_AVILA_PCI_INTD, IRQT_LOW);
set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

10
arch/arm/mach-ixp4xx/common.c
View File

@ -142,23 +142,23 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
return -EINVAL;
switch (type){
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
irq_type = IXP4XX_IRQ_EDGE;
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
irq_type = IXP4XX_IRQ_EDGE;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
irq_type = IXP4XX_IRQ_EDGE;
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
irq_type = IXP4XX_IRQ_LEVEL;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
irq_type = IXP4XX_IRQ_LEVEL;
break;

4
arch/arm/mach-ixp4xx/coyote-pci.c
View File

@ -27,8 +27,8 @@
void __init coyote_pci_preinit(void)
{
set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW);
set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW);
set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

12
arch/arm/mach-ixp4xx/dsmg600-pci.c
View File

@ -25,12 +25,12 @@
void __init dsmg600_pci_preinit(void)
{
set_irq_type(IRQ_DSMG600_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTD, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTE, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTF, IRQT_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

6
arch/arm/mach-ixp4xx/fsg-pci.c
View File

@ -25,9 +25,9 @@
void __init fsg_pci_preinit(void)
{
set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/gateway7001-pci.c
View File

@ -29,8 +29,8 @@
void __init gateway7001_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

8
arch/arm/mach-ixp4xx/gtwx5715-pci.c
View File

@ -41,10 +41,10 @@
*/
void __init gtwx5715_pci_preinit(void)
{
set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW);
set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW);
set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW);
set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

8
arch/arm/mach-ixp4xx/ixdp425-pci.c
View File

@ -27,10 +27,10 @@
void __init ixdp425_pci_preinit(void)
{
set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/ixdpg425-pci.c
View File

@ -25,8 +25,8 @@
void __init ixdpg425_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

10
arch/arm/mach-ixp4xx/nas100d-pci.c
View File

@ -24,11 +24,11 @@
void __init nas100d_pci_preinit(void)
{
set_irq_type(IRQ_NAS100D_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTD, IRQT_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTE, IRQT_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

6
arch/arm/mach-ixp4xx/nslu2-pci.c
View File

@ -24,9 +24,9 @@
void __init nslu2_pci_preinit(void)
{
set_irq_type(IRQ_NSLU2_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/wg302v2-pci.c
View File

@ -29,8 +29,8 @@
void __init wg302v2_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

10
arch/arm/mach-ks8695/irq.c
View File

@ -72,21 +72,21 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type)
ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
switch (type) {
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
mode = IOPC_TM_HIGH;
level_triggered = 1;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
mode = IOPC_TM_LOW;
level_triggered = 1;
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
mode = IOPC_TM_RISING;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
mode = IOPC_TM_FALLING;
break;
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
mode = IOPC_TM_EDGE;
break;
default:

8
arch/arm/mach-netx/generic.c
View File

@ -99,19 +99,19 @@ netx_hif_irq_type(unsigned int _irq, unsigned int type)
irq = _irq - NETX_IRQ_HIF_CHAINED(0);
if (type & __IRQT_RISEDGE) {
if (type & IRQ_TYPE_EDGE_RISING) {
DEBUG_IRQ("rising edges\n");
val |= (1 << 26) << irq;
}
if (type & __IRQT_FALEDGE) {
if (type & IRQ_TYPE_EDGE_FALLING) {
DEBUG_IRQ("falling edges\n");
val &= ~((1 << 26) << irq);
}
if (type & __IRQT_LOWLVL) {
if (type & IRQ_TYPE_LEVEL_LOW) {
DEBUG_IRQ("low level\n");
val &= ~((1 << 26) << irq);
}
if (type & __IRQT_HIGHLVL) {
if (type & IRQ_TYPE_LEVEL_HIGH) {
DEBUG_IRQ("high level\n");
val |= (1 << 26) << irq;
}

6
arch/arm/mach-omap1/board-osk.c
View File

@ -288,7 +288,7 @@ static void __init osk_init_cf(void)
return;
}
/* the CF I/O IRQ is really active-low */
set_irq_type(OMAP_GPIO_IRQ(62), IRQT_FALLING);
set_irq_type(OMAP_GPIO_IRQ(62), IRQ_TYPE_EDGE_FALLING);
}
static void __init osk_init_irq(void)
@ -483,7 +483,7 @@ static void __init osk_mistral_init(void)
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
gpio_request(4, "ts_int");
gpio_direction_input(4);
set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
set_irq_type(OMAP_GPIO_IRQ(4), IRQ_TYPE_EDGE_FALLING);
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
@ -494,7 +494,7 @@ static void __init osk_mistral_init(void)
int ret = 0;
gpio_direction_input(OMAP_MPUIO(2));
set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the
* button for more than wakeup from system sleep.

4
arch/arm/mach-omap1/board-palmz71.c
View File

@ -298,11 +298,11 @@ palmz71_powercable(int irq, void *dev_id)
if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) {
printk(KERN_INFO "PM: Power cable connected\n");
set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO),
IRQT_FALLING);
IRQ_TYPE_EDGE_FALLING);
} else {
printk(KERN_INFO "PM: Power cable disconnected\n");
set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO),
IRQT_RISING);
IRQ_TYPE_EDGE_RISING);
}
return IRQ_HANDLED;
}

8
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -186,10 +186,10 @@ static void __init voiceblue_init(void)
omap_request_gpio(13);
omap_request_gpio(14);
omap_request_gpio(15);
set_irq_type(OMAP_GPIO_IRQ(12), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(14), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(15), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(OMAP_GPIO_IRQ(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(OMAP_GPIO_IRQ(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;

2
arch/arm/mach-omap1/fpga.c
View File

@ -181,7 +181,7 @@ void omap1510_fpga_init_irq(void)
*/
omap_request_gpio(13);
omap_set_gpio_direction(13, 1);
set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
}

6
arch/arm/mach-omap2/board-apollon.c
View File

@ -337,17 +337,17 @@ static void __init apollon_sw_init(void)
omap_request_gpio(SW_DOWN_GPIO58);
omap_set_gpio_direction(SW_DOWN_GPIO58, 1);
set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt,
IRQF_SHARED, "enter sw",
&apollon_sw_interrupt))
return;
set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_UP_GPIO17), &apollon_sw_interrupt,
IRQF_SHARED, "up sw",
&apollon_sw_interrupt))
return;
set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQT_RISING);
set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQ_TYPE_EDGE_RISING);
if (request_irq(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), &apollon_sw_interrupt,
IRQF_SHARED, "down sw",
&apollon_sw_interrupt))

4
arch/arm/mach-orion5x/db88f5281-setup.c
View File

@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield "
"to set_irq_type pin %d\n", pin);

12
arch/arm/mach-orion5x/irq.c
View File

@ -91,27 +91,27 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
desc = irq_desc + irq;
switch (type) {
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
/*
@ -156,7 +156,7 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
if (cause & (1 << pin)) {
irq = gpio_to_irq(pin);
desc = irq_desc + irq;
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
/* Swap polarity (race with GPIO line) */
u32 polarity = readl(GPIO_IN_POL);
polarity ^= 1 << pin;

4
arch/arm/mach-orion5x/rd88f5182-setup.c
View File

@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);

4
arch/arm/mach-orion5x/ts209-setup.c
View File

@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed "
"to set_irq_type pin %d\n", pin);

10
arch/arm/mach-pnx4008/irq.c
View File

@ -56,28 +56,28 @@ static void pnx4008_mask_ack_irq(unsigned int irq)
static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
{
switch (type) {
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
set_irq_handler(irq, handle_edge_irq);
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
set_irq_handler(irq, handle_edge_irq);
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
set_irq_handler(irq, handle_level_irq);
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
set_irq_handler(irq, handle_level_irq);
break;
/* IRQT_BOTHEDGE is not supported */
/* IRQ_TYPE_EDGE_BOTH is not supported */
default:
printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
return -1;

2
arch/arm/mach-pxa/cm-x270-pci.c
View File

@ -71,7 +71,7 @@ void __cmx270_pci_init_irq(int irq_gpio)
cmx270_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING);
set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
}

2
arch/arm/mach-pxa/lpd270.c
View File

@ -113,7 +113,7 @@ static void __init lpd270_init_irq(void)
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}

2
arch/arm/mach-pxa/lubbock.c
View File

@ -152,7 +152,7 @@ static void __init lubbock_init_irq(void)
}
set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM

2
arch/arm/mach-pxa/mainstone.c
View File

@ -191,7 +191,7 @@ static void __init mainstone_init_irq(void)
MST_INTSETCLR = 0;
set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM

8
arch/arm/mach-pxa/sharpsl_pm.c
View File

@ -146,18 +146,18 @@ void sharpsl_pm_pxa_init(void)
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQT_BOTHEDGE);
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQ_TYPE_EDGE_BOTH);
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQT_FALLING);
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQ_TYPE_EDGE_FALLING);
if (sharpsl_pm.machinfo->gpio_fatal) {
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQT_FALLING);
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQ_TYPE_EDGE_FALLING);
}
if (sharpsl_pm.machinfo->batfull_irq)
@ -166,7 +166,7 @@ void sharpsl_pm_pxa_init(void)
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQT_RISING);
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQ_TYPE_EDGE_RISING);
}
}

2
arch/arm/mach-pxa/trizeps4.c
View File

@ -122,7 +122,7 @@ static struct resource dm9000_resources[] = {
[2] = {
.start = TRIZEPS4_ETH_IRQ,
.end = TRIZEPS4_ETH_IRQ,
.flags = (IORESOURCE_IRQ | IRQT_RISING),
.flags = (IORESOURCE_IRQ | IRQ_TYPE_EDGE_RISING),
},
};

2
arch/arm/mach-sa1100/cerf.c
View File

@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = {
static void __init cerf_init_irq(void)
{
sa1100_init_irq();
set_irq_type(CERF_ETH_IRQ, IRQT_RISING);
set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
}
static struct map_desc cerf_io_desc[] __initdata = {

2
arch/arm/mach-sa1100/h3600.c
View File

@ -834,7 +834,7 @@ static void __init h3800_init_irq(void)
set_irq_chip(irq, &h3800_gpio_irqchip);
}
#endif
set_irq_type(IRQ_GPIO_H3800_ASIC, IRQT_RISING);
set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux);
}

8
arch/arm/mach-sa1100/irq.c
View File

@ -46,17 +46,17 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type)
else
mask = GPIO11_27_MASK(irq);
if (type == IRQT_PROBE) {
if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = __IRQT_RISEDGE | __IRQT_FALEDGE;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & __IRQT_RISEDGE) {
if (type & IRQ_TYPE_EDGE_RISING) {
GPIO_IRQ_rising_edge |= mask;
} else
GPIO_IRQ_rising_edge &= ~mask;
if (type & __IRQT_FALEDGE) {
if (type & IRQ_TYPE_EDGE_FALLING) {
GPIO_IRQ_falling_edge |= mask;
} else
GPIO_IRQ_falling_edge &= ~mask;

2
arch/arm/mach-sa1100/neponset.c
View File

@ -151,7 +151,7 @@ static int __devinit neponset_probe(struct platform_device *dev)
/*
* Install handler for GPIO25.
*/
set_irq_type(IRQ_GPIO25, IRQT_RISING);
set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);
/*

2
arch/arm/mach-sa1100/pleb.c
View File

@ -143,7 +143,7 @@ static void __init pleb_map_io(void)
GPDR &= ~GPIO_ETH0_IRQ;
set_irq_type(GPIO_ETH0_IRQ, IRQT_FALLING);
set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
}
MACHINE_START(PLEB, "PLEB")

10
arch/arm/mm/fault-armv.c
View File

@ -37,7 +37,7 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
pgd_t *pgd;
pmd_t *pmd;
pte_t *pte, entry;
int ret = 0;
int ret;
pgd = pgd_offset(vma->vm_mm, address);
if (pgd_none(*pgd))
@ -54,16 +54,20 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
pte = pte_offset_map(pmd, address);
entry = *pte;
/*
* If this page is present, it's actually being shared.
*/
ret = pte_present(entry);
/*
* If this page isn't present, or is already setup to
* fault (ie, is old), we can safely ignore any issues.
*/
if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
if (ret && pte_val(entry) & shared_pte_mask) {
flush_cache_page(vma, address, pte_pfn(entry));
pte_val(entry) &= ~shared_pte_mask;
set_pte_at(vma->vm_mm, address, pte, entry);
flush_tlb_page(vma, address);
ret = 1;
}
pte_unmap(pte);
return ret;

10
arch/arm/plat-mxc/gpio.c
View File

@ -73,19 +73,19 @@ static int gpio_set_irq_type(u32 irq, u32 type)
void __iomem *reg = port->base;
switch (type) {
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
edge = GPIO_INT_FALL_EDGE;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
edge = GPIO_INT_HIGH_LEV;
break;
default: /* this includes IRQT_BOTHEDGE */
default: /* this includes IRQ_TYPE_EDGE_BOTH */
return -EINVAL;
}

28
arch/arm/plat-omap/gpio.c
View File

@ -517,13 +517,13 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
u32 gpio_bit = 1 << gpio;
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
trigger & __IRQT_LOWLVL);
trigger & IRQ_TYPE_LEVEL_LOW);
MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
trigger & __IRQT_HIGHLVL);
trigger & IRQ_TYPE_LEVEL_HIGH);
MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
trigger & __IRQT_RISEDGE);
trigger & IRQ_TYPE_EDGE_RISING);
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
trigger & __IRQT_FALEDGE);
trigger & IRQ_TYPE_EDGE_FALLING);
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (trigger != 0)
@ -555,9 +555,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_INT_EDGE;
l = __raw_readl(reg);
if (trigger & __IRQT_RISEDGE)
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & __IRQT_FALEDGE)
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
@ -567,9 +567,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
l = __raw_readl(reg);
if (trigger & __IRQT_RISEDGE)
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & __IRQT_FALEDGE)
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
@ -584,9 +584,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
gpio &= 0x07;
l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
if (trigger & __IRQT_RISEDGE)
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 2 << (gpio << 1);
if (trigger & __IRQT_FALEDGE)
if (trigger & IRQ_TYPE_EDGE_FALLING)
l |= 1 << (gpio << 1);
if (trigger)
/* Enable wake-up during idle for dynamic tick */
@ -599,9 +599,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_CONTROL;
l = __raw_readl(reg);
if (trigger & __IRQT_RISEDGE)
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & __IRQT_FALEDGE)
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
@ -887,7 +887,7 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
_set_gpio_irqenable(bank, gpio, 0);
_clear_gpio_irqstatus(bank, gpio);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
@ -924,7 +924,7 @@ int omap_request_gpio(int gpio)
/* Set trigger to none. You need to enable the desired trigger with
* request_irq() or set_irq_type().
*/
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
#ifdef CONFIG_ARCH_OMAP15XX
if (bank->method == METHOD_GPIO_1510) {

2
arch/arm/plat-s3c24xx/Kconfig
View File

@ -9,7 +9,7 @@ config PLAT_S3C24XX
depends on ARCH_S3C2410
default y if ARCH_S3C2410
select NO_IOPORT
select HAVE_GPIO_LIB
select ARCH_REQUIRE_GPIOLIB
help
Base platform code for any Samsung S3C24XX device

12
arch/arm/plat-s3c24xx/irq.c
View File

@ -292,27 +292,27 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
/* Set the external interrupt to pointed trigger type */
switch (type)
{
case IRQT_NOEDGE:
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQT_RISING:
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQT_FALLING:
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQT_BOTHEDGE:
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQT_LOW:
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQT_HIGH:
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;

8
arch/x86/kernel/head_32.S
View File

@ -456,9 +456,6 @@ is386: movl $2,%ecx # set MP
1:
#endif /* CONFIG_SMP */
jmp *(initial_code)
.align 4
ENTRY(initial_code)
.long i386_start_kernel
/*
* We depend on ET to be correct. This checks for 287/387.
@ -601,6 +598,11 @@ ignore_int:
#endif
iret
.section .cpuinit.data,"wa"
.align 4
ENTRY(initial_code)
.long i386_start_kernel
.section .text
/*
* Real beginning of normal "text" segment

2
drivers/ata/pata_ixp4xx_cf.c
View File

@ -169,7 +169,7 @@ static __devinit int ixp4xx_pata_probe(struct platform_device *pdev)
irq = platform_get_irq(pdev, 0);
if (irq)
set_irq_type(irq, IRQT_RISING);
set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
/* Setup expansion bus chip selects */
*data->cs0_cfg = data->cs0_bits;

6
drivers/char/nwflash.c
View File

@ -125,15 +125,15 @@ static ssize_t flash_read(struct file *file, char __user *buf, size_t size,
ssize_t ret;
if (flashdebug)
printk(KERN_DEBUG "flash_read: flash_read: offset=0x%lX, "
"buffer=%p, count=0x%X.\n", p, buf, count);
printk(KERN_DEBUG "flash_read: flash_read: offset=0x%llx, "
"buffer=%p, count=0x%zx.\n", *ppos, buf, size);
/*
* We now lock against reads and writes. --rmk
*/
if (mutex_lock_interruptible(&nwflash_mutex))
return -ERESTARTSYS;
ret = simple_read_from_buffer(buf, size, ppos, FLASH_BASE, gbFlashSize);
ret = simple_read_from_buffer(buf, size, ppos, (void *)FLASH_BASE, gbFlashSize);
mutex_unlock(&nwflash_mutex);
return ret;

8
drivers/input/touchscreen/corgi_ts.c
View File

@ -195,7 +195,7 @@ static void ts_interrupt_main(struct corgi_ts *corgi_ts, int isTimer)
{
if ((GPLR(IRQ_TO_GPIO(corgi_ts->irq_gpio)) & GPIO_bit(IRQ_TO_GPIO(corgi_ts->irq_gpio))) == 0) {
/* Disable Interrupt */
set_irq_type(corgi_ts->irq_gpio, IRQT_NOEDGE);
set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_NONE);
if (read_xydata(corgi_ts)) {
corgi_ts->pendown = 1;
new_data(corgi_ts);
@ -214,7 +214,7 @@ static void ts_interrupt_main(struct corgi_ts *corgi_ts, int isTimer)
}
/* Enable Falling Edge */
set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
corgi_ts->pendown = 0;
}
}
@ -258,7 +258,7 @@ static int corgits_resume(struct platform_device *dev)
corgi_ssp_ads7846_putget((4u << ADSCTRL_ADR_SH) | ADSCTRL_STS);
/* Enable Falling Edge */
set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
corgi_ts->power_mode = PWR_MODE_ACTIVE;
return 0;
@ -333,7 +333,7 @@ static int __init corgits_probe(struct platform_device *pdev)
corgi_ts->power_mode = PWR_MODE_ACTIVE;
/* Enable Falling Edge */
set_irq_type(corgi_ts->irq_gpio, IRQT_FALLING);
set_irq_type(corgi_ts->irq_gpio, IRQ_TYPE_EDGE_FALLING);
return 0;

2
drivers/input/touchscreen/mainstone-wm97xx.c
View File

@ -198,7 +198,7 @@ static int wm97xx_acc_startup(struct wm97xx *wm)
switch (wm->id) {
case WM9705_ID2:
wm->pen_irq = IRQ_GPIO(4);
set_irq_type(IRQ_GPIO(4), IRQT_BOTHEDGE);
set_irq_type(IRQ_GPIO(4), IRQ_TYPE_EDGE_BOTH);
break;
case WM9712_ID2:
case WM9713_ID2:

14
drivers/mfd/asic3.c
View File

@ -256,28 +256,28 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
bank + ASIC3_GPIO_TRIGGER_TYPE);
asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
if (type == IRQT_RISING) {
if (type == IRQ_TYPE_EDGE_RISING) {
trigger |= bit;
edge |= bit;
} else if (type == IRQT_FALLING) {
} else if (type == IRQ_TYPE_EDGE_FALLING) {
trigger |= bit;
edge &= ~bit;
} else if (type == IRQT_BOTHEDGE) {
} else if (type == IRQ_TYPE_EDGE_BOTH) {
trigger |= bit;
if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
edge &= ~bit;
else
edge |= bit;
asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
} else if (type == IRQT_LOW) {
} else if (type == IRQ_TYPE_LEVEL_LOW) {
trigger &= ~bit;
level &= ~bit;
} else if (type == IRQT_HIGH) {
} else if (type == IRQ_TYPE_LEVEL_HIGH) {
trigger &= ~bit;
level |= bit;
} else {
/*
* if type == IRQT_NOEDGE, we should mask interrupts, but
* if type == IRQ_TYPE_NONE, we should mask interrupts, but
* be careful to not unmask them if mask was also called.
* Probably need internal state for mask.
*/
@ -343,7 +343,7 @@ static int __init asic3_irq_probe(struct platform_device *pdev)
ASIC3_INTMASK_GINTMASK);
set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
set_irq_type(asic->irq_nr, IRQT_RISING);
set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
set_irq_data(asic->irq_nr, asic);
return 0;

2
drivers/mfd/tc6393xb.c
View File

@ -324,7 +324,7 @@ static void tc6393xb_attach_irq(struct platform_device *dev)
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_type(tc6393xb->irq, IRQT_FALLING);
set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_data(tc6393xb->irq, tc6393xb);
set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
}

12
drivers/pcmcia/soc_common.c
View File

@ -149,10 +149,10 @@ soc_common_pcmcia_config_skt(struct soc_pcmcia_socket *skt, socket_state_t *stat
*/
if (skt->irq_state != 1 && state->io_irq) {
skt->irq_state = 1;
set_irq_type(skt->irq, IRQT_FALLING);
set_irq_type(skt->irq, IRQ_TYPE_EDGE_FALLING);
} else if (skt->irq_state == 1 && state->io_irq == 0) {
skt->irq_state = 0;
set_irq_type(skt->irq, IRQT_NOEDGE);
set_irq_type(skt->irq, IRQ_TYPE_NONE);
}
skt->cs_state = *state;
@ -527,7 +527,7 @@ int soc_pcmcia_request_irqs(struct soc_pcmcia_socket *skt,
IRQF_DISABLED, irqs[i].str, skt);
if (res)
break;
set_irq_type(irqs[i].irq, IRQT_NOEDGE);
set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
}
if (res) {
@ -560,7 +560,7 @@ void soc_pcmcia_disable_irqs(struct soc_pcmcia_socket *skt,
for (i = 0; i < nr; i++)
if (irqs[i].sock == skt->nr)
set_irq_type(irqs[i].irq, IRQT_NOEDGE);
set_irq_type(irqs[i].irq, IRQ_TYPE_NONE);
}
EXPORT_SYMBOL(soc_pcmcia_disable_irqs);
@ -571,8 +571,8 @@ void soc_pcmcia_enable_irqs(struct soc_pcmcia_socket *skt,
for (i = 0; i < nr; i++)
if (irqs[i].sock == skt->nr) {
set_irq_type(irqs[i].irq, IRQT_RISING);
set_irq_type(irqs[i].irq, IRQT_BOTHEDGE);
set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_RISING);
set_irq_type(irqs[i].irq, IRQ_TYPE_EDGE_BOTH);
}
}
EXPORT_SYMBOL(soc_pcmcia_enable_irqs);

2
drivers/video/am200epd.c
View File

@ -221,7 +221,7 @@ static int am200_setup_irq(struct fb_info *info)
return retval;
}
return set_irq_type(IRQ_GPIO(RDY_GPIO_PIN), IRQT_FALLING);
return set_irq_type(IRQ_GPIO(RDY_GPIO_PIN), IRQ_TYPE_EDGE_FALLING);
}
static void am200_set_rst(struct metronomefb_par *par, int state)

2
drivers/video/omap/sossi.c
View File

@ -646,7 +646,7 @@ static int sossi_init(struct omapfb_device *fbdev)
sossi_write_reg(SOSSI_INIT1_REG, l);
if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
IRQT_FALLING,
IRQ_TYPE_EDGE_FALLING,
"sossi_match", sossi.fbdev->dev)) < 0) {
dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
goto err;

2
drivers/video/pxafb.c
View File

@ -1336,7 +1336,7 @@ static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
fbi->dma_buff_phys = fbi->map_dma;
fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi->palette_size*sizeof(u16));
pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
#ifdef CONFIG_FB_PXA_SMARTPANEL
fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;

6
fs/nfs/super.c
View File

@ -1718,9 +1718,9 @@ nfs_remount(struct super_block *sb, int *flags, char *raw_data)
* ones were explicitly specified. Fall back to legacy behavior and
* just return success.
*/
if ((nfsvers == 4 && options4->version == 1) ||
(nfsvers <= 3 && options->version >= 1 &&
options->version <= 6))
if ((nfsvers == 4 && (!options4 || options4->version == 1)) ||
(nfsvers <= 3 && (!options || (options->version >= 1 &&
options->version <= 6))))
return 0;
data = kzalloc(sizeof(*data), GFP_KERNEL);

3
fs/nfs/unlink.c
View File

@ -95,10 +95,11 @@ static void nfs_async_unlink_done(struct rpc_task *task, void *calldata)
static void nfs_async_unlink_release(void *calldata)
{
struct nfs_unlinkdata *data = calldata;
struct super_block *sb = data->dir->i_sb;
nfs_dec_sillycount(data->dir);
nfs_sb_deactive(NFS_SERVER(data->dir));
nfs_free_unlinkdata(data);
nfs_sb_deactive(NFS_SB(sb));
}
static const struct rpc_call_ops nfs_unlink_ops = {

10
fs/proc/base.c
View File

@ -2403,7 +2403,7 @@ static int proc_base_fill_cache(struct file *filp, void *dirent,
#ifdef CONFIG_TASK_IO_ACCOUNTING
static int do_io_accounting(struct task_struct *task, char *buffer, int whole)
{
struct proc_io_accounting acct = task->ioac;
struct task_io_accounting acct = task->ioac;
unsigned long flags;
if (whole && lock_task_sighand(task, &flags)) {
@ -2423,10 +2423,10 @@ static int do_io_accounting(struct task_struct *task, char *buffer, int whole)
"read_bytes: %llu\n"
"write_bytes: %llu\n"
"cancelled_write_bytes: %llu\n",
acct.chr.rchar, acct.chr.wchar,
acct.chr.syscr, acct.chr.syscw,
acct.blk.read_bytes, acct.blk.write_bytes,
acct.blk.cancelled_write_bytes);
acct.rchar, acct.wchar,
acct.syscr, acct.syscw,
acct.read_bytes, acct.write_bytes,
acct.cancelled_write_bytes);
}
static int proc_tid_io_accounting(struct task_struct *task, char *buffer)

48
include/asm-arm/arch-pnx4008/irqs.h
View File

@ -135,30 +135,30 @@
#define PNX4008_IRQ_TYPES \
{ /*IRQ #'s: */ \
IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
}
/* Start Enable Pin Interrupts - table 58 page 66 */

10
include/asm-arm/arch-pxa/idp.h
View File

@ -138,18 +138,18 @@
#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
#define IDE_IRQ IRQ_GPIO(21)
#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING
#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define ETHERNET_IRQ IRQ_GPIO(4)
#define ETHERNET_IRQ_EDGE IRQT_RISING
#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define IDE_IRQ_EDGE IRQT_RISING
#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
#define PCMCIA_S1_RDYINT IRQ_GPIO(22)

14
include/asm-arm/arch-pxa/pcm990_baseboard.h
View File

@ -29,14 +29,14 @@
/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
#define PCM990_CTRL_INT_IRQ_GPIO 9
#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
#define PCM990_CTRL_BASE 0xea000000
#define PCM990_CTRL_SIZE (1*1024*1024)
#define PCM990_CTRL_PWR_IRQ_GPIO 14
#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/* visible CPLD (U7) registers */
#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
@ -133,7 +133,7 @@
*/
#define PCM990_IDE_IRQ_GPIO 13
#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
#define PCM990_IDE_IRQ_EDGE IRQT_RISING
#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
#define PCM990_IDE_PLD_BASE 0xee000000
#define PCM990_IDE_PLD_SIZE (1*1024*1024)
@ -189,11 +189,11 @@
*/
#define PCM990_CF_IRQ_GPIO 11
#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
#define PCM990_CF_IRQ_EDGE IRQT_RISING
#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_CD_GPIO 12
#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
#define PCM990_CF_CD_EDGE IRQT_RISING
#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
#define PCM990_CF_PLD_BASE 0xef000000
@ -259,14 +259,14 @@
*/
#define PCM990_AC97_IRQ_GPIO 10
#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
#define PCM990_AC97_IRQ_EDGE IRQT_RISING
#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/*
* MMC phyCORE
*/
#define PCM990_MMC0_IRQ_GPIO 9
#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
/*
* USB phyCore

2
include/asm-arm/arch-pxa/pxa25x-udc.h
View File

@ -2,7 +2,7 @@
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
#error You can't include both PXA25x and PXA27x UDC support
#error "You can't include both PXA25x and PXA27x UDC support"
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */

2
include/asm-arm/arch-sa1100/ide.h
View File

@ -61,7 +61,7 @@ ide_init_default_hwifs(void)
/* Enable GPIO as interrupt line */
GPDR &= ~LART_GPIO_IDE;
set_irq_type(LART_IRQ_IDE, IRQT_RISING);
set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
/* set PCMCIA interface timing */
MECR = 0x00060006;

9
include/asm-arm/bitops.h
View File

@ -277,9 +277,16 @@ static inline int constant_fls(int x)
* the clz instruction for much better code efficiency.
*/
#define fls(x) \
#define __fls(x) \
( __builtin_constant_p(x) ? constant_fls(x) : \
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
/* Implement fls() in C so that 64-bit args are suitably truncated */
static inline int fls(int x)
{
return __fls(x);
}
#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
#define __ffs(x) (ffs(x) - 1)
#define ffz(x) __ffs( ~(x) )

17
include/asm-arm/cacheflush.h
View File

@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
/*
* VIVT caches only
*/
#define cache_is_vivt() 1
#define cache_is_vipt() 0
#define cache_is_vipt_nonaliasing() 0
#define cache_is_vipt_aliasing() 0
#define icache_is_vivt_asid_tagged() 0
#elif defined(CONFIG_CPU_CACHE_VIPT)
#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
/*
* VIPT caches only
*/
#define cache_is_vivt() 0
#define cache_is_vipt() 1
#define cache_is_vipt_nonaliasing() \
@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
})
#else
/*
* VIVT or VIPT caches. Note that this is unreliable since ARM926
* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
* There's no way to tell from the CacheType register what type (!)
* the cache is.
*/
#define cache_is_vivt() \
({ \
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \

17
include/asm-arm/irq.h
View File

@ -19,23 +19,6 @@
#define NO_IRQ ((unsigned int)(-1))
#endif
/*
* Migration helpers
*/
#define __IRQT_FALEDGE IRQ_TYPE_EDGE_FALLING
#define __IRQT_RISEDGE IRQ_TYPE_EDGE_RISING
#define __IRQT_LOWLVL IRQ_TYPE_LEVEL_LOW
#define __IRQT_HIGHLVL IRQ_TYPE_LEVEL_HIGH
#define IRQT_NOEDGE (0)
#define IRQT_RISING (__IRQT_RISEDGE)
#define IRQT_FALLING (__IRQT_FALEDGE)
#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
#define IRQT_LOW (__IRQT_LOWLVL)
#define IRQT_HIGH (__IRQT_HIGHLVL)
#define IRQT_PROBE IRQ_TYPE_PROBE
#ifndef __ASSEMBLY__
struct irqaction;
extern void migrate_irqs(void);

8
include/asm-arm/pci.h
View File

@ -78,6 +78,14 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res)
return root;
}
/*
* Dummy implementation; always return 0.
*/
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
return 0;
}
#endif /* __KERNEL__ */
#endif

12
include/linux/sched.h
View File

@ -505,7 +505,7 @@ struct signal_struct {
unsigned long nvcsw, nivcsw, cnvcsw, cnivcsw;
unsigned long min_flt, maj_flt, cmin_flt, cmaj_flt;
unsigned long inblock, oublock, cinblock, coublock;
struct proc_io_accounting ioac;
struct task_io_accounting ioac;
/*
* Cumulative ns of scheduled CPU time for dead threads in the
@ -1253,7 +1253,7 @@ struct task_struct {
unsigned long ptrace_message;
siginfo_t *last_siginfo; /* For ptrace use. */
struct proc_io_accounting ioac;
struct task_io_accounting ioac;
#if defined(CONFIG_TASK_XACCT)
u64 acct_rss_mem1; /* accumulated rss usage */
u64 acct_vm_mem1; /* accumulated virtual memory usage */
@ -2183,22 +2183,22 @@ extern long sched_group_rt_period(struct task_group *tg);
#ifdef CONFIG_TASK_XACCT
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)
{
tsk->ioac.chr.rchar += amt;
tsk->ioac.rchar += amt;
}
static inline void add_wchar(struct task_struct *tsk, ssize_t amt)
{
tsk->ioac.chr.wchar += amt;
tsk->ioac.wchar += amt;
}
static inline void inc_syscr(struct task_struct *tsk)
{
tsk->ioac.chr.syscr++;
tsk->ioac.syscr++;
}
static inline void inc_syscw(struct task_struct *tsk)
{
tsk->ioac.chr.syscw++;
tsk->ioac.syscw++;
}
#else
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)

17
include/linux/task_io_accounting.h
View File

@ -1,5 +1,5 @@
/*
* proc_io_accounting: a structure which is used for recording a single task's
* task_io_accounting: a structure which is used for recording a single task's
* IO statistics.
*
* Don't include this header file directly - it is designed to be dragged in via
@ -8,8 +8,8 @@
* Blame akpm@osdl.org for all this.
*/
struct task_io_accounting {
#ifdef CONFIG_TASK_XACCT
struct task_chr_io_accounting {
/* bytes read */
u64 rchar;
/* bytes written */
@ -18,14 +18,9 @@ struct task_chr_io_accounting {
u64 syscr;
/* # of write syscalls */
u64 syscw;
};
#else /* CONFIG_TASK_XACCT */
struct task_chr_io_accounting {
};
#endif /* CONFIG_TASK_XACCT */
#ifdef CONFIG_TASK_IO_ACCOUNTING
struct task_io_accounting {
/*
* The number of bytes which this task has caused to be read from
* storage.
@ -46,13 +41,5 @@ struct task_io_accounting {
* information loss in doing that.
*/
u64 cancelled_write_bytes;
};
#else /* CONFIG_TASK_IO_ACCOUNTING */
struct task_io_accounting {
};
#endif /* CONFIG_TASK_IO_ACCOUNTING */
struct proc_io_accounting {
struct task_chr_io_accounting chr;
struct task_io_accounting blk;
};

48
include/linux/task_io_accounting_ops.h
View File

@ -9,7 +9,7 @@
#ifdef CONFIG_TASK_IO_ACCOUNTING
static inline void task_io_account_read(size_t bytes)
{
current->ioac.blk.read_bytes += bytes;
current->ioac.read_bytes += bytes;
}
/*
@ -18,12 +18,12 @@ static inline void task_io_account_read(size_t bytes)
*/
static inline unsigned long task_io_get_inblock(const struct task_struct *p)
{
return p->ioac.blk.read_bytes >> 9;
return p->ioac.read_bytes >> 9;
}
static inline void task_io_account_write(size_t bytes)
{
current->ioac.blk.write_bytes += bytes;
current->ioac.write_bytes += bytes;
}
/*
@ -32,25 +32,25 @@ static inline void task_io_account_write(size_t bytes)
*/
static inline unsigned long task_io_get_oublock(const struct task_struct *p)
{
return p->ioac.blk.write_bytes >> 9;
return p->ioac.write_bytes >> 9;
}
static inline void task_io_account_cancelled_write(size_t bytes)
{
current->ioac.blk.cancelled_write_bytes += bytes;
current->ioac.cancelled_write_bytes += bytes;
}
static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
memset(ioac, 0, sizeof(*ioac));
}
static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
dst->blk.read_bytes += src->blk.read_bytes;
dst->blk.write_bytes += src->blk.write_bytes;
dst->blk.cancelled_write_bytes += src->blk.cancelled_write_bytes;
dst->read_bytes += src->read_bytes;
dst->write_bytes += src->write_bytes;
dst->cancelled_write_bytes += src->cancelled_write_bytes;
}
#else
@ -77,35 +77,35 @@ static inline void task_io_account_cancelled_write(size_t bytes)
{
}
static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
}
static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_IO_ACCOUNTING */
#ifdef CONFIG_TASK_XACCT
static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
dst->chr.rchar += src->chr.rchar;
dst->chr.wchar += src->chr.wchar;
dst->chr.syscr += src->chr.syscr;
dst->chr.syscw += src->chr.syscw;
dst->rchar += src->rchar;
dst->wchar += src->wchar;
dst->syscr += src->syscr;
dst->syscw += src->syscw;
}
#else
static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_XACCT */
static inline void task_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
task_chr_io_accounting_add(dst, src);
task_blk_io_accounting_add(dst, src);

14
kernel/tsacct.c
View File

@ -94,14 +94,14 @@ void xacct_add_tsk(struct taskstats *stats, struct task_struct *p)
stats->hiwater_vm = mm->hiwater_vm * PAGE_SIZE / KB;
mmput(mm);
}
stats->read_char = p->ioac.chr.rchar;
stats->write_char = p->ioac.chr.wchar;
stats->read_syscalls = p->ioac.chr.syscr;
stats->write_syscalls = p->ioac.chr.syscw;
stats->read_char = p->ioac.rchar;
stats->write_char = p->ioac.wchar;
stats->read_syscalls = p->ioac.syscr;
stats->write_syscalls = p->ioac.syscw;
#ifdef CONFIG_TASK_IO_ACCOUNTING
stats->read_bytes = p->ioac.blk.read_bytes;
stats->write_bytes = p->ioac.blk.write_bytes;
stats->cancelled_write_bytes = p->ioac.blk.cancelled_write_bytes;
stats->read_bytes = p->ioac.read_bytes;
stats->write_bytes = p->ioac.write_bytes;
stats->cancelled_write_bytes = p->ioac.cancelled_write_bytes;
#else
stats->read_bytes = 0;
stats->write_bytes = 0;