dt-bindings: PCI: Add support for MT2712 and MT7622
Add controller support for MT2712/MT7622 and update related properties. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Ryder Lee
Bjorn Helgaas
parent
b099631df1
commit
c2e0ba9caf
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@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
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Required properties:
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- compatible: Should contain one of the following strings:
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"mediatek,mt2701-pcie"
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"mediatek,mt2712-pcie"
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"mediatek,mt7622-pcie"
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"mediatek,mt7623-pcie"
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- device_type: Must be "pci"
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- reg: Base addresses and lengths of the PCIe controller.
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- reg: Base addresses and lengths of the PCIe subsys and root ports.
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- reg-names: Names of the above areas to use during resource lookup.
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- #address-cells: Address representation for root ports (must be 3)
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- #size-cells: Size representation for root ports (must be 2)
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- free_ck :for reference clock of PCIe subsys
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- sys_ck0 :for clock of Port0
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- sys_ck1 :for clock of Port1
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- sys_ck2 :for clock of Port2
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- clock-names:
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Mandatory entries:
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- sys_ckN :transaction layer and data link layer clock
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Required entries for MT2701/MT7623:
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- free_ck :for reference clock of PCIe subsys
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Required entries for MT2712/MT7622:
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- ahb_ckN :AHB slave interface operating clock for CSR access and RC
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initiated MMIO access
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Required entries for MT7622:
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- axi_ckN :application layer MMIO channel operating clock
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- aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
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pcie_mac_ck/pcie_pipe_ck is turned off
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- obff_ckN :OBFF functional block operating clock
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- pipe_ckN :LTSSM and PHY/MAC layer operating clock
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where N starting from 0 to one less than the number of root ports.
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- phys: List of PHY specifiers (used by generic PHY framework).
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- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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@ -33,6 +46,10 @@ Required properties for MT7623/MT2701:
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- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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number of root ports.
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Required properties for MT2712/MT7622:
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-interrupts: A list of interrupt outputs of the controller, must have one
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entry for each PCIe port
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In addition, the device tree node must have sub-nodes describing each
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PCIe port interface, having the following mandatory properties:
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@ -50,7 +67,7 @@ Required properties:
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property is sufficient.
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- num-lanes: Number of lanes to use for this port.
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Examples:
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Examples for MT7623:
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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@ -68,6 +85,7 @@ Examples:
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<0 0x1a142000 0 0x1000>, /* Port0 registers */
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<0 0x1a143000 0 0x1000>, /* Port1 registers */
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<0 0x1a144000 0 0x1000>; /* Port2 registers */
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reg-names = "subsys", "port0", "port1", "port2";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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@ -128,3 +146,139 @@ Examples:
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num-lanes = <1>;
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};
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};
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Examples for MT2712:
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pcie: pcie@11700000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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reg = <0 0x11700000 0 0x1000>,
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<0 0x112ff000 0 0x1000>;
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reg-names = "port0", "port1";
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE0>,
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<&pericfg CLK_PERI_PCIE1>;
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clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0", "pcie-phy1";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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pcie0: pcie@0,0 {
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device_type = "pci";
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1,0 {
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device_type = "pci";
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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Examples for MT7622:
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pcie: pcie@1a140000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0 0x1a140000 0 0x1000>,
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<0 0x1a143000 0 0x1000>,
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<0 0x1a145000 0 0x1000>;
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reg-names = "subsys", "port0", "port1";
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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<&pciesys CLK_PCIE_P1_MAC_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P1_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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<&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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<&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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<&pciesys CLK_PCIE_P1_OBFF_EN>,
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<&pciesys CLK_PCIE_P0_PIPE_EN>,
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<&pciesys CLK_PCIE_P1_PIPE_EN>;
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clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0", "pcie-phy1";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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pcie0: pcie@0,0 {
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device_type = "pci";
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1,0 {
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device_type = "pci";
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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