Merge branch '86xx' into for_paulus
This commit is contained in:
commit
c2944612cf
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@ -66,7 +66,7 @@
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compatible = "fsl-i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupts = <2b 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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dfsrr;
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dfsrr;
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};
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};
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@ -75,7 +75,7 @@
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compatible = "fsl-i2c";
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compatible = "fsl-i2c";
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reg = <3100 100>;
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reg = <3100 100>;
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interrupts = <2b 2>;
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interrupts = <2b 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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dfsrr;
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dfsrr;
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};
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};
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@ -85,31 +85,26 @@
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device_type = "mdio";
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device_type = "mdio";
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compatible = "gianfar";
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compatible = "gianfar";
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reg = <24520 20>;
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reg = <24520 20>;
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linux,phandle = <24520>;
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phy0: ethernet-phy@0 {
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ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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linux,phandle = <2452000>;
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interrupt-parent = <40000>;
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interrupts = <4a 1>;
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interrupts = <4a 1>;
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reg = <0>;
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reg = <0>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@1 {
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phy1: ethernet-phy@1 {
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linux,phandle = <2452001>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <40000>;
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interrupts = <4a 1>;
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interrupts = <4a 1>;
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reg = <1>;
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reg = <1>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@2 {
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phy2: ethernet-phy@2 {
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linux,phandle = <2452002>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <40000>;
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interrupts = <4a 1>;
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interrupts = <4a 1>;
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reg = <2>;
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reg = <2>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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};
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};
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ethernet-phy@3 {
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phy3: ethernet-phy@3 {
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linux,phandle = <2452003>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <40000>;
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interrupts = <4a 1>;
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interrupts = <4a 1>;
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reg = <3>;
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reg = <3>;
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device_type = "ethernet-phy";
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device_type = "ethernet-phy";
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@ -125,8 +120,8 @@
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reg = <24000 1000>;
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reg = <24000 1000>;
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mac-address = [ 00 E0 0C 00 73 00 ];
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mac-address = [ 00 E0 0C 00 73 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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phy-handle = <2452000>;
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phy-handle = <&phy0>;
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};
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};
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ethernet@25000 {
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ethernet@25000 {
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@ -138,8 +133,8 @@
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reg = <25000 1000>;
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reg = <25000 1000>;
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mac-address = [ 00 E0 0C 00 73 01 ];
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mac-address = [ 00 E0 0C 00 73 01 ];
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interrupts = <23 2 24 2 28 2>;
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interrupts = <23 2 24 2 28 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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phy-handle = <2452001>;
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phy-handle = <&phy1>;
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};
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};
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ethernet@26000 {
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ethernet@26000 {
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@ -151,8 +146,8 @@
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reg = <26000 1000>;
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reg = <26000 1000>;
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mac-address = [ 00 E0 0C 00 02 FD ];
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mac-address = [ 00 E0 0C 00 02 FD ];
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interrupts = <1F 2 20 2 21 2>;
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interrupts = <1F 2 20 2 21 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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phy-handle = <2452002>;
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phy-handle = <&phy2>;
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};
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};
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ethernet@27000 {
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ethernet@27000 {
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@ -164,8 +159,8 @@
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reg = <27000 1000>;
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reg = <27000 1000>;
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mac-address = [ 00 E0 0C 00 03 FD ];
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mac-address = [ 00 E0 0C 00 03 FD ];
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interrupts = <25 2 26 2 27 2>;
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interrupts = <25 2 26 2 27 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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phy-handle = <2452003>;
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phy-handle = <&phy3>;
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};
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};
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serial@4500 {
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serial@4500 {
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device_type = "serial";
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device_type = "serial";
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@ -173,7 +168,7 @@
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reg = <4500 100>;
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reg = <4500 100>;
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clock-frequency = <0>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupts = <2a 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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};
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};
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serial@4600 {
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serial@4600 {
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@ -182,7 +177,7 @@
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reg = <4600 100>;
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reg = <4600 100>;
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clock-frequency = <0>;
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clock-frequency = <0>;
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interrupts = <1c 2>;
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interrupts = <1c 2>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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};
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};
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pci@8000 {
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pci@8000 {
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@ -196,103 +191,102 @@
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ranges = <02000000 0 80000000 80000000 0 20000000
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <1fca055>;
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clock-frequency = <1fca055>;
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interrupt-parent = <40000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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interrupts = <18 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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interrupt-map = <
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/* IDSEL 0x11 */
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/* IDSEL 0x11 */
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8800 0 0 1 4d0 3 2
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8800 0 0 1 &i8259 3 2
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8800 0 0 2 4d0 4 2
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8800 0 0 2 &i8259 4 2
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8800 0 0 3 4d0 5 2
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8800 0 0 3 &i8259 5 2
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8800 0 0 4 4d0 6 2
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8800 0 0 4 &i8259 6 2
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/* IDSEL 0x12 */
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/* IDSEL 0x12 */
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9000 0 0 1 4d0 4 2
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9000 0 0 1 &i8259 4 2
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9000 0 0 2 4d0 5 2
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9000 0 0 2 &i8259 5 2
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9000 0 0 3 4d0 6 2
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9000 0 0 3 &i8259 6 2
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9000 0 0 4 4d0 3 2
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9000 0 0 4 &i8259 3 2
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/* IDSEL 0x13 */
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/* IDSEL 0x13 */
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9800 0 0 1 4d0 0 0
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9800 0 0 1 &i8259 0 0
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9800 0 0 2 4d0 0 0
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9800 0 0 2 &i8259 0 0
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9800 0 0 3 4d0 0 0
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9800 0 0 3 &i8259 0 0
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9800 0 0 4 4d0 0 0
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9800 0 0 4 &i8259 0 0
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/* IDSEL 0x14 */
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/* IDSEL 0x14 */
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a000 0 0 1 4d0 0 0
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a000 0 0 1 &i8259 0 0
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a000 0 0 2 4d0 0 0
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a000 0 0 2 &i8259 0 0
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a000 0 0 3 4d0 0 0
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a000 0 0 3 &i8259 0 0
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a000 0 0 4 4d0 0 0
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a000 0 0 4 &i8259 0 0
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/* IDSEL 0x15 */
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/* IDSEL 0x15 */
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a800 0 0 1 4d0 0 0
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a800 0 0 1 &i8259 0 0
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a800 0 0 2 4d0 0 0
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a800 0 0 2 &i8259 0 0
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a800 0 0 3 4d0 0 0
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a800 0 0 3 &i8259 0 0
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a800 0 0 4 4d0 0 0
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a800 0 0 4 &i8259 0 0
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/* IDSEL 0x16 */
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/* IDSEL 0x16 */
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b000 0 0 1 4d0 0 0
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b000 0 0 1 &i8259 0 0
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b000 0 0 2 4d0 0 0
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b000 0 0 2 &i8259 0 0
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b000 0 0 3 4d0 0 0
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b000 0 0 3 &i8259 0 0
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b000 0 0 4 4d0 0 0
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b000 0 0 4 &i8259 0 0
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/* IDSEL 0x17 */
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/* IDSEL 0x17 */
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b800 0 0 1 4d0 0 0
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b800 0 0 1 &i8259 0 0
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b800 0 0 2 4d0 0 0
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b800 0 0 2 &i8259 0 0
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b800 0 0 3 4d0 0 0
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b800 0 0 3 &i8259 0 0
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b800 0 0 4 4d0 0 0
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b800 0 0 4 &i8259 0 0
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/* IDSEL 0x18 */
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/* IDSEL 0x18 */
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c000 0 0 1 4d0 0 0
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c000 0 0 1 &i8259 0 0
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c000 0 0 2 4d0 0 0
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c000 0 0 2 &i8259 0 0
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c000 0 0 3 4d0 0 0
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c000 0 0 3 &i8259 0 0
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c000 0 0 4 4d0 0 0
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c000 0 0 4 &i8259 0 0
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/* IDSEL 0x19 */
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/* IDSEL 0x19 */
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c800 0 0 1 4d0 0 0
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c800 0 0 1 &i8259 0 0
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c800 0 0 2 4d0 0 0
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c800 0 0 2 &i8259 0 0
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c800 0 0 3 4d0 0 0
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c800 0 0 3 &i8259 0 0
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c800 0 0 4 4d0 0 0
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c800 0 0 4 &i8259 0 0
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/* IDSEL 0x1a */
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/* IDSEL 0x1a */
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d000 0 0 1 4d0 6 2
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d000 0 0 1 &i8259 6 2
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d000 0 0 2 4d0 3 2
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d000 0 0 2 &i8259 3 2
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d000 0 0 3 4d0 4 2
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d000 0 0 3 &i8259 4 2
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d000 0 0 4 4d0 5 2
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d000 0 0 4 &i8259 5 2
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/* IDSEL 0x1b */
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/* IDSEL 0x1b */
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d800 0 0 1 4d0 5 2
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d800 0 0 1 &i8259 5 2
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d800 0 0 2 4d0 0 0
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d800 0 0 2 &i8259 0 0
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d800 0 0 3 4d0 0 0
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d800 0 0 3 &i8259 0 0
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d800 0 0 4 4d0 0 0
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d800 0 0 4 &i8259 0 0
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/* IDSEL 0x1c */
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/* IDSEL 0x1c */
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e000 0 0 1 4d0 9 2
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e000 0 0 1 &i8259 9 2
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e000 0 0 2 4d0 a 2
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e000 0 0 2 &i8259 a 2
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e000 0 0 3 4d0 c 2
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e000 0 0 3 &i8259 c 2
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e000 0 0 4 4d0 7 2
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e000 0 0 4 &i8259 7 2
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/* IDSEL 0x1d */
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/* IDSEL 0x1d */
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e800 0 0 1 4d0 9 2
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e800 0 0 1 &i8259 9 2
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e800 0 0 2 4d0 a 2
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e800 0 0 2 &i8259 a 2
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e800 0 0 3 4d0 b 2
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e800 0 0 3 &i8259 b 2
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e800 0 0 4 4d0 0 0
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e800 0 0 4 &i8259 0 0
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/* IDSEL 0x1e */
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/* IDSEL 0x1e */
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f000 0 0 1 4d0 c 2
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f000 0 0 1 &i8259 c 2
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f000 0 0 2 4d0 0 0
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f000 0 0 2 &i8259 0 0
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||||||
f000 0 0 3 4d0 0 0
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f000 0 0 3 &i8259 0 0
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f000 0 0 4 4d0 0 0
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f000 0 0 4 &i8259 0 0
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/* IDSEL 0x1f */
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/* IDSEL 0x1f */
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f800 0 0 1 4d0 6 2
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f800 0 0 1 &i8259 6 2
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f800 0 0 2 4d0 0 0
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f800 0 0 2 &i8259 0 0
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f800 0 0 3 4d0 0 0
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f800 0 0 3 &i8259 0 0
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f800 0 0 4 4d0 0 0
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f800 0 0 4 &i8259 0 0
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||||||
>;
|
>;
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||||||
i8259@4d0 {
|
i8259: i8259@4d0 {
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||||||
linux,phandle = <4d0>;
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clock-frequency = <0>;
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clock-frequency = <0>;
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||||||
interrupt-controller;
|
interrupt-controller;
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||||||
device_type = "interrupt-controller";
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device_type = "interrupt-controller";
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|
@ -302,12 +296,11 @@
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||||||
compatible = "chrp,iic";
|
compatible = "chrp,iic";
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||||||
big-endian;
|
big-endian;
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||||||
interrupts = <49 2>;
|
interrupts = <49 2>;
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||||||
interrupt-parent = <40000>;
|
interrupt-parent = <&mpic>;
|
||||||
};
|
};
|
||||||
|
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||||||
};
|
};
|
||||||
pic@40000 {
|
mpic: pic@40000 {
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||||||
linux,phandle = <40000>;
|
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#address-cells = <0>;
|
#address-cells = <0>;
|
||||||
|
@ -316,23 +309,7 @@
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||||||
built-in;
|
built-in;
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||||||
compatible = "chrp,open-pic";
|
compatible = "chrp,open-pic";
|
||||||
device_type = "open-pic";
|
device_type = "open-pic";
|
||||||
big-endian;
|
big-endian;
|
||||||
interrupts = <
|
|
||||||
10 2 11 2 12 2 13 2
|
|
||||||
14 2 15 2 16 2 17 2
|
|
||||||
18 2 19 2 1a 2 1b 2
|
|
||||||
1c 2 1d 2 1e 2 1f 2
|
|
||||||
20 2 21 2 22 2 23 2
|
|
||||||
24 2 25 2 26 2 27 2
|
|
||||||
28 2 29 2 2a 2 2b 2
|
|
||||||
2c 2 2d 2 2e 2 2f 2
|
|
||||||
30 2 31 2 32 2 33 2
|
|
||||||
34 2 35 2 36 2 37 2
|
|
||||||
38 2 39 2 2a 2 3b 2
|
|
||||||
3c 2 3d 2 3e 2 3f 2
|
|
||||||
48 1 49 2 4a 1
|
|
||||||
>;
|
|
||||||
interrupt-parent = <40000>;
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in New Issue