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Blackfin arch: update anomaly sheets to match latest public info 

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger 2009-03-04 17:36:49 +08:00 committed by Bryan Wu
parent ff19fed4fe
commit c18e99cfba
7 changed files with 38 additions and 14 deletions
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13
arch/blackfin/mach-bf518/include/mach/anomaly.h
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@ -2,12 +2,12 @@
* File: include/asm-blackfin/mach-bf518/anomaly.h * File: include/asm-blackfin/mach-bf518/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - ???? * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
@ -19,6 +19,8 @@
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@ -53,6 +55,12 @@
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* Incorrect L1 Instruction Bank B Memory Map Location */ /* Incorrect L1 Instruction Bank B Memory Map Location */
#define ANOMALY_05000444 (1) #define ANOMALY_05000444 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (1)
/* PWM_TRIPB Signal Not Available on PG10 */
#define ANOMALY_05000453 (1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
@ -67,6 +75,7 @@
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)

3
arch/blackfin/mach-bf527/include/mach/anomaly.h
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@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf527/anomaly.h * File: include/asm-blackfin/mach-bf527/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
@ -169,6 +169,7 @@
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)

4
arch/blackfin/mach-bf533/include/mach/anomaly.h
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@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf533/anomaly.h * File: include/asm-blackfin/mach-bf533/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
@ -160,7 +160,7 @@
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) #define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) #define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) #define ANOMALY_05000306 (__SILICON_REVISION__ < 5)

4
arch/blackfin/mach-bf537/include/mach/anomaly.h
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@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf537/anomaly.h * File: include/asm-blackfin/mach-bf537/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
@ -110,7 +110,7 @@
#define ANOMALY_05000301 (1) #define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) #define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) #define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */ /* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) #define ANOMALY_05000307 (__SILICON_REVISION__ < 3)

3
arch/blackfin/mach-bf538/include/mach/anomaly.h
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@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf538/anomaly.h * File: include/asm-blackfin/mach-bf538/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
@ -120,6 +120,7 @@
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1) #define ANOMALY_05000353 (1)

21
arch/blackfin/mach-bf548/include/mach/anomaly.h
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@ -2,12 +2,12 @@
* File: include/asm-blackfin/mach-bf548/anomaly.h * File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
@ -91,8 +91,6 @@
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) #define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
@ -157,8 +155,22 @@
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */ /* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
/* OTP Write Accesses Not Supported */
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
#define ANOMALY_05000446 (1)
/* UART IrDA Receiver Fails on Extended Bit Pulses */
#define ANOMALY_05000447 (1)
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
@ -172,6 +184,7 @@
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)

4
arch/blackfin/mach-bf561/include/mach/anomaly.h
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@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf561/anomaly.h * File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/ * Bugs: Enter bugs at http://blackfin.uclinux.org/
* *
* Copyright (C) 2004-2008 Analog Devices Inc. * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later. * Licensed under the GPL-2 or later.
*/ */
@ -224,7 +224,7 @@
#define ANOMALY_05000301 (1) #define ANOMALY_05000301 (1)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (1) #define ANOMALY_05000302 (1)
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */ /* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) #define ANOMALY_05000307 (__SILICON_REVISION__ < 5)