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Merge commit 'gcl/gcl-next'

This commit is contained in:
Benjamin Herrenschmidt 2008-07-25 15:35:03 +10:00
parent fb2e405fc1 79c28acb2b
commit c174aff956
4 changed files with 95 additions and 6 deletions
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57
Documentation/powerpc/booting-without-of.txt
View File

@ -59,6 +59,7 @@ Table of Contents
p) Freescale Synchronous Serial Interface
q) USB EHCI controllers
r) MDIO on GPIOs
s) SPI busses
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@ -1883,6 +1884,62 @@ platforms are moved over to use the flattened-device-tree model.
&qe_pio_c 6>;
};
s) SPI (Serial Peripheral Interface) busses
SPI busses can be described with a node for the SPI master device
and a set of child nodes for each SPI slave on the bus. For this
discussion, it is assumed that the system's SPI controller is in
SPI master mode. This binding does not describe SPI controllers
in slave mode.
The SPI master node requires the following properties:
- #address-cells - number of cells required to define a chip select
address on the SPI bus.
- #size-cells - should be zero.
- compatible - name of SPI bus controller following generic names
recommended practice.
No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
assigning chip select numbers. Since SPI chip select configuration is
flexible and non-standardized, it is left out of this binding with the
assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.
SPI slave nodes must be children of the SPI master node and can
contain the following properties.
- reg - (required) chip select address of device.
- compatible - (required) name of SPI device following generic names
recommended practice
- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
- spi-cpol - (optional) Empty property indicating device requires
inverse clock polarity (CPOL) mode
- spi-cpha - (optional) Empty property indicating device requires
shifted clock phase (CPHA) mode
SPI example for an MPC5200 SPI bus:
spi@f00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
ethernet-switch@0 {
compatible = "micrel,ks8995m";
spi-max-frequency = <1000000>;
reg = <0>;
};
codec@1 {
compatible = "ti,tlv320aic26";
spi-max-frequency = <100000>;
reg = <1>;
};
};
VII - Marvell Discovery mv64[345]6x System Controller chips
===========================================================

2
arch/powerpc/platforms/52xx/Kconfig
View File

@ -1,7 +1,6 @@
config PPC_MPC52xx
bool "52xx-based boards"
depends on PPC_MULTIPLATFORM && PPC32
select FSL_SOC
select PPC_CLOCK
select PPC_PCI_CHOICE
@ -48,6 +47,7 @@ config PPC_MPC5200_BUGFIX
config PPC_MPC5200_GPIO
bool "MPC5200 GPIO support"
depends on PPC_MPC52xx
select GENERIC_GPIO
select HAVE_GPIO_LIB
help
Enable gpiolib support for mpc5200 based boards

2
drivers/of/of_i2c.c
View File

@ -91,8 +91,6 @@ void of_register_i2c_devices(struct i2c_adapter *adap,
}
info.irq = irq_of_parse_and_map(node, 0);
if (info.irq == NO_IRQ)
info.irq = -1;
if (of_find_i2c_driver(node, &info) < 0) {
irq_dispose_mapping(info.irq);

40
include/asm-powerpc/mpc52xx_psc.h
View File

@ -60,10 +60,12 @@
#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
/* PSC interrupt mask bits */
/* PSC interrupt status/mask bits */
#define MPC52xx_PSC_IMR_TXRDY 0x0100
#define MPC52xx_PSC_IMR_RXRDY 0x0200
#define MPC52xx_PSC_IMR_DB 0x0400
#define MPC52xx_PSC_IMR_TXEMP 0x0800
#define MPC52xx_PSC_IMR_ORERR 0x1000
#define MPC52xx_PSC_IMR_IPC 0x8000
/* PSC input port change bit */
@ -92,6 +94,34 @@
#define MPC52xx_PSC_RFNUM_MASK 0x01ff
#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
#define MPC52xx_PSC_SICR_SHDR (1 << 28)
#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
#define MPC52xx_PSC_SICR_I2S (1 << 22)
#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
#define MPC52xx_PSC_SICR_ESAI (1 << 17)
#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
#define MPC52xx_PSC_SICR_SPI (1 << 15)
#define MPC52xx_PSC_SICR_MSTR (1 << 14)
#define MPC52xx_PSC_SICR_CPOL (1 << 13)
#define MPC52xx_PSC_SICR_CPHA (1 << 12)
#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
/* Structure of the hardware registers */
struct mpc52xx_psc {
@ -132,8 +162,12 @@ struct mpc52xx_psc {
u8 reserved5[3];
u8 ctlr; /* PSC + 0x1c */
u8 reserved6[3];
u16 ccr; /* PSC + 0x20 */
u8 reserved7[14];
/* BitClkDiv field of CCR is byte swapped in
* the hardware for mpc5200/b compatibility */
u32 ccr; /* PSC + 0x20 */
u32 ac97_slots; /* PSC + 0x24 */
u32 ac97_cmd; /* PSC + 0x28 */
u32 ac97_data; /* PSC + 0x2c */
u8 ivr; /* PSC + 0x30 */
u8 reserved8[3];
u8 ip; /* PSC + 0x34 */