drm/i915: provide interface for audio driver to query cdclk
For Haswell and Broadwell, if the display power well has been disabled, the display audio controller divider values EM4 M VALUE and EM5 N VALUE will have been lost. The CDCLK frequency is required for reprogramming them to generate 24MHz HD-A link BCLK. So provide a private interface for the audio driver to query CDCLK. This is a stopgap solution until a more generic interface between audio and display drivers has been implemented. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -6053,6 +6053,27 @@ int i915_release_power_well(void)
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}
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}
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EXPORT_SYMBOL_GPL(i915_release_power_well);
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EXPORT_SYMBOL_GPL(i915_release_power_well);
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/*
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* Private interface for the audio driver to get CDCLK in kHz.
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*
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* Caller must request power well using i915_request_power_well() prior to
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* making the call.
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*/
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int i915_get_cdclk_freq(void)
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{
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struct drm_i915_private *dev_priv;
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if (!hsw_pwr)
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return -ENODEV;
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dev_priv = container_of(hsw_pwr, struct drm_i915_private,
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power_domains);
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return intel_ddi_get_cdclk_freq(dev_priv);
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}
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EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
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#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
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#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
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#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
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#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
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@ -32,5 +32,6 @@
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/* For use by hda_i915 driver */
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/* For use by hda_i915 driver */
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extern int i915_request_power_well(void);
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extern int i915_request_power_well(void);
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extern int i915_release_power_well(void);
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extern int i915_release_power_well(void);
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extern int i915_get_cdclk_freq(void);
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#endif /* _I915_POWERWELL_H_ */
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#endif /* _I915_POWERWELL_H_ */
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