MXC PWM: should active during DOZE/WAIT/DBG mode
Signed-off-by: Jason Chen <jason.chen@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: stable@kernel.org
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@ -32,6 +32,9 @@
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#define MX3_PWMSAR 0x0C /* PWM Sample Register */
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#define MX3_PWMPR 0x10 /* PWM Period Register */
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#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
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#define MX3_PWMCR_DOZEEN (1 << 24)
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#define MX3_PWMCR_WAITEN (1 << 23)
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#define MX3_PWMCR_DBGEN (1 << 22)
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#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
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#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
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#define MX3_PWMCR_EN (1 << 0)
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@ -77,7 +80,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
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writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
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writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
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cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
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cr = MX3_PWMCR_PRESCALER(prescale) |
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MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
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if (cpu_is_mx25())
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cr |= MX3_PWMCR_CLKSRC_IPG;
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