dt-bindings: serial: Add binding for uartlite

The uartlite devicetree binding was missed out.
Add the binding documentation for uartlite that is already in use.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Shubhrajyoti Datta 2018-07-21 17:19:07 +05:30 committed by Greg Kroah-Hartman
parent a3a10614ca
commit bfbf2de2c9
1 changed files with 23 additions and 0 deletions

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Xilinx Axi Uartlite controller Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Can be either of
"xlnx,xps-uartlite-1.00.a"
"xlnx,opb-uartlite-1.00.b"
- reg : Physical base address and size of the Axi Uartlite
registers map.
- interrupts : Should contain the UART controller interrupt.
Optional properties:
- port-number : Set Uart port number
- clock-names : Should be "s_axi_aclk"
- clocks : Input clock specifier. Refer to common clock bindings.
Example:
serial@800c0000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x0 0x800c0000 0x10000>;
interrupts = <0x0 0x6e 0x1>;
port-number = <0>;
};