Merge branch 'for-3.5/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2
By Stephen Warren (29) and others via Stephen Warren * 'for-3.5/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (43 commits) ARM: dt: tegra trimslice: add support for audio ARM: dt: tegra trimslice: enable SDHCI1 controller ARM: dt: tegra trimslice: add RTC I2C device ARM: dt: tegra seaboard: add i2c devices ARM: dt: tegra seaboard: configure I2C2 pinmux ARM: dt: tegra seaboard: fix I2C2 SCL rate ARM: dt: tegra: enable als and proximity sensor + pinctrl mergebase branch The pinctrl mergebase branch merge conflicts in drivers/pinctrl/core.c that were resolved. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
bf98a6eaa9
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NVIDIA Tegra20 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra20-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the tri-state, mux, pull-up/down, and pad control register sets.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an abitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, tristate, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function or tristate parameter. For this
|
||||
reason, even seemingly boolean values are actually tristates in this binding:
|
||||
unspecified, off, or on. Unspecified is represented as an absent property,
|
||||
and off/on are represented as integer values 0 and 1.
|
||||
|
||||
Required subnode-properties:
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||||
- nvidia,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- nvidia,function: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below. See the Tegra
|
||||
TRM to determine which are valid for each pin or group.
|
||||
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
|
||||
0: none, 1: down, 2: up.
|
||||
- nvidia,tristate: Integer.
|
||||
0: drive, 1: tristate.
|
||||
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
|
||||
0: no, 1: yes.
|
||||
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
|
||||
0: no, 1: yes.
|
||||
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
|
||||
most power. Controls the drive power or current. See "Low Power Mode"
|
||||
or "LPMD1" and "LPMD0" in the Tegra TRM.
|
||||
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
|
||||
Tegra TRM.
|
||||
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
|
||||
Tegra TRM.
|
||||
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVDN_SLWR" in the Tegra TRM.
|
||||
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVUP_SLWF" in the Tegra TRM.
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
|
||||
details regarding which groups support which functionality. The Linux pinctrl
|
||||
driver may also be a useful reference, since it consolidates, disambiguates,
|
||||
and corrects data from all those sources.
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||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
mux groups:
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||||
|
||||
These all support nvidia,function, nvidia,tristate, and many support
|
||||
nvidia,pull.
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||||
|
||||
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
|
||||
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
|
||||
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
|
||||
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
|
||||
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
|
||||
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
|
||||
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
|
||||
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
|
||||
uca, ucb, uda.
|
||||
|
||||
tristate groups:
|
||||
|
||||
These only support nvidia,pull.
|
||||
|
||||
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
|
||||
ld19_18, ld21_20, ld23_22.
|
||||
|
||||
drive groups:
|
||||
|
||||
With some exceptions, these support nvidia,high-speed-mode,
|
||||
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
|
||||
nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
|
||||
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
|
||||
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
|
||||
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
|
||||
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
|
||||
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
|
||||
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
|
||||
drive_uda.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra20-pinmux";
|
||||
reg = < 0x70000014 0x10 /* Tri-state registers */
|
||||
0x70000080 0x20 /* Mux registers */
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||||
0x700000a0 0x14 /* Pull-up/down registers */
|
||||
0x70000868 0xa8 >; /* Pad control registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdio4_default: sdio4_default {
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio4_default>;
|
||||
};
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||||
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NVIDIA Tegra30 pinmux controller
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||||
|
||||
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
|
||||
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
|
||||
that binding as a baseline, and only documents the differences between the
|
||||
two bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra30-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the pad control and mux registers.
|
||||
|
||||
Tegra30 adds the following optional properties for pin configuration subnodes:
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
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||||
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset. 0: no, 1: yes.
|
||||
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
|
||||
|
||||
As with Tegra20, see the Tegra TRM for complete details regarding which groups
|
||||
support which functionality.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
per-pin mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, nvidia,pull,
|
||||
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
|
||||
nvidia,io-reset.
|
||||
|
||||
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
|
||||
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
|
||||
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
|
||||
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
|
||||
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
|
||||
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
|
||||
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
|
||||
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
|
||||
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
|
||||
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
|
||||
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
|
||||
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
|
||||
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
|
||||
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
|
||||
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
|
||||
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
|
||||
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
|
||||
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
|
||||
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
|
||||
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
|
||||
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
|
||||
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
|
||||
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
|
||||
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
|
||||
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
|
||||
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
|
||||
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
|
||||
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
|
||||
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
|
||||
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
|
||||
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
|
||||
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
|
||||
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
|
||||
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
|
||||
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
|
||||
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
|
||||
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
|
||||
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
|
||||
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
|
||||
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
|
||||
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
|
||||
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
|
||||
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
|
||||
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
|
||||
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
|
||||
pwr_int_n.
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
|
||||
nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
|
||||
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
|
||||
|
||||
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
|
||||
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
|
||||
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
|
||||
uart3, uda, vi1.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra30-pinmux";
|
||||
reg = < 0x70000868 0xd0 /* Pad control registers */
|
||||
0x70003000 0x3e0 >; /* Mux registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc4_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
== Introduction ==
|
||||
|
||||
Hardware modules that control pin multiplexing or configuration parameters
|
||||
such as pull-up/down, tri-state, drive-strength etc are designated as pin
|
||||
controllers. Each pin controller must be represented as a node in device tree,
|
||||
just like any other hardware module.
|
||||
|
||||
Hardware modules whose signals are affected by pin configuration are
|
||||
designated client devices. Again, each client device must be represented as a
|
||||
node in device tree, just like any other hardware module.
|
||||
|
||||
For a client device to operate correctly, certain pin controllers must
|
||||
set up certain specific pin configurations. Some client devices need a
|
||||
single static pin configuration, e.g. set up during initialization. Others
|
||||
need to reconfigure pins at run-time, for example to tri-state pins when the
|
||||
device is inactive. Hence, each client device can define a set of named
|
||||
states. The number and names of those states is defined by the client device's
|
||||
own binding.
|
||||
|
||||
The common pinctrl bindings defined in this file provide an infrastructure
|
||||
for client device device tree nodes to map those state names to the pin
|
||||
configuration used by those states.
|
||||
|
||||
Note that pin controllers themselves may also be client devices of themselves.
|
||||
For example, a pin controller may set up its own "active" state when the
|
||||
driver loads. This would allow representing a board's static pin configuration
|
||||
in a single place, rather than splitting it across multiple client device
|
||||
nodes. The decision to do this or not somewhat rests with the author of
|
||||
individual board device tree files, and any requirements imposed by the
|
||||
bindings for the individual client devices in use by that board, i.e. whether
|
||||
they require certain specific named states for dynamic pin configuration.
|
||||
|
||||
== Pinctrl client devices ==
|
||||
|
||||
For each client device individually, every pin state is assigned an integer
|
||||
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
|
||||
property exists to define the pin configuration. Each state may also be
|
||||
assigned a name. When names are used, another property exists to map from
|
||||
those names to the integer IDs.
|
||||
|
||||
Each client device's own binding determines the set of states the must be
|
||||
defined in its device tree node, and whether to define the set of state
|
||||
IDs that must be provided, or whether to define the set of state names that
|
||||
must be provided.
|
||||
|
||||
Required properties:
|
||||
pinctrl-0: List of phandles, each pointing at a pin configuration
|
||||
node. These referenced pin configuration nodes must be child
|
||||
nodes of the pin controller that they configure. Multiple
|
||||
entries may exist in this list so that multiple pin
|
||||
controllers may be configured, or so that a state may be built
|
||||
from multiple nodes for a single pin controller, each
|
||||
contributing part of the overall configuration. See the next
|
||||
section of this document for details of the format of these
|
||||
pin configuration nodes.
|
||||
|
||||
In some cases, it may be useful to define a state, but for it
|
||||
to be empty. This may be required when a common IP block is
|
||||
used in an SoC either without a pin controller, or where the
|
||||
pin controller does not affect the HW module in question. If
|
||||
the binding for that IP block requires certain pin states to
|
||||
exist, they must still be defined, but may be left empty.
|
||||
|
||||
Optional properties:
|
||||
pinctrl-1: List of phandles, each pointing at a pin configuration
|
||||
node within a pin controller.
|
||||
...
|
||||
pinctrl-n: List of phandles, each pointing at a pin configuration
|
||||
node within a pin controller.
|
||||
pinctrl-names: The list of names to assign states. List entry 0 defines the
|
||||
name for integer state ID 0, list entry 1 for state ID 1, and
|
||||
so on.
|
||||
|
||||
For example:
|
||||
|
||||
/* For a client device requiring named states */
|
||||
device {
|
||||
pinctrl-names = "active", "idle";
|
||||
pinctrl-0 = <&state_0_node_a>;
|
||||
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
|
||||
};
|
||||
|
||||
/* For the same device if using state IDs */
|
||||
device {
|
||||
pinctrl-0 = <&state_0_node_a>;
|
||||
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
|
||||
};
|
||||
|
||||
/*
|
||||
* For an IP block whose binding supports pin configuration,
|
||||
* but in use on an SoC that doesn't have any pin control hardware
|
||||
*/
|
||||
device {
|
||||
pinctrl-names = "active", "idle";
|
||||
pinctrl-0 = <>;
|
||||
pinctrl-1 = <>;
|
||||
};
|
||||
|
||||
== Pin controller devices ==
|
||||
|
||||
Pin controller devices should contain the pin configuration nodes that client
|
||||
devices reference.
|
||||
|
||||
For example:
|
||||
|
||||
pincontroller {
|
||||
... /* Standard DT properties for the device itself elided */
|
||||
|
||||
state_0_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_b {
|
||||
...
|
||||
};
|
||||
}
|
||||
|
||||
The contents of each of those pin configuration child nodes is defined
|
||||
entirely by the binding for the individual pin controller device. There
|
||||
exists no common standard for this content.
|
||||
|
||||
The pin configuration nodes need not be direct children of the pin controller
|
||||
device; they may be grandchildren, for example. Whether this is legal, and
|
||||
whether there is any interaction between the child and intermediate parent
|
||||
nodes, is again defined entirely by the binding for the individual pin
|
||||
controller device.
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
NVIDIA Tegra 2 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra20-pinmux"
|
||||
|
||||
|
|
@ -276,3 +276,7 @@ REGULATOR
|
|||
devm_regulator_get()
|
||||
devm_regulator_put()
|
||||
devm_regulator_bulk_get()
|
||||
|
||||
PINCTRL
|
||||
devm_pinctrl_get()
|
||||
devm_pinctrl_put()
|
||||
|
|
|
|||
|
|
@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
|
|||
};
|
||||
|
||||
|
||||
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_groups);
|
||||
}
|
||||
|
||||
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
}
|
||||
|
||||
static struct pinctrl_ops foo_pctrl_ops = {
|
||||
.list_groups = foo_list_groups,
|
||||
.get_groups_count = foo_get_groups_count,
|
||||
.get_group_name = foo_get_group_name,
|
||||
.get_group_pins = foo_get_group_pins,
|
||||
};
|
||||
|
|
@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
|
|||
.pctlops = &foo_pctrl_ops,
|
||||
};
|
||||
|
||||
The pin control subsystem will call the .list_groups() function repeatedly
|
||||
beginning on 0 until it returns non-zero to determine legal selectors, then
|
||||
it will call the other functions to retrieve the name and pins of the group.
|
||||
Maintaining the data structure of the groups is up to the driver, this is
|
||||
just a simple example - in practice you may need more entries in your group
|
||||
structure, for example specific register ranges associated with each group
|
||||
and so on.
|
||||
The pin control subsystem will call the .get_groups_count() function to
|
||||
determine total number of legal selectors, then it will call the other functions
|
||||
to retrieve the name and pins of the group. Maintaining the data structure of
|
||||
the groups is up to the driver, this is just a simple example - in practice you
|
||||
may need more entries in your group structure, for example specific register
|
||||
ranges associated with each group and so on.
|
||||
|
||||
|
||||
Pin configuration
|
||||
|
|
@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
|
|||
};
|
||||
|
||||
|
||||
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_groups);
|
||||
}
|
||||
|
||||
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
}
|
||||
|
||||
static struct pinctrl_ops foo_pctrl_ops = {
|
||||
.list_groups = foo_list_groups,
|
||||
.get_groups_count = foo_get_groups_count,
|
||||
.get_group_name = foo_get_group_name,
|
||||
.get_group_pins = foo_get_group_pins,
|
||||
};
|
||||
|
|
@ -640,7 +635,7 @@ struct foo_pmx_func {
|
|||
const unsigned num_groups;
|
||||
};
|
||||
|
||||
static const char * const spi0_groups[] = { "spi0_1_grp" };
|
||||
static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
|
||||
static const char * const i2c0_groups[] = { "i2c0_grp" };
|
||||
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
|
||||
"mmc0_3_grp" };
|
||||
|
|
@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
|
|||
},
|
||||
};
|
||||
|
||||
int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
int foo_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_functions))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_functions);
|
||||
}
|
||||
|
||||
const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
|
|
@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
}
|
||||
|
||||
struct pinmux_ops foo_pmxops = {
|
||||
.list_functions = foo_list_funcs,
|
||||
.get_functions_count = foo_get_functions_count,
|
||||
.get_function_name = foo_get_fname,
|
||||
.get_function_groups = foo_get_groups,
|
||||
.enable = foo_enable,
|
||||
|
|
@ -786,7 +779,7 @@ and spi on the second function mapping:
|
|||
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
static const struct pinctrl_map __initdata mapping[] = {
|
||||
static const struct pinctrl_map mapping[] __initconst = {
|
||||
{
|
||||
.dev_name = "foo-spi.0",
|
||||
.name = PINCTRL_STATE_DEFAULT,
|
||||
|
|
@ -952,13 +945,13 @@ case), we define a mapping like this:
|
|||
The result of grabbing this mapping from the device with something like
|
||||
this (see next paragraph):
|
||||
|
||||
p = pinctrl_get(dev);
|
||||
p = devm_pinctrl_get(dev);
|
||||
s = pinctrl_lookup_state(p, "8bit");
|
||||
ret = pinctrl_select_state(p, s);
|
||||
|
||||
or more simply:
|
||||
|
||||
p = pinctrl_get_select(dev, "8bit");
|
||||
p = devm_pinctrl_get_select(dev, "8bit");
|
||||
|
||||
Will be that you activate all the three bottom records in the mapping at
|
||||
once. Since they share the same name, pin controller device, function and
|
||||
|
|
@ -992,7 +985,7 @@ foo_probe()
|
|||
/* Allocate a state holder named "foo" etc */
|
||||
struct foo_state *foo = ...;
|
||||
|
||||
foo->p = pinctrl_get(&device);
|
||||
foo->p = devm_pinctrl_get(&device);
|
||||
if (IS_ERR(foo->p)) {
|
||||
/* FIXME: clean up "foo" here */
|
||||
return PTR_ERR(foo->p);
|
||||
|
|
@ -1000,24 +993,17 @@ foo_probe()
|
|||
|
||||
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
|
||||
if (IS_ERR(foo->s)) {
|
||||
pinctrl_put(foo->p);
|
||||
/* FIXME: clean up "foo" here */
|
||||
return PTR_ERR(s);
|
||||
}
|
||||
|
||||
ret = pinctrl_select_state(foo->s);
|
||||
if (ret < 0) {
|
||||
pinctrl_put(foo->p);
|
||||
/* FIXME: clean up "foo" here */
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
foo_remove()
|
||||
{
|
||||
pinctrl_put(state->p);
|
||||
}
|
||||
|
||||
This get/lookup/select/put sequence can just as well be handled by bus drivers
|
||||
if you don't want each and every driver to handle it and you know the
|
||||
arrangement on your bus.
|
||||
|
|
@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
|
|||
kernel memory to hold the pinmux state. All mapping table parsing or similar
|
||||
slow operations take place within this API.
|
||||
|
||||
- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
|
||||
to be called automatically on the retrieved pointer when the associated
|
||||
device is removed. It is recommended to use this function over plain
|
||||
pinctrl_get().
|
||||
|
||||
- pinctrl_lookup_state() is called in process context to obtain a handle to a
|
||||
specific state for a the client device. This operation may be slow too.
|
||||
|
||||
|
|
@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
|
|||
|
||||
- pinctrl_put() frees all information associated with a pinctrl handle.
|
||||
|
||||
- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
|
||||
explicitly destroy a pinctrl object returned by devm_pinctrl_get().
|
||||
However, use of this function will be rare, due to the automatic cleanup
|
||||
that will occur even without calling it.
|
||||
|
||||
pinctrl_get() must be paired with a plain pinctrl_put().
|
||||
pinctrl_get() may not be paired with devm_pinctrl_put().
|
||||
devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
|
||||
devm_pinctrl_get() may not be paired with plain pinctrl_put().
|
||||
|
||||
Usually the pin control core handled the get/put pair and call out to the
|
||||
device drivers bookkeeping operations, like checking available functions and
|
||||
the associated pins, whereas the enable/disable pass on to the pin controller
|
||||
driver which takes care of activating and/or deactivating the mux setting by
|
||||
quickly poking some registers.
|
||||
|
||||
The pins are allocated for your device when you issue the pinctrl_get() call,
|
||||
after this you should be able to see this in the debugfs listing of all pins.
|
||||
The pins are allocated for your device when you issue the devm_pinctrl_get()
|
||||
call, after this you should be able to see this in the debugfs listing of all
|
||||
pins.
|
||||
|
||||
NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
|
||||
requested pinctrl handles, for example if the pinctrl driver has not yet
|
||||
registered. Thus make sure that the error path in your driver gracefully
|
||||
cleans up and is ready to retry the probing later in the startup process.
|
||||
|
||||
|
||||
System pin control hogging
|
||||
|
|
@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
|
|||
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
foo_switch()
|
||||
{
|
||||
struct pinctrl *p;
|
||||
struct pinctrl_state *s1, *s2;
|
||||
struct pinctrl *p;
|
||||
struct pinctrl_state *s1, *s2;
|
||||
|
||||
foo_probe()
|
||||
{
|
||||
/* Setup */
|
||||
p = pinctrl_get(&device);
|
||||
p = devm_pinctrl_get(&device);
|
||||
if (IS_ERR(p))
|
||||
...
|
||||
|
||||
|
|
@ -1111,7 +1118,10 @@ foo_switch()
|
|||
s2 = pinctrl_lookup_state(foo->p, "pos-B");
|
||||
if (IS_ERR(s2))
|
||||
...
|
||||
}
|
||||
|
||||
foo_switch()
|
||||
{
|
||||
/* Enable on position A */
|
||||
ret = pinctrl_select_state(s1);
|
||||
if (ret < 0)
|
||||
|
|
@ -1125,8 +1135,6 @@ foo_switch()
|
|||
...
|
||||
|
||||
...
|
||||
|
||||
pinctrl_put(p);
|
||||
}
|
||||
|
||||
The above has to be done from process context.
|
||||
|
|
|
|||
|
|
@ -10,6 +10,50 @@
|
|||
reg = < 0x80000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
"sdmmc1_dat0_py7",
|
||||
"sdmmc1_dat1_py6",
|
||||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
clock-frequency = < 408000000 >;
|
||||
};
|
||||
|
|
@ -40,6 +84,14 @@
|
|||
|
||||
i2c@7000c500 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* ALS and Proximity sensor */
|
||||
isl29028@44 {
|
||||
compatible = "isil,isl29028";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <88 0x04>; /*gpio PL0 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,230 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
|
||||
"spia", "spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
dtb {
|
||||
nvidia,pins = "dtb", "dtc", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "spdi", "spdo", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "dap1", "dtb", "gma", "gmb",
|
||||
"gmc", "gmd", "gme", "gpu7", "gpv",
|
||||
"i2cp", "pta", "rm", "slxa", "slxk",
|
||||
"spia", "spib";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2", "csus", "spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
||||
"dtc", "dte", "dtf", "gpu", "sdio1",
|
||||
"slxc", "slxd", "spdi", "spdo", "spig",
|
||||
"uac", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc@7000f400 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,226 @@
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"dap2", "gmb", "gmc", "gmd", "spia",
|
||||
"spib", "spic", "spid", "spie";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "pllc_out1";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu", "sdb", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
kbcb {
|
||||
nvidia,pins = "kbcb", "kbcd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc";
|
||||
nvidia,function = "owr";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdc {
|
||||
nvidia,pins = "sdc";
|
||||
nvidia,function = "twc";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spi4";
|
||||
};
|
||||
spdi {
|
||||
nvidia,pins = "spdi", "spdo";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
spif {
|
||||
nvidia,pins = "spif", "uac";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "dap1", "dap2", "dtf", "gma",
|
||||
"gmb", "gmc", "gmd", "gme", "gpu",
|
||||
"gpu7", "gpv", "i2cp", "pta", "rm",
|
||||
"sdio1", "slxk", "spdo", "uac", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
|
||||
"dtc", "dte", "slxa", "slxc", "slxd",
|
||||
"spdi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spia", "spib", "spid",
|
||||
"spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"spic", "spig", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
|
||||
"spie", "spih", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhs", "lsc0", "lspi",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_lcsn {
|
||||
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
|
||||
"lm0", "lm1", "lpp", "lpw0", "lpw1",
|
||||
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "lvp1", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,253 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "spia",
|
||||
"spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp", "lm1";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc", "owc", "spdi", "spdo",
|
||||
"uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gmd {
|
||||
nvidia,pins = "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
|
||||
"lsck", "lsda";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
|
||||
"lsdi", "lvp0";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lpp", "lsc0",
|
||||
"lspi", "lvp1", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd",
|
||||
"cdev1", "cdev2", "dap1", "dap2",
|
||||
"dap4", "dtf", "gma", "gmc", "gmd",
|
||||
"gme", "gpu", "gpu7", "i2cp", "irrx",
|
||||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxd", "slxk", "spdi", "spdo", "uac",
|
||||
"uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3", "ddc",
|
||||
"gpv", "owc", "slxc", "spib", "spid",
|
||||
"spie";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spia",
|
||||
"spig", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "spic", "uaa",
|
||||
"uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,low-power-mode = <3>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <3>;
|
||||
nvidia,slew-rate-falling = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -27,10 +274,32 @@
|
|||
micdet-delay = <100>;
|
||||
gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
|
||||
};
|
||||
|
||||
/* ALS and proximity sensor */
|
||||
isl29018@44 {
|
||||
compatible = "isil,isl29018";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = < 202 0x04 >; /* GPIO PZ2 */
|
||||
};
|
||||
|
||||
gyrometer@68 {
|
||||
compatible = "invn,mpu3050";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <204 0x04>; /* gpio PZ4 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
smart-battery@b {
|
||||
compatible = "ti,bq20z75", "smart-battery-1.1";
|
||||
reg = <0xb>;
|
||||
ti,i2c-retry-count = <2>;
|
||||
ti,poll-retry-count = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
|
|
@ -40,10 +309,17 @@
|
|||
i2c@7000d000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adt7461";
|
||||
temperature-sensor@4c {
|
||||
compatible = "nct1008";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
magnetometer@c {
|
||||
compatible = "ak8975";
|
||||
reg = <0xc>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <109 0x04>; /* gpio PN5 */
|
||||
};
|
||||
};
|
||||
|
||||
i2s@70002a00 {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,236 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc", "gmb";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gme", "pta";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc", "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
spdi {
|
||||
nvidia,pins = "spdi", "spdo";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spia {
|
||||
nvidia,pins = "spia", "spib", "spic";
|
||||
nvidia,function = "spi2";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"crtp", "dap2", "dap3", "dap4", "dta",
|
||||
"dtb", "dtc", "dtd", "dte", "gmb",
|
||||
"gme", "i2cp", "pta", "slxc", "slxd",
|
||||
"spdi", "spdo", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_atb {
|
||||
nvidia,pins = "atb", "cdev1", "dap1", "gma",
|
||||
"gmc", "gmd", "gpu", "gpu7", "gpv",
|
||||
"sdio1", "slxa", "slxk", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2", "csus", "spia", "spib",
|
||||
"spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "pmc";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
|
||||
"kbcc", "kbcd", "kbce", "kbcf", "owc",
|
||||
"spic", "spie", "spig", "spih", "uaa",
|
||||
"uab", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
|
@ -20,22 +250,30 @@
|
|||
|
||||
i2c@7000c500 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
codec: codec@1a {
|
||||
compatible = "ti,tlv320aic23";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
rtc@56 {
|
||||
compatible = "emmicro,em3027";
|
||||
reg = <0x56>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
i2s@70002800 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
i2s@70002a00 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
das@70000c00 {
|
||||
status = "disable";
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-trimslice";
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&codec>;
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
|
|
@ -58,10 +296,6 @@
|
|||
status = "disable";
|
||||
};
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
sdhci@c8000200 {
|
||||
status = "disable";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,236 @@
|
|||
reg = < 0x00000000 0x40000000 >;
|
||||
};
|
||||
|
||||
pinmux@70000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata";
|
||||
nvidia,function = "ide";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
atc {
|
||||
nvidia,pins = "atc";
|
||||
nvidia,function = "nand";
|
||||
};
|
||||
atd {
|
||||
nvidia,pins = "atd", "ate", "gmb", "spia",
|
||||
"spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp", "lm1";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap2 {
|
||||
nvidia,pins = "dap2";
|
||||
nvidia,function = "dap2";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc", "owc", "spdi", "spdo",
|
||||
"uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gmc {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
};
|
||||
gmd {
|
||||
nvidia,pins = "gmd";
|
||||
nvidia,function = "sflash";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uartb";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
|
||||
"lsdi", "lvp0";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lpp", "lpw0",
|
||||
"lpw2", "lsc0", "lsc1", "lsck", "lsda",
|
||||
"lspi", "lvp1", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdb {
|
||||
nvidia,pins = "sdb", "sdc", "sdd", "slxc";
|
||||
nvidia,function = "sdio3";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxd {
|
||||
nvidia,pins = "slxd";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
spid {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd",
|
||||
"cdev1", "cdev2", "dap1", "dap2",
|
||||
"dap4", "ddc", "dtf", "gma", "gmc",
|
||||
"gme", "gpu", "gpu7", "i2cp", "irrx",
|
||||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxc", "slxd", "slxk", "spdi", "spdo",
|
||||
"uac", "uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3", "gmd",
|
||||
"gpv", "owc", "spia", "spib", "spic",
|
||||
"spid", "spie", "spig";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
"ld5", "ld6", "ld7", "ld8", "ld9",
|
||||
"ld10", "ld11", "ld12", "ld13", "ld14",
|
||||
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
||||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
|
||||
"lvp1", "lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -26,6 +256,14 @@
|
|||
micdet-delay = <100>;
|
||||
gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
|
||||
};
|
||||
|
||||
/* ALS and proximity sensor */
|
||||
isl29018@44 {
|
||||
compatible = "isil,isl29018";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <202 0x04>; /*gpio PZ2 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@ obj-y += io.o
|
|||
obj-y += irq.o
|
||||
obj-y += clock.o
|
||||
obj-y += timer.o
|
||||
obj-y += pinmux.o
|
||||
obj-y += fuse.o
|
||||
obj-y += pmc.o
|
||||
obj-y += flowctrl.o
|
||||
|
|
@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
|
|||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
|
|
|||
|
|
@ -47,15 +47,7 @@
|
|||
#include "clock.h"
|
||||
#include "devices.h"
|
||||
|
||||
void harmony_pinmux_init(void);
|
||||
void paz00_pinmux_init(void);
|
||||
void seaboard_pinmux_init(void);
|
||||
void trimslice_pinmux_init(void);
|
||||
void ventana_pinmux_init(void);
|
||||
|
||||
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
|
||||
|
|
@ -95,33 +87,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct {
|
||||
char *machine;
|
||||
void (*init)(void);
|
||||
} pinmux_configs[] = {
|
||||
{ "compulab,trimslice", trimslice_pinmux_init },
|
||||
{ "nvidia,harmony", harmony_pinmux_init },
|
||||
{ "compal,paz00", paz00_pinmux_init },
|
||||
{ "nvidia,seaboard", seaboard_pinmux_init },
|
||||
{ "nvidia,ventana", ventana_pinmux_init },
|
||||
};
|
||||
|
||||
static void __init tegra_dt_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
tegra_clk_init_from_table(tegra_dt_clk_init_table);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
|
||||
if (of_machine_is_compatible(pinmux_configs[i].machine)) {
|
||||
pinmux_configs[i].init();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WARN(i == ARRAY_SIZE(pinmux_configs),
|
||||
"Unknown platform! Pinmuxing not initialized\n");
|
||||
|
||||
/*
|
||||
* Finished with the static registrations now; fill in the missing
|
||||
* devices
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-harmony-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,153 +16,138 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-harmony.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config harmony_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_HP_DET, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
|
||||
static struct pinctrl_map harmony_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = harmony_pinmux,
|
||||
.pg_count = ARRAY_SIZE(harmony_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = harmony_map,
|
||||
.map_count = ARRAY_SIZE(harmony_map),
|
||||
};
|
||||
|
||||
void harmony_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-paz00-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,150 +16,138 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-paz00.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config paz00_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD1_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_ULPI_RST, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_PWRN, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_RST, .enable = true },
|
||||
{ .gpio = TEGRA_WIFI_LED, .enable = true },
|
||||
static struct pinctrl_map paz00_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = paz00_pinmux,
|
||||
.pg_count = ARRAY_SIZE(paz00_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = paz00_map,
|
||||
.map_count = ARRAY_SIZE(paz00_map),
|
||||
};
|
||||
|
||||
void paz00_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,75 +15,59 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/gpio-tegra.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#include "board-pinmux.h"
|
||||
#include "devices.h"
|
||||
|
||||
struct tegra_board_pinmux_conf *confs[2];
|
||||
unsigned long tegra_pincfg_pullnone_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
static void tegra_board_pinmux_setup_gpios(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tegra_pincfg_pullnone_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(confs); i++) {
|
||||
if (!confs[i])
|
||||
continue;
|
||||
unsigned long tegra_pincfg_pullnone_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
|
||||
};
|
||||
|
||||
tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
|
||||
}
|
||||
}
|
||||
unsigned long tegra_pincfg_pullup_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
static void tegra_board_pinmux_setup_pinmux(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long tegra_pincfg_pullup_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(confs); i++) {
|
||||
if (!confs[i])
|
||||
continue;
|
||||
unsigned long tegra_pincfg_pullup_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
|
||||
};
|
||||
|
||||
tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
|
||||
unsigned long tegra_pincfg_pulldown_driven[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
if (confs[i]->drives)
|
||||
tegra_drive_pinmux_config_table(confs[i]->drives,
|
||||
confs[i]->drive_count);
|
||||
}
|
||||
}
|
||||
unsigned long tegra_pincfg_pulldown_tristate[2] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
|
||||
unsigned long event, void *vdev)
|
||||
{
|
||||
static bool had_gpio;
|
||||
static bool had_pinmux;
|
||||
unsigned long tegra_pincfg_pulldown_na[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
|
||||
};
|
||||
|
||||
struct device *dev = vdev;
|
||||
const char *devname;
|
||||
unsigned long tegra_pincfg_pullna_driven[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
|
||||
};
|
||||
|
||||
if (event != BUS_NOTIFY_BOUND_DRIVER)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
devname = dev_name(dev);
|
||||
|
||||
if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
|
||||
tegra_board_pinmux_setup_gpios();
|
||||
had_gpio = true;
|
||||
} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
|
||||
tegra_board_pinmux_setup_pinmux();
|
||||
had_pinmux = true;
|
||||
}
|
||||
|
||||
if (had_gpio && had_pinmux)
|
||||
return NOTIFY_STOP_MASK;
|
||||
else
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block nb = {
|
||||
.notifier_call = tegra_board_pinmux_bus_notify,
|
||||
unsigned long tegra_pincfg_pullna_tristate[1] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] = {
|
||||
|
|
@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
|
|||
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
|
||||
struct tegra_board_pinmux_conf *conf_b)
|
||||
{
|
||||
confs[0] = conf_a;
|
||||
confs[1] = conf_b;
|
||||
if (conf_a)
|
||||
pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
|
||||
if (conf_b)
|
||||
pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
|
||||
|
||||
bus_register_notifier(&platform_bus_type, &nb);
|
||||
|
||||
if (!of_machine_is_compatible("nvidia,tegra20"))
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -15,21 +15,37 @@
|
|||
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
|
||||
#define __MACH_TEGRA_BOARD_PINMUX_H
|
||||
|
||||
#define GPIO_DEV "tegra-gpio"
|
||||
#define PINMUX_DEV "tegra-pinmux"
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
struct tegra_pingroup_config;
|
||||
struct tegra_gpio_table;
|
||||
#include <mach/pinconf-tegra.h>
|
||||
|
||||
#define PINMUX_DEV "tegra20-pinctrl"
|
||||
|
||||
#define TEGRA_MAP_MUX(_group_, _function_) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
|
||||
|
||||
#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
|
||||
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
|
||||
|
||||
#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
|
||||
TEGRA_MAP_MUX(_group_, _function_), \
|
||||
TEGRA_MAP_CONF(_group_, _pull_, _drive_)
|
||||
|
||||
extern unsigned long tegra_pincfg_pullnone_driven[2];
|
||||
extern unsigned long tegra_pincfg_pullnone_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pullnone_na[1];
|
||||
extern unsigned long tegra_pincfg_pullup_driven[2];
|
||||
extern unsigned long tegra_pincfg_pullup_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pullup_na[1];
|
||||
extern unsigned long tegra_pincfg_pulldown_driven[2];
|
||||
extern unsigned long tegra_pincfg_pulldown_tristate[2];
|
||||
extern unsigned long tegra_pincfg_pulldown_na[1];
|
||||
extern unsigned long tegra_pincfg_pullna_driven[1];
|
||||
extern unsigned long tegra_pincfg_pullna_tristate[1];
|
||||
|
||||
struct tegra_board_pinmux_conf {
|
||||
struct tegra_pingroup_config *pgs;
|
||||
int pg_count;
|
||||
|
||||
struct tegra_drive_pingroup_config *drives;
|
||||
int drive_count;
|
||||
|
||||
struct tegra_gpio_table *gpios;
|
||||
int gpio_count;
|
||||
struct pinctrl_map *maps;
|
||||
int map_count;
|
||||
};
|
||||
|
||||
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2010,2011 NVIDIA Corporation
|
||||
* Copyright (C) 2010-2012 NVIDIA Corporation
|
||||
* Copyright (C) 2011 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
|
|
@ -14,216 +14,176 @@
|
|||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-pinmux.h"
|
||||
#include "board-seaboard.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
#define DEFAULT_DRIVE(_name) \
|
||||
{ \
|
||||
.pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
|
||||
.hsm = TEGRA_HSM_DISABLE, \
|
||||
.schmitt = TEGRA_SCHMITT_ENABLE, \
|
||||
.drive = TEGRA_DRIVE_DIV_1, \
|
||||
.pull_down = TEGRA_PULL_31, \
|
||||
.pull_up = TEGRA_PULL_31, \
|
||||
.slew_rising = TEGRA_SLEW_SLOWEST, \
|
||||
.slew_falling = TEGRA_SLEW_SLOWEST, \
|
||||
}
|
||||
|
||||
static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
|
||||
DEFAULT_DRIVE(SDIO1),
|
||||
static unsigned long seaboard_pincfg_drive_sdio1[] = {
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
|
||||
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config common_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
static struct pinctrl_map common_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
|
||||
TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
|
||||
TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
|
||||
TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config seaboard_pinmux[] = {
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
static struct pinctrl_map seaboard_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
|
||||
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
|
||||
};
|
||||
|
||||
static struct tegra_pingroup_config ventana_pinmux[] = {
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table common_gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table seaboard_gpio_table[] = {
|
||||
{ .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_POWERKEY, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_HP_DET, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true },
|
||||
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table ventana_gpio_table[] = {
|
||||
/* hp_det */
|
||||
{ .gpio = TEGRA_GPIO_PW2, .enable = true },
|
||||
/* int_mic_en */
|
||||
{ .gpio = TEGRA_GPIO_PX0, .enable = true },
|
||||
/* ext_mic_en */
|
||||
{ .gpio = TEGRA_GPIO_PX1, .enable = true },
|
||||
static struct pinctrl_map ventana_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf common_conf = {
|
||||
.pgs = common_pinmux,
|
||||
.pg_count = ARRAY_SIZE(common_pinmux),
|
||||
.gpios = common_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(common_gpio_table),
|
||||
.maps = common_map,
|
||||
.map_count = ARRAY_SIZE(common_map),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf seaboard_conf = {
|
||||
.pgs = seaboard_pinmux,
|
||||
.pg_count = ARRAY_SIZE(seaboard_pinmux),
|
||||
.drives = seaboard_drive_pinmux,
|
||||
.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
|
||||
.gpios = seaboard_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
|
||||
.maps = seaboard_map,
|
||||
.map_count = ARRAY_SIZE(seaboard_map),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf ventana_conf = {
|
||||
.pgs = ventana_pinmux,
|
||||
.pg_count = ARRAY_SIZE(ventana_pinmux),
|
||||
.gpios = ventana_gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(ventana_gpio_table),
|
||||
.maps = ventana_map,
|
||||
.map_count = ARRAY_SIZE(ventana_map),
|
||||
};
|
||||
|
||||
void seaboard_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/platform_data/tegra_usb.h>
|
||||
|
||||
#include <sound/wm8903.h>
|
||||
|
||||
|
|
@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
|
|||
|
||||
static int seaboard_ehci_init(void)
|
||||
{
|
||||
int gpio_status;
|
||||
struct tegra_ehci_platform_data *pdata;
|
||||
|
||||
gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
|
||||
if (gpio_status < 0) {
|
||||
pr_err("VBUS_USB1 request GPIO FAILED\n");
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
|
||||
if (gpio_status < 0) {
|
||||
pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
|
||||
WARN_ON(1);
|
||||
}
|
||||
gpio_set_value(TEGRA_GPIO_USB1, 1);
|
||||
pdata = tegra_ehci1_device.dev.platform_data;
|
||||
pdata->vbus_gpio = TEGRA_GPIO_USB1;
|
||||
|
||||
platform_device_register(&tegra_ehci1_device);
|
||||
platform_device_register(&tegra_ehci3_device);
|
||||
|
|
@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
|
|||
|
||||
static void __init seaboard_i2c_init(void)
|
||||
{
|
||||
gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
|
||||
gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
|
||||
|
||||
isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
|
||||
i2c_register_board_info(0, &isl29018_device, 1);
|
||||
|
||||
|
|
@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
|
|||
debug_uart_platform_data[0].irq = INT_UARTB;
|
||||
|
||||
seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
|
||||
tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
|
||||
|
||||
seaboard_common_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* arch/arm/mach-tegra/board-trimslice-pinmux.c
|
||||
*
|
||||
* Copyright (C) 2011 CompuLab, Ltd.
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -13,150 +14,139 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
|
||||
#include "gpio-names.h"
|
||||
#include "board-pinmux.h"
|
||||
#include "board-trimslice.h"
|
||||
#include "board-pinmux.h"
|
||||
|
||||
static struct tegra_pingroup_config trimslice_pinmux[] = {
|
||||
{TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
|
||||
{TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
|
||||
};
|
||||
|
||||
static struct tegra_gpio_table gpio_table[] = {
|
||||
{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
|
||||
{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
|
||||
|
||||
{ .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
|
||||
{ .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
|
||||
static struct pinctrl_map trimslice_map[] = {
|
||||
TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
|
||||
TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
|
||||
TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
|
||||
TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
|
||||
TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
|
||||
TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
|
||||
TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
|
||||
TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
|
||||
TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
|
||||
TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
|
||||
TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
|
||||
TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
|
||||
TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
|
||||
TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
|
||||
TEGRA_MAP_CONF("ck32", none, na),
|
||||
TEGRA_MAP_CONF("ddrc", none, na),
|
||||
TEGRA_MAP_CONF("pmca", none, na),
|
||||
TEGRA_MAP_CONF("pmcb", none, na),
|
||||
TEGRA_MAP_CONF("pmcc", none, na),
|
||||
TEGRA_MAP_CONF("pmcd", none, na),
|
||||
TEGRA_MAP_CONF("pmce", none, na),
|
||||
TEGRA_MAP_CONF("xm2c", none, na),
|
||||
TEGRA_MAP_CONF("xm2d", none, na),
|
||||
TEGRA_MAP_CONF("ls", up, na),
|
||||
TEGRA_MAP_CONF("lc", up, na),
|
||||
TEGRA_MAP_CONF("ld17_0", down, na),
|
||||
TEGRA_MAP_CONF("ld19_18", down, na),
|
||||
TEGRA_MAP_CONF("ld21_20", down, na),
|
||||
TEGRA_MAP_CONF("ld23_22", down, na),
|
||||
};
|
||||
|
||||
static struct tegra_board_pinmux_conf conf = {
|
||||
.pgs = trimslice_pinmux,
|
||||
.pg_count = ARRAY_SIZE(trimslice_pinmux),
|
||||
.gpios = gpio_table,
|
||||
.gpio_count = ARRAY_SIZE(gpio_table),
|
||||
.maps = trimslice_map,
|
||||
.map_count = ARRAY_SIZE(trimslice_map),
|
||||
};
|
||||
|
||||
void trimslice_pinmux_init(void)
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/tegra_usb.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
|
|||
|
||||
static void trimslice_usb_init(void)
|
||||
{
|
||||
int err;
|
||||
struct tegra_ehci_platform_data *pdata;
|
||||
|
||||
pdata = tegra_ehci1_device.dev.platform_data;
|
||||
pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
|
||||
|
||||
platform_device_register(&tegra_ehci3_device);
|
||||
|
||||
platform_device_register(&tegra_ehci2_device);
|
||||
|
||||
err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
|
||||
"usb1mode");
|
||||
if (err) {
|
||||
pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
platform_device_register(&tegra_ehci1_device);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
|
|||
};
|
||||
|
||||
struct platform_device tegra_pinmux_device = {
|
||||
.name = "tegra-pinmux",
|
||||
.name = "tegra20-pinctrl",
|
||||
.id = -1,
|
||||
.resource = pinmux_resource,
|
||||
.num_resources = ARRAY_SIZE(pinmux_resource),
|
||||
|
|
@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
|
|||
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
|
||||
.operating_mode = TEGRA_USB_OTG,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
struct tegra_ehci_platform_data tegra_ehci2_pdata = {
|
||||
.phy_config = &tegra_ehci2_ulpi_phy_config,
|
||||
.operating_mode = TEGRA_USB_HOST,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
struct tegra_ehci_platform_data tegra_ehci3_pdata = {
|
||||
.operating_mode = TEGRA_USB_HOST,
|
||||
.power_down_on_bus_suspend = 1,
|
||||
.vbus_gpio = -1,
|
||||
};
|
||||
|
||||
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
|
||||
|
|
|
|||
|
|
@ -25,13 +25,4 @@
|
|||
|
||||
#define TEGRA_NR_GPIOS INT_GPIO_NR
|
||||
|
||||
struct tegra_gpio_table {
|
||||
int gpio; /* GPIO number */
|
||||
bool enable; /* Enable for GPIO at init? */
|
||||
};
|
||||
|
||||
void tegra_gpio_config(struct tegra_gpio_table *table, int num);
|
||||
void tegra_gpio_enable(int gpio);
|
||||
void tegra_gpio_disable(int gpio);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,184 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
|
||||
#define __MACH_TEGRA_PINMUX_TEGRA20_H
|
||||
|
||||
enum tegra_pingroup {
|
||||
TEGRA_PINGROUP_ATA = 0,
|
||||
TEGRA_PINGROUP_ATB,
|
||||
TEGRA_PINGROUP_ATC,
|
||||
TEGRA_PINGROUP_ATD,
|
||||
TEGRA_PINGROUP_ATE,
|
||||
TEGRA_PINGROUP_CDEV1,
|
||||
TEGRA_PINGROUP_CDEV2,
|
||||
TEGRA_PINGROUP_CRTP,
|
||||
TEGRA_PINGROUP_CSUS,
|
||||
TEGRA_PINGROUP_DAP1,
|
||||
TEGRA_PINGROUP_DAP2,
|
||||
TEGRA_PINGROUP_DAP3,
|
||||
TEGRA_PINGROUP_DAP4,
|
||||
TEGRA_PINGROUP_DDC,
|
||||
TEGRA_PINGROUP_DTA,
|
||||
TEGRA_PINGROUP_DTB,
|
||||
TEGRA_PINGROUP_DTC,
|
||||
TEGRA_PINGROUP_DTD,
|
||||
TEGRA_PINGROUP_DTE,
|
||||
TEGRA_PINGROUP_DTF,
|
||||
TEGRA_PINGROUP_GMA,
|
||||
TEGRA_PINGROUP_GMB,
|
||||
TEGRA_PINGROUP_GMC,
|
||||
TEGRA_PINGROUP_GMD,
|
||||
TEGRA_PINGROUP_GME,
|
||||
TEGRA_PINGROUP_GPU,
|
||||
TEGRA_PINGROUP_GPU7,
|
||||
TEGRA_PINGROUP_GPV,
|
||||
TEGRA_PINGROUP_HDINT,
|
||||
TEGRA_PINGROUP_I2CP,
|
||||
TEGRA_PINGROUP_IRRX,
|
||||
TEGRA_PINGROUP_IRTX,
|
||||
TEGRA_PINGROUP_KBCA,
|
||||
TEGRA_PINGROUP_KBCB,
|
||||
TEGRA_PINGROUP_KBCC,
|
||||
TEGRA_PINGROUP_KBCD,
|
||||
TEGRA_PINGROUP_KBCE,
|
||||
TEGRA_PINGROUP_KBCF,
|
||||
TEGRA_PINGROUP_LCSN,
|
||||
TEGRA_PINGROUP_LD0,
|
||||
TEGRA_PINGROUP_LD1,
|
||||
TEGRA_PINGROUP_LD10,
|
||||
TEGRA_PINGROUP_LD11,
|
||||
TEGRA_PINGROUP_LD12,
|
||||
TEGRA_PINGROUP_LD13,
|
||||
TEGRA_PINGROUP_LD14,
|
||||
TEGRA_PINGROUP_LD15,
|
||||
TEGRA_PINGROUP_LD16,
|
||||
TEGRA_PINGROUP_LD17,
|
||||
TEGRA_PINGROUP_LD2,
|
||||
TEGRA_PINGROUP_LD3,
|
||||
TEGRA_PINGROUP_LD4,
|
||||
TEGRA_PINGROUP_LD5,
|
||||
TEGRA_PINGROUP_LD6,
|
||||
TEGRA_PINGROUP_LD7,
|
||||
TEGRA_PINGROUP_LD8,
|
||||
TEGRA_PINGROUP_LD9,
|
||||
TEGRA_PINGROUP_LDC,
|
||||
TEGRA_PINGROUP_LDI,
|
||||
TEGRA_PINGROUP_LHP0,
|
||||
TEGRA_PINGROUP_LHP1,
|
||||
TEGRA_PINGROUP_LHP2,
|
||||
TEGRA_PINGROUP_LHS,
|
||||
TEGRA_PINGROUP_LM0,
|
||||
TEGRA_PINGROUP_LM1,
|
||||
TEGRA_PINGROUP_LPP,
|
||||
TEGRA_PINGROUP_LPW0,
|
||||
TEGRA_PINGROUP_LPW1,
|
||||
TEGRA_PINGROUP_LPW2,
|
||||
TEGRA_PINGROUP_LSC0,
|
||||
TEGRA_PINGROUP_LSC1,
|
||||
TEGRA_PINGROUP_LSCK,
|
||||
TEGRA_PINGROUP_LSDA,
|
||||
TEGRA_PINGROUP_LSDI,
|
||||
TEGRA_PINGROUP_LSPI,
|
||||
TEGRA_PINGROUP_LVP0,
|
||||
TEGRA_PINGROUP_LVP1,
|
||||
TEGRA_PINGROUP_LVS,
|
||||
TEGRA_PINGROUP_OWC,
|
||||
TEGRA_PINGROUP_PMC,
|
||||
TEGRA_PINGROUP_PTA,
|
||||
TEGRA_PINGROUP_RM,
|
||||
TEGRA_PINGROUP_SDB,
|
||||
TEGRA_PINGROUP_SDC,
|
||||
TEGRA_PINGROUP_SDD,
|
||||
TEGRA_PINGROUP_SDIO1,
|
||||
TEGRA_PINGROUP_SLXA,
|
||||
TEGRA_PINGROUP_SLXC,
|
||||
TEGRA_PINGROUP_SLXD,
|
||||
TEGRA_PINGROUP_SLXK,
|
||||
TEGRA_PINGROUP_SPDI,
|
||||
TEGRA_PINGROUP_SPDO,
|
||||
TEGRA_PINGROUP_SPIA,
|
||||
TEGRA_PINGROUP_SPIB,
|
||||
TEGRA_PINGROUP_SPIC,
|
||||
TEGRA_PINGROUP_SPID,
|
||||
TEGRA_PINGROUP_SPIE,
|
||||
TEGRA_PINGROUP_SPIF,
|
||||
TEGRA_PINGROUP_SPIG,
|
||||
TEGRA_PINGROUP_SPIH,
|
||||
TEGRA_PINGROUP_UAA,
|
||||
TEGRA_PINGROUP_UAB,
|
||||
TEGRA_PINGROUP_UAC,
|
||||
TEGRA_PINGROUP_UAD,
|
||||
TEGRA_PINGROUP_UCA,
|
||||
TEGRA_PINGROUP_UCB,
|
||||
TEGRA_PINGROUP_UDA,
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
TEGRA_PINGROUP_CK32,
|
||||
TEGRA_PINGROUP_DDRC,
|
||||
TEGRA_PINGROUP_PMCA,
|
||||
TEGRA_PINGROUP_PMCB,
|
||||
TEGRA_PINGROUP_PMCC,
|
||||
TEGRA_PINGROUP_PMCD,
|
||||
TEGRA_PINGROUP_PMCE,
|
||||
TEGRA_PINGROUP_XM2C,
|
||||
TEGRA_PINGROUP_XM2D,
|
||||
TEGRA_MAX_PINGROUP,
|
||||
};
|
||||
|
||||
enum tegra_drive_pingroup {
|
||||
TEGRA_DRIVE_PINGROUP_AO1 = 0,
|
||||
TEGRA_DRIVE_PINGROUP_AO2,
|
||||
TEGRA_DRIVE_PINGROUP_AT1,
|
||||
TEGRA_DRIVE_PINGROUP_AT2,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV1,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV2,
|
||||
TEGRA_DRIVE_PINGROUP_CSUS,
|
||||
TEGRA_DRIVE_PINGROUP_DAP1,
|
||||
TEGRA_DRIVE_PINGROUP_DAP2,
|
||||
TEGRA_DRIVE_PINGROUP_DAP3,
|
||||
TEGRA_DRIVE_PINGROUP_DAP4,
|
||||
TEGRA_DRIVE_PINGROUP_DBG,
|
||||
TEGRA_DRIVE_PINGROUP_LCD1,
|
||||
TEGRA_DRIVE_PINGROUP_LCD2,
|
||||
TEGRA_DRIVE_PINGROUP_SDMMC2,
|
||||
TEGRA_DRIVE_PINGROUP_SDMMC3,
|
||||
TEGRA_DRIVE_PINGROUP_SPI,
|
||||
TEGRA_DRIVE_PINGROUP_UAA,
|
||||
TEGRA_DRIVE_PINGROUP_UAB,
|
||||
TEGRA_DRIVE_PINGROUP_UART2,
|
||||
TEGRA_DRIVE_PINGROUP_UART3,
|
||||
TEGRA_DRIVE_PINGROUP_VI1,
|
||||
TEGRA_DRIVE_PINGROUP_VI2,
|
||||
TEGRA_DRIVE_PINGROUP_XM2A,
|
||||
TEGRA_DRIVE_PINGROUP_XM2C,
|
||||
TEGRA_DRIVE_PINGROUP_XM2D,
|
||||
TEGRA_DRIVE_PINGROUP_XM2CLK,
|
||||
TEGRA_DRIVE_PINGROUP_MEMCOMP,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO1,
|
||||
TEGRA_DRIVE_PINGROUP_CRT,
|
||||
TEGRA_DRIVE_PINGROUP_DDC,
|
||||
TEGRA_DRIVE_PINGROUP_GMA,
|
||||
TEGRA_DRIVE_PINGROUP_GMB,
|
||||
TEGRA_DRIVE_PINGROUP_GMC,
|
||||
TEGRA_DRIVE_PINGROUP_GMD,
|
||||
TEGRA_DRIVE_PINGROUP_GME,
|
||||
TEGRA_DRIVE_PINGROUP_OWR,
|
||||
TEGRA_DRIVE_PINGROUP_UAD,
|
||||
TEGRA_MAX_DRIVE_PINGROUP,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (C) 2010,2011 Nvidia, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
|
||||
#define __MACH_TEGRA_PINMUX_TEGRA30_H
|
||||
|
||||
enum tegra_pingroup {
|
||||
TEGRA_PINGROUP_ULPI_DATA0 = 0,
|
||||
TEGRA_PINGROUP_ULPI_DATA1,
|
||||
TEGRA_PINGROUP_ULPI_DATA2,
|
||||
TEGRA_PINGROUP_ULPI_DATA3,
|
||||
TEGRA_PINGROUP_ULPI_DATA4,
|
||||
TEGRA_PINGROUP_ULPI_DATA5,
|
||||
TEGRA_PINGROUP_ULPI_DATA6,
|
||||
TEGRA_PINGROUP_ULPI_DATA7,
|
||||
TEGRA_PINGROUP_ULPI_CLK,
|
||||
TEGRA_PINGROUP_ULPI_DIR,
|
||||
TEGRA_PINGROUP_ULPI_NXT,
|
||||
TEGRA_PINGROUP_ULPI_STP,
|
||||
TEGRA_PINGROUP_DAP3_FS,
|
||||
TEGRA_PINGROUP_DAP3_DIN,
|
||||
TEGRA_PINGROUP_DAP3_DOUT,
|
||||
TEGRA_PINGROUP_DAP3_SCLK,
|
||||
TEGRA_PINGROUP_GPIO_PV0,
|
||||
TEGRA_PINGROUP_GPIO_PV1,
|
||||
TEGRA_PINGROUP_SDMMC1_CLK,
|
||||
TEGRA_PINGROUP_SDMMC1_CMD,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC1_DAT0,
|
||||
TEGRA_PINGROUP_GPIO_PV2,
|
||||
TEGRA_PINGROUP_GPIO_PV3,
|
||||
TEGRA_PINGROUP_CLK2_OUT,
|
||||
TEGRA_PINGROUP_CLK2_REQ,
|
||||
TEGRA_PINGROUP_LCD_PWR1,
|
||||
TEGRA_PINGROUP_LCD_PWR2,
|
||||
TEGRA_PINGROUP_LCD_SDIN,
|
||||
TEGRA_PINGROUP_LCD_SDOUT,
|
||||
TEGRA_PINGROUP_LCD_WR_N,
|
||||
TEGRA_PINGROUP_LCD_CS0_N,
|
||||
TEGRA_PINGROUP_LCD_DC0,
|
||||
TEGRA_PINGROUP_LCD_SCK,
|
||||
TEGRA_PINGROUP_LCD_PWR0,
|
||||
TEGRA_PINGROUP_LCD_PCLK,
|
||||
TEGRA_PINGROUP_LCD_DE,
|
||||
TEGRA_PINGROUP_LCD_HSYNC,
|
||||
TEGRA_PINGROUP_LCD_VSYNC,
|
||||
TEGRA_PINGROUP_LCD_D0,
|
||||
TEGRA_PINGROUP_LCD_D1,
|
||||
TEGRA_PINGROUP_LCD_D2,
|
||||
TEGRA_PINGROUP_LCD_D3,
|
||||
TEGRA_PINGROUP_LCD_D4,
|
||||
TEGRA_PINGROUP_LCD_D5,
|
||||
TEGRA_PINGROUP_LCD_D6,
|
||||
TEGRA_PINGROUP_LCD_D7,
|
||||
TEGRA_PINGROUP_LCD_D8,
|
||||
TEGRA_PINGROUP_LCD_D9,
|
||||
TEGRA_PINGROUP_LCD_D10,
|
||||
TEGRA_PINGROUP_LCD_D11,
|
||||
TEGRA_PINGROUP_LCD_D12,
|
||||
TEGRA_PINGROUP_LCD_D13,
|
||||
TEGRA_PINGROUP_LCD_D14,
|
||||
TEGRA_PINGROUP_LCD_D15,
|
||||
TEGRA_PINGROUP_LCD_D16,
|
||||
TEGRA_PINGROUP_LCD_D17,
|
||||
TEGRA_PINGROUP_LCD_D18,
|
||||
TEGRA_PINGROUP_LCD_D19,
|
||||
TEGRA_PINGROUP_LCD_D20,
|
||||
TEGRA_PINGROUP_LCD_D21,
|
||||
TEGRA_PINGROUP_LCD_D22,
|
||||
TEGRA_PINGROUP_LCD_D23,
|
||||
TEGRA_PINGROUP_LCD_CS1_N,
|
||||
TEGRA_PINGROUP_LCD_M1,
|
||||
TEGRA_PINGROUP_LCD_DC1,
|
||||
TEGRA_PINGROUP_HDMI_INT,
|
||||
TEGRA_PINGROUP_DDC_SCL,
|
||||
TEGRA_PINGROUP_DDC_SDA,
|
||||
TEGRA_PINGROUP_CRT_HSYNC,
|
||||
TEGRA_PINGROUP_CRT_VSYNC,
|
||||
TEGRA_PINGROUP_VI_D0,
|
||||
TEGRA_PINGROUP_VI_D1,
|
||||
TEGRA_PINGROUP_VI_D2,
|
||||
TEGRA_PINGROUP_VI_D3,
|
||||
TEGRA_PINGROUP_VI_D4,
|
||||
TEGRA_PINGROUP_VI_D5,
|
||||
TEGRA_PINGROUP_VI_D6,
|
||||
TEGRA_PINGROUP_VI_D7,
|
||||
TEGRA_PINGROUP_VI_D8,
|
||||
TEGRA_PINGROUP_VI_D9,
|
||||
TEGRA_PINGROUP_VI_D10,
|
||||
TEGRA_PINGROUP_VI_D11,
|
||||
TEGRA_PINGROUP_VI_PCLK,
|
||||
TEGRA_PINGROUP_VI_MCLK,
|
||||
TEGRA_PINGROUP_VI_VSYNC,
|
||||
TEGRA_PINGROUP_VI_HSYNC,
|
||||
TEGRA_PINGROUP_UART2_RXD,
|
||||
TEGRA_PINGROUP_UART2_TXD,
|
||||
TEGRA_PINGROUP_UART2_RTS_N,
|
||||
TEGRA_PINGROUP_UART2_CTS_N,
|
||||
TEGRA_PINGROUP_UART3_TXD,
|
||||
TEGRA_PINGROUP_UART3_RXD,
|
||||
TEGRA_PINGROUP_UART3_CTS_N,
|
||||
TEGRA_PINGROUP_UART3_RTS_N,
|
||||
TEGRA_PINGROUP_GPIO_PU0,
|
||||
TEGRA_PINGROUP_GPIO_PU1,
|
||||
TEGRA_PINGROUP_GPIO_PU2,
|
||||
TEGRA_PINGROUP_GPIO_PU3,
|
||||
TEGRA_PINGROUP_GPIO_PU4,
|
||||
TEGRA_PINGROUP_GPIO_PU5,
|
||||
TEGRA_PINGROUP_GPIO_PU6,
|
||||
TEGRA_PINGROUP_GEN1_I2C_SDA,
|
||||
TEGRA_PINGROUP_GEN1_I2C_SCL,
|
||||
TEGRA_PINGROUP_DAP4_FS,
|
||||
TEGRA_PINGROUP_DAP4_DIN,
|
||||
TEGRA_PINGROUP_DAP4_DOUT,
|
||||
TEGRA_PINGROUP_DAP4_SCLK,
|
||||
TEGRA_PINGROUP_CLK3_OUT,
|
||||
TEGRA_PINGROUP_CLK3_REQ,
|
||||
TEGRA_PINGROUP_GMI_WP_N,
|
||||
TEGRA_PINGROUP_GMI_IORDY,
|
||||
TEGRA_PINGROUP_GMI_WAIT,
|
||||
TEGRA_PINGROUP_GMI_ADV_N,
|
||||
TEGRA_PINGROUP_GMI_CLK,
|
||||
TEGRA_PINGROUP_GMI_CS0_N,
|
||||
TEGRA_PINGROUP_GMI_CS1_N,
|
||||
TEGRA_PINGROUP_GMI_CS2_N,
|
||||
TEGRA_PINGROUP_GMI_CS3_N,
|
||||
TEGRA_PINGROUP_GMI_CS4_N,
|
||||
TEGRA_PINGROUP_GMI_CS6_N,
|
||||
TEGRA_PINGROUP_GMI_CS7_N,
|
||||
TEGRA_PINGROUP_GMI_AD0,
|
||||
TEGRA_PINGROUP_GMI_AD1,
|
||||
TEGRA_PINGROUP_GMI_AD2,
|
||||
TEGRA_PINGROUP_GMI_AD3,
|
||||
TEGRA_PINGROUP_GMI_AD4,
|
||||
TEGRA_PINGROUP_GMI_AD5,
|
||||
TEGRA_PINGROUP_GMI_AD6,
|
||||
TEGRA_PINGROUP_GMI_AD7,
|
||||
TEGRA_PINGROUP_GMI_AD8,
|
||||
TEGRA_PINGROUP_GMI_AD9,
|
||||
TEGRA_PINGROUP_GMI_AD10,
|
||||
TEGRA_PINGROUP_GMI_AD11,
|
||||
TEGRA_PINGROUP_GMI_AD12,
|
||||
TEGRA_PINGROUP_GMI_AD13,
|
||||
TEGRA_PINGROUP_GMI_AD14,
|
||||
TEGRA_PINGROUP_GMI_AD15,
|
||||
TEGRA_PINGROUP_GMI_A16,
|
||||
TEGRA_PINGROUP_GMI_A17,
|
||||
TEGRA_PINGROUP_GMI_A18,
|
||||
TEGRA_PINGROUP_GMI_A19,
|
||||
TEGRA_PINGROUP_GMI_WR_N,
|
||||
TEGRA_PINGROUP_GMI_OE_N,
|
||||
TEGRA_PINGROUP_GMI_DQS,
|
||||
TEGRA_PINGROUP_GMI_RST_N,
|
||||
TEGRA_PINGROUP_GEN2_I2C_SCL,
|
||||
TEGRA_PINGROUP_GEN2_I2C_SDA,
|
||||
TEGRA_PINGROUP_SDMMC4_CLK,
|
||||
TEGRA_PINGROUP_SDMMC4_CMD,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT0,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT4,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT5,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT6,
|
||||
TEGRA_PINGROUP_SDMMC4_DAT7,
|
||||
TEGRA_PINGROUP_SDMMC4_RST_N,
|
||||
TEGRA_PINGROUP_CAM_MCLK,
|
||||
TEGRA_PINGROUP_GPIO_PCC1,
|
||||
TEGRA_PINGROUP_GPIO_PBB0,
|
||||
TEGRA_PINGROUP_CAM_I2C_SCL,
|
||||
TEGRA_PINGROUP_CAM_I2C_SDA,
|
||||
TEGRA_PINGROUP_GPIO_PBB3,
|
||||
TEGRA_PINGROUP_GPIO_PBB4,
|
||||
TEGRA_PINGROUP_GPIO_PBB5,
|
||||
TEGRA_PINGROUP_GPIO_PBB6,
|
||||
TEGRA_PINGROUP_GPIO_PBB7,
|
||||
TEGRA_PINGROUP_GPIO_PCC2,
|
||||
TEGRA_PINGROUP_JTAG_RTCK,
|
||||
TEGRA_PINGROUP_PWR_I2C_SCL,
|
||||
TEGRA_PINGROUP_PWR_I2C_SDA,
|
||||
TEGRA_PINGROUP_KB_ROW0,
|
||||
TEGRA_PINGROUP_KB_ROW1,
|
||||
TEGRA_PINGROUP_KB_ROW2,
|
||||
TEGRA_PINGROUP_KB_ROW3,
|
||||
TEGRA_PINGROUP_KB_ROW4,
|
||||
TEGRA_PINGROUP_KB_ROW5,
|
||||
TEGRA_PINGROUP_KB_ROW6,
|
||||
TEGRA_PINGROUP_KB_ROW7,
|
||||
TEGRA_PINGROUP_KB_ROW8,
|
||||
TEGRA_PINGROUP_KB_ROW9,
|
||||
TEGRA_PINGROUP_KB_ROW10,
|
||||
TEGRA_PINGROUP_KB_ROW11,
|
||||
TEGRA_PINGROUP_KB_ROW12,
|
||||
TEGRA_PINGROUP_KB_ROW13,
|
||||
TEGRA_PINGROUP_KB_ROW14,
|
||||
TEGRA_PINGROUP_KB_ROW15,
|
||||
TEGRA_PINGROUP_KB_COL0,
|
||||
TEGRA_PINGROUP_KB_COL1,
|
||||
TEGRA_PINGROUP_KB_COL2,
|
||||
TEGRA_PINGROUP_KB_COL3,
|
||||
TEGRA_PINGROUP_KB_COL4,
|
||||
TEGRA_PINGROUP_KB_COL5,
|
||||
TEGRA_PINGROUP_KB_COL6,
|
||||
TEGRA_PINGROUP_KB_COL7,
|
||||
TEGRA_PINGROUP_CLK_32K_OUT,
|
||||
TEGRA_PINGROUP_SYS_CLK_REQ,
|
||||
TEGRA_PINGROUP_CORE_PWR_REQ,
|
||||
TEGRA_PINGROUP_CPU_PWR_REQ,
|
||||
TEGRA_PINGROUP_PWR_INT_N,
|
||||
TEGRA_PINGROUP_CLK_32K_IN,
|
||||
TEGRA_PINGROUP_OWR,
|
||||
TEGRA_PINGROUP_DAP1_FS,
|
||||
TEGRA_PINGROUP_DAP1_DIN,
|
||||
TEGRA_PINGROUP_DAP1_DOUT,
|
||||
TEGRA_PINGROUP_DAP1_SCLK,
|
||||
TEGRA_PINGROUP_CLK1_REQ,
|
||||
TEGRA_PINGROUP_CLK1_OUT,
|
||||
TEGRA_PINGROUP_SPDIF_IN,
|
||||
TEGRA_PINGROUP_SPDIF_OUT,
|
||||
TEGRA_PINGROUP_DAP2_FS,
|
||||
TEGRA_PINGROUP_DAP2_DIN,
|
||||
TEGRA_PINGROUP_DAP2_DOUT,
|
||||
TEGRA_PINGROUP_DAP2_SCLK,
|
||||
TEGRA_PINGROUP_SPI2_MOSI,
|
||||
TEGRA_PINGROUP_SPI2_MISO,
|
||||
TEGRA_PINGROUP_SPI2_CS0_N,
|
||||
TEGRA_PINGROUP_SPI2_SCK,
|
||||
TEGRA_PINGROUP_SPI1_MOSI,
|
||||
TEGRA_PINGROUP_SPI1_SCK,
|
||||
TEGRA_PINGROUP_SPI1_CS0_N,
|
||||
TEGRA_PINGROUP_SPI1_MISO,
|
||||
TEGRA_PINGROUP_SPI2_CS1_N,
|
||||
TEGRA_PINGROUP_SPI2_CS2_N,
|
||||
TEGRA_PINGROUP_SDMMC3_CLK,
|
||||
TEGRA_PINGROUP_SDMMC3_CMD,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT0,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT1,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT2,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT3,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT4,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT5,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT6,
|
||||
TEGRA_PINGROUP_SDMMC3_DAT7,
|
||||
TEGRA_PINGROUP_PEX_L0_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L0_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
|
||||
TEGRA_PINGROUP_PEX_WAKE_N,
|
||||
TEGRA_PINGROUP_PEX_L1_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L1_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
|
||||
TEGRA_PINGROUP_PEX_L2_PRSNT_N,
|
||||
TEGRA_PINGROUP_PEX_L2_RST_N,
|
||||
TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
|
||||
TEGRA_PINGROUP_HDMI_CEC,
|
||||
TEGRA_MAX_PINGROUP,
|
||||
};
|
||||
|
||||
enum tegra_drive_pingroup {
|
||||
TEGRA_DRIVE_PINGROUP_AO1 = 0,
|
||||
TEGRA_DRIVE_PINGROUP_AO2,
|
||||
TEGRA_DRIVE_PINGROUP_AT1,
|
||||
TEGRA_DRIVE_PINGROUP_AT2,
|
||||
TEGRA_DRIVE_PINGROUP_AT3,
|
||||
TEGRA_DRIVE_PINGROUP_AT4,
|
||||
TEGRA_DRIVE_PINGROUP_AT5,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV1,
|
||||
TEGRA_DRIVE_PINGROUP_CDEV2,
|
||||
TEGRA_DRIVE_PINGROUP_CSUS,
|
||||
TEGRA_DRIVE_PINGROUP_DAP1,
|
||||
TEGRA_DRIVE_PINGROUP_DAP2,
|
||||
TEGRA_DRIVE_PINGROUP_DAP3,
|
||||
TEGRA_DRIVE_PINGROUP_DAP4,
|
||||
TEGRA_DRIVE_PINGROUP_DBG,
|
||||
TEGRA_DRIVE_PINGROUP_LCD1,
|
||||
TEGRA_DRIVE_PINGROUP_LCD2,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO2,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO3,
|
||||
TEGRA_DRIVE_PINGROUP_SPI,
|
||||
TEGRA_DRIVE_PINGROUP_UAA,
|
||||
TEGRA_DRIVE_PINGROUP_UAB,
|
||||
TEGRA_DRIVE_PINGROUP_UART2,
|
||||
TEGRA_DRIVE_PINGROUP_UART3,
|
||||
TEGRA_DRIVE_PINGROUP_VI1,
|
||||
TEGRA_DRIVE_PINGROUP_SDIO1,
|
||||
TEGRA_DRIVE_PINGROUP_CRT,
|
||||
TEGRA_DRIVE_PINGROUP_DDC,
|
||||
TEGRA_DRIVE_PINGROUP_GMA,
|
||||
TEGRA_DRIVE_PINGROUP_GMB,
|
||||
TEGRA_DRIVE_PINGROUP_GMC,
|
||||
TEGRA_DRIVE_PINGROUP_GMD,
|
||||
TEGRA_DRIVE_PINGROUP_GME,
|
||||
TEGRA_DRIVE_PINGROUP_GMF,
|
||||
TEGRA_DRIVE_PINGROUP_GMG,
|
||||
TEGRA_DRIVE_PINGROUP_GMH,
|
||||
TEGRA_DRIVE_PINGROUP_OWR,
|
||||
TEGRA_DRIVE_PINGROUP_UAD,
|
||||
TEGRA_DRIVE_PINGROUP_GPV,
|
||||
TEGRA_DRIVE_PINGROUP_DEV3,
|
||||
TEGRA_DRIVE_PINGROUP_CEC,
|
||||
TEGRA_MAX_DRIVE_PINGROUP,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,302 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/include/mach/pinmux.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
* Copyright (C) 2010,2011 Nvidia, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_PINMUX_H
|
||||
#define __MACH_TEGRA_PINMUX_H
|
||||
|
||||
enum tegra_mux_func {
|
||||
TEGRA_MUX_RSVD = 0x8000,
|
||||
TEGRA_MUX_RSVD1 = 0x8000,
|
||||
TEGRA_MUX_RSVD2 = 0x8001,
|
||||
TEGRA_MUX_RSVD3 = 0x8002,
|
||||
TEGRA_MUX_RSVD4 = 0x8003,
|
||||
TEGRA_MUX_INVALID = 0x4000,
|
||||
TEGRA_MUX_NONE = -1,
|
||||
TEGRA_MUX_AHB_CLK,
|
||||
TEGRA_MUX_APB_CLK,
|
||||
TEGRA_MUX_AUDIO_SYNC,
|
||||
TEGRA_MUX_CRT,
|
||||
TEGRA_MUX_DAP1,
|
||||
TEGRA_MUX_DAP2,
|
||||
TEGRA_MUX_DAP3,
|
||||
TEGRA_MUX_DAP4,
|
||||
TEGRA_MUX_DAP5,
|
||||
TEGRA_MUX_DISPLAYA,
|
||||
TEGRA_MUX_DISPLAYB,
|
||||
TEGRA_MUX_EMC_TEST0_DLL,
|
||||
TEGRA_MUX_EMC_TEST1_DLL,
|
||||
TEGRA_MUX_GMI,
|
||||
TEGRA_MUX_GMI_INT,
|
||||
TEGRA_MUX_HDMI,
|
||||
TEGRA_MUX_I2C,
|
||||
TEGRA_MUX_I2C2,
|
||||
TEGRA_MUX_I2C3,
|
||||
TEGRA_MUX_IDE,
|
||||
TEGRA_MUX_IRDA,
|
||||
TEGRA_MUX_KBC,
|
||||
TEGRA_MUX_MIO,
|
||||
TEGRA_MUX_MIPI_HS,
|
||||
TEGRA_MUX_NAND,
|
||||
TEGRA_MUX_OSC,
|
||||
TEGRA_MUX_OWR,
|
||||
TEGRA_MUX_PCIE,
|
||||
TEGRA_MUX_PLLA_OUT,
|
||||
TEGRA_MUX_PLLC_OUT1,
|
||||
TEGRA_MUX_PLLM_OUT1,
|
||||
TEGRA_MUX_PLLP_OUT2,
|
||||
TEGRA_MUX_PLLP_OUT3,
|
||||
TEGRA_MUX_PLLP_OUT4,
|
||||
TEGRA_MUX_PWM,
|
||||
TEGRA_MUX_PWR_INTR,
|
||||
TEGRA_MUX_PWR_ON,
|
||||
TEGRA_MUX_RTCK,
|
||||
TEGRA_MUX_SDIO1,
|
||||
TEGRA_MUX_SDIO2,
|
||||
TEGRA_MUX_SDIO3,
|
||||
TEGRA_MUX_SDIO4,
|
||||
TEGRA_MUX_SFLASH,
|
||||
TEGRA_MUX_SPDIF,
|
||||
TEGRA_MUX_SPI1,
|
||||
TEGRA_MUX_SPI2,
|
||||
TEGRA_MUX_SPI2_ALT,
|
||||
TEGRA_MUX_SPI3,
|
||||
TEGRA_MUX_SPI4,
|
||||
TEGRA_MUX_TRACE,
|
||||
TEGRA_MUX_TWC,
|
||||
TEGRA_MUX_UARTA,
|
||||
TEGRA_MUX_UARTB,
|
||||
TEGRA_MUX_UARTC,
|
||||
TEGRA_MUX_UARTD,
|
||||
TEGRA_MUX_UARTE,
|
||||
TEGRA_MUX_ULPI,
|
||||
TEGRA_MUX_VI,
|
||||
TEGRA_MUX_VI_SENSOR_CLK,
|
||||
TEGRA_MUX_XIO,
|
||||
TEGRA_MUX_BLINK,
|
||||
TEGRA_MUX_CEC,
|
||||
TEGRA_MUX_CLK12,
|
||||
TEGRA_MUX_DAP,
|
||||
TEGRA_MUX_DAPSDMMC2,
|
||||
TEGRA_MUX_DDR,
|
||||
TEGRA_MUX_DEV3,
|
||||
TEGRA_MUX_DTV,
|
||||
TEGRA_MUX_VI_ALT1,
|
||||
TEGRA_MUX_VI_ALT2,
|
||||
TEGRA_MUX_VI_ALT3,
|
||||
TEGRA_MUX_EMC_DLL,
|
||||
TEGRA_MUX_EXTPERIPH1,
|
||||
TEGRA_MUX_EXTPERIPH2,
|
||||
TEGRA_MUX_EXTPERIPH3,
|
||||
TEGRA_MUX_GMI_ALT,
|
||||
TEGRA_MUX_HDA,
|
||||
TEGRA_MUX_HSI,
|
||||
TEGRA_MUX_I2C4,
|
||||
TEGRA_MUX_I2C5,
|
||||
TEGRA_MUX_I2CPWR,
|
||||
TEGRA_MUX_I2S0,
|
||||
TEGRA_MUX_I2S1,
|
||||
TEGRA_MUX_I2S2,
|
||||
TEGRA_MUX_I2S3,
|
||||
TEGRA_MUX_I2S4,
|
||||
TEGRA_MUX_NAND_ALT,
|
||||
TEGRA_MUX_POPSDIO4,
|
||||
TEGRA_MUX_POPSDMMC4,
|
||||
TEGRA_MUX_PWM0,
|
||||
TEGRA_MUX_PWM1,
|
||||
TEGRA_MUX_PWM2,
|
||||
TEGRA_MUX_PWM3,
|
||||
TEGRA_MUX_SATA,
|
||||
TEGRA_MUX_SPI5,
|
||||
TEGRA_MUX_SPI6,
|
||||
TEGRA_MUX_SYSCLK,
|
||||
TEGRA_MUX_VGP1,
|
||||
TEGRA_MUX_VGP2,
|
||||
TEGRA_MUX_VGP3,
|
||||
TEGRA_MUX_VGP4,
|
||||
TEGRA_MUX_VGP5,
|
||||
TEGRA_MUX_VGP6,
|
||||
TEGRA_MUX_SAFE,
|
||||
TEGRA_MAX_MUX,
|
||||
};
|
||||
|
||||
enum tegra_pullupdown {
|
||||
TEGRA_PUPD_NORMAL = 0,
|
||||
TEGRA_PUPD_PULL_DOWN,
|
||||
TEGRA_PUPD_PULL_UP,
|
||||
};
|
||||
|
||||
enum tegra_tristate {
|
||||
TEGRA_TRI_NORMAL = 0,
|
||||
TEGRA_TRI_TRISTATE = 1,
|
||||
};
|
||||
|
||||
enum tegra_pin_io {
|
||||
TEGRA_PIN_OUTPUT = 0,
|
||||
TEGRA_PIN_INPUT = 1,
|
||||
};
|
||||
|
||||
enum tegra_vddio {
|
||||
TEGRA_VDDIO_BB = 0,
|
||||
TEGRA_VDDIO_LCD,
|
||||
TEGRA_VDDIO_VI,
|
||||
TEGRA_VDDIO_UART,
|
||||
TEGRA_VDDIO_DDR,
|
||||
TEGRA_VDDIO_NAND,
|
||||
TEGRA_VDDIO_SYS,
|
||||
TEGRA_VDDIO_AUDIO,
|
||||
TEGRA_VDDIO_SD,
|
||||
TEGRA_VDDIO_CAM,
|
||||
TEGRA_VDDIO_GMI,
|
||||
TEGRA_VDDIO_PEXCTL,
|
||||
TEGRA_VDDIO_SDMMC1,
|
||||
TEGRA_VDDIO_SDMMC3,
|
||||
TEGRA_VDDIO_SDMMC4,
|
||||
};
|
||||
|
||||
struct tegra_pingroup_config {
|
||||
int pingroup;
|
||||
enum tegra_mux_func func;
|
||||
enum tegra_pullupdown pupd;
|
||||
enum tegra_tristate tristate;
|
||||
};
|
||||
|
||||
enum tegra_slew {
|
||||
TEGRA_SLEW_FASTEST = 0,
|
||||
TEGRA_SLEW_FAST,
|
||||
TEGRA_SLEW_SLOW,
|
||||
TEGRA_SLEW_SLOWEST,
|
||||
TEGRA_MAX_SLEW,
|
||||
};
|
||||
|
||||
enum tegra_pull_strength {
|
||||
TEGRA_PULL_0 = 0,
|
||||
TEGRA_PULL_1,
|
||||
TEGRA_PULL_2,
|
||||
TEGRA_PULL_3,
|
||||
TEGRA_PULL_4,
|
||||
TEGRA_PULL_5,
|
||||
TEGRA_PULL_6,
|
||||
TEGRA_PULL_7,
|
||||
TEGRA_PULL_8,
|
||||
TEGRA_PULL_9,
|
||||
TEGRA_PULL_10,
|
||||
TEGRA_PULL_11,
|
||||
TEGRA_PULL_12,
|
||||
TEGRA_PULL_13,
|
||||
TEGRA_PULL_14,
|
||||
TEGRA_PULL_15,
|
||||
TEGRA_PULL_16,
|
||||
TEGRA_PULL_17,
|
||||
TEGRA_PULL_18,
|
||||
TEGRA_PULL_19,
|
||||
TEGRA_PULL_20,
|
||||
TEGRA_PULL_21,
|
||||
TEGRA_PULL_22,
|
||||
TEGRA_PULL_23,
|
||||
TEGRA_PULL_24,
|
||||
TEGRA_PULL_25,
|
||||
TEGRA_PULL_26,
|
||||
TEGRA_PULL_27,
|
||||
TEGRA_PULL_28,
|
||||
TEGRA_PULL_29,
|
||||
TEGRA_PULL_30,
|
||||
TEGRA_PULL_31,
|
||||
TEGRA_MAX_PULL,
|
||||
};
|
||||
|
||||
enum tegra_drive {
|
||||
TEGRA_DRIVE_DIV_8 = 0,
|
||||
TEGRA_DRIVE_DIV_4,
|
||||
TEGRA_DRIVE_DIV_2,
|
||||
TEGRA_DRIVE_DIV_1,
|
||||
TEGRA_MAX_DRIVE,
|
||||
};
|
||||
|
||||
enum tegra_hsm {
|
||||
TEGRA_HSM_DISABLE = 0,
|
||||
TEGRA_HSM_ENABLE,
|
||||
};
|
||||
|
||||
enum tegra_schmitt {
|
||||
TEGRA_SCHMITT_DISABLE = 0,
|
||||
TEGRA_SCHMITT_ENABLE,
|
||||
};
|
||||
|
||||
struct tegra_drive_pingroup_config {
|
||||
int pingroup;
|
||||
enum tegra_hsm hsm;
|
||||
enum tegra_schmitt schmitt;
|
||||
enum tegra_drive drive;
|
||||
enum tegra_pull_strength pull_down;
|
||||
enum tegra_pull_strength pull_up;
|
||||
enum tegra_slew slew_rising;
|
||||
enum tegra_slew slew_falling;
|
||||
};
|
||||
|
||||
struct tegra_drive_pingroup_desc {
|
||||
const char *name;
|
||||
s16 reg_bank;
|
||||
s16 reg;
|
||||
};
|
||||
|
||||
struct tegra_pingroup_desc {
|
||||
const char *name;
|
||||
int funcs[4];
|
||||
int func_safe;
|
||||
int vddio;
|
||||
enum tegra_pin_io io_default;
|
||||
s16 tri_bank; /* Register bank the tri_reg exists within */
|
||||
s16 mux_bank; /* Register bank the mux_reg exists within */
|
||||
s16 pupd_bank; /* Register bank the pupd_reg exists within */
|
||||
s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
|
||||
s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
|
||||
s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
|
||||
s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
|
||||
s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
|
||||
s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
|
||||
s8 lock_bit; /* offset of the LOCK bit into mux register bit */
|
||||
s8 od_bit; /* offset of the OD bit into mux register bit */
|
||||
s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
|
||||
};
|
||||
|
||||
typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max);
|
||||
|
||||
void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
|
||||
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
|
||||
|
||||
void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
|
||||
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
|
||||
|
||||
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
|
||||
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
|
||||
|
||||
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
|
||||
void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len);
|
||||
void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_tristate tristate);
|
||||
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_pullupdown pupd);
|
||||
#endif
|
||||
|
|
@ -1,244 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
|
||||
*
|
||||
* Common pinmux configurations for Tegra20 SoCs
|
||||
*
|
||||
* Copyright (C) 2010 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra20.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
#define TRISTATE_REG_A 0x14
|
||||
#define PIN_MUX_CTL_REG_A 0x80
|
||||
#define PULLUPDOWN_REG_A 0xa0
|
||||
#define PINGROUP_REG_A 0x868
|
||||
|
||||
#define DRIVE_PINGROUP(pg_name, r) \
|
||||
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.reg_bank = 3, \
|
||||
.reg = ((r) - PINGROUP_REG_A) \
|
||||
}
|
||||
|
||||
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
|
||||
DRIVE_PINGROUP(AO1, 0x868),
|
||||
DRIVE_PINGROUP(AO2, 0x86c),
|
||||
DRIVE_PINGROUP(AT1, 0x870),
|
||||
DRIVE_PINGROUP(AT2, 0x874),
|
||||
DRIVE_PINGROUP(CDEV1, 0x878),
|
||||
DRIVE_PINGROUP(CDEV2, 0x87c),
|
||||
DRIVE_PINGROUP(CSUS, 0x880),
|
||||
DRIVE_PINGROUP(DAP1, 0x884),
|
||||
DRIVE_PINGROUP(DAP2, 0x888),
|
||||
DRIVE_PINGROUP(DAP3, 0x88c),
|
||||
DRIVE_PINGROUP(DAP4, 0x890),
|
||||
DRIVE_PINGROUP(DBG, 0x894),
|
||||
DRIVE_PINGROUP(LCD1, 0x898),
|
||||
DRIVE_PINGROUP(LCD2, 0x89c),
|
||||
DRIVE_PINGROUP(SDMMC2, 0x8a0),
|
||||
DRIVE_PINGROUP(SDMMC3, 0x8a4),
|
||||
DRIVE_PINGROUP(SPI, 0x8a8),
|
||||
DRIVE_PINGROUP(UAA, 0x8ac),
|
||||
DRIVE_PINGROUP(UAB, 0x8b0),
|
||||
DRIVE_PINGROUP(UART2, 0x8b4),
|
||||
DRIVE_PINGROUP(UART3, 0x8b8),
|
||||
DRIVE_PINGROUP(VI1, 0x8bc),
|
||||
DRIVE_PINGROUP(VI2, 0x8c0),
|
||||
DRIVE_PINGROUP(XM2A, 0x8c4),
|
||||
DRIVE_PINGROUP(XM2C, 0x8c8),
|
||||
DRIVE_PINGROUP(XM2D, 0x8cc),
|
||||
DRIVE_PINGROUP(XM2CLK, 0x8d0),
|
||||
DRIVE_PINGROUP(MEMCOMP, 0x8d4),
|
||||
DRIVE_PINGROUP(SDIO1, 0x8e0),
|
||||
DRIVE_PINGROUP(CRT, 0x8ec),
|
||||
DRIVE_PINGROUP(DDC, 0x8f0),
|
||||
DRIVE_PINGROUP(GMA, 0x8f4),
|
||||
DRIVE_PINGROUP(GMB, 0x8f8),
|
||||
DRIVE_PINGROUP(GMC, 0x8fc),
|
||||
DRIVE_PINGROUP(GMD, 0x900),
|
||||
DRIVE_PINGROUP(GME, 0x904),
|
||||
DRIVE_PINGROUP(OWR, 0x908),
|
||||
DRIVE_PINGROUP(UAD, 0x90c),
|
||||
};
|
||||
|
||||
#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
|
||||
tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
|
||||
[TEGRA_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.vddio = TEGRA_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## f_safe, \
|
||||
.tri_bank = 0, \
|
||||
.tri_reg = ((tri_r) - TRISTATE_REG_A), \
|
||||
.tri_bit = tri_b, \
|
||||
.mux_bank = 1, \
|
||||
.mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
|
||||
.mux_bit = mux_b, \
|
||||
.pupd_bank = 2, \
|
||||
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
|
||||
.pupd_bit = pupd_b, \
|
||||
.lock_bit = -1, \
|
||||
.od_bit = -1, \
|
||||
.ioreset_bit = -1, \
|
||||
.io_default = -1, \
|
||||
}
|
||||
|
||||
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
|
||||
PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
|
||||
PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
|
||||
PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
|
||||
PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
|
||||
PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
|
||||
PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
|
||||
PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
|
||||
PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
|
||||
PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
|
||||
PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
|
||||
PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
|
||||
PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
|
||||
PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
|
||||
PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
|
||||
PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
|
||||
PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
|
||||
PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
|
||||
PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
|
||||
PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
|
||||
PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
|
||||
PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
|
||||
PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
|
||||
PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
|
||||
PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
|
||||
PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
|
||||
PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
|
||||
PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
|
||||
PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
|
||||
PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
|
||||
PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
|
||||
PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
|
||||
PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
|
||||
PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
|
||||
PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
|
||||
PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
|
||||
PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
|
||||
PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
|
||||
PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
|
||||
PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
|
||||
PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
|
||||
PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
|
||||
PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
|
||||
PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
|
||||
PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
|
||||
PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
|
||||
PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
|
||||
PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
|
||||
PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
|
||||
PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
|
||||
PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
|
||||
PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
|
||||
PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
|
||||
PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
|
||||
PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
|
||||
PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
|
||||
PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
|
||||
PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
|
||||
PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
|
||||
PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
|
||||
PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
|
||||
PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
|
||||
PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
|
||||
PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
|
||||
PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
|
||||
PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
|
||||
PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
|
||||
PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
|
||||
PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
|
||||
PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
|
||||
PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
|
||||
PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
|
||||
PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
|
||||
PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
|
||||
PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
|
||||
PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
|
||||
PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
|
||||
PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
|
||||
PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
|
||||
PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
|
||||
PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
|
||||
PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
|
||||
PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
|
||||
PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
|
||||
PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
|
||||
PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
|
||||
PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
|
||||
PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
|
||||
PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
|
||||
PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
|
||||
PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
|
||||
PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
|
||||
PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
|
||||
PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
|
||||
PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
|
||||
PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
|
||||
PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
|
||||
PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
|
||||
PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
|
||||
PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
|
||||
PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
|
||||
PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
|
||||
PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
|
||||
PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
|
||||
PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
|
||||
PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
|
||||
PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
|
||||
PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
|
||||
/* these pin groups only have pullup and pull down control */
|
||||
PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
|
||||
PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
|
||||
PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
|
||||
PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
|
||||
PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
|
||||
PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
|
||||
PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
|
||||
PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
|
||||
PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
|
||||
};
|
||||
|
||||
void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max)
|
||||
{
|
||||
*pg = tegra_soc_pingroups;
|
||||
*pg_max = TEGRA_MAX_PINGROUP;
|
||||
*pgdrive = tegra_soc_drive_pingroups;
|
||||
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
|
||||
}
|
||||
|
||||
|
|
@ -1,376 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
|
||||
*
|
||||
* Common pinmux configurations for Tegra30 SoCs
|
||||
*
|
||||
* Copyright (C) 2010,2011 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/pinmux-tegra30.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
#define PINGROUP_REG_A 0x868
|
||||
#define MUXCTL_REG_A 0x3000
|
||||
|
||||
#define DRIVE_PINGROUP(pg_name, r) \
|
||||
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.reg_bank = 0, \
|
||||
.reg = ((r) - PINGROUP_REG_A) \
|
||||
}
|
||||
|
||||
static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
|
||||
DRIVE_PINGROUP(AO1, 0x868),
|
||||
DRIVE_PINGROUP(AO2, 0x86c),
|
||||
DRIVE_PINGROUP(AT1, 0x870),
|
||||
DRIVE_PINGROUP(AT2, 0x874),
|
||||
DRIVE_PINGROUP(AT3, 0x878),
|
||||
DRIVE_PINGROUP(AT4, 0x87c),
|
||||
DRIVE_PINGROUP(AT5, 0x880),
|
||||
DRIVE_PINGROUP(CDEV1, 0x884),
|
||||
DRIVE_PINGROUP(CDEV2, 0x888),
|
||||
DRIVE_PINGROUP(CSUS, 0x88c),
|
||||
DRIVE_PINGROUP(DAP1, 0x890),
|
||||
DRIVE_PINGROUP(DAP2, 0x894),
|
||||
DRIVE_PINGROUP(DAP3, 0x898),
|
||||
DRIVE_PINGROUP(DAP4, 0x89c),
|
||||
DRIVE_PINGROUP(DBG, 0x8a0),
|
||||
DRIVE_PINGROUP(LCD1, 0x8a4),
|
||||
DRIVE_PINGROUP(LCD2, 0x8a8),
|
||||
DRIVE_PINGROUP(SDIO2, 0x8ac),
|
||||
DRIVE_PINGROUP(SDIO3, 0x8b0),
|
||||
DRIVE_PINGROUP(SPI, 0x8b4),
|
||||
DRIVE_PINGROUP(UAA, 0x8b8),
|
||||
DRIVE_PINGROUP(UAB, 0x8bc),
|
||||
DRIVE_PINGROUP(UART2, 0x8c0),
|
||||
DRIVE_PINGROUP(UART3, 0x8c4),
|
||||
DRIVE_PINGROUP(VI1, 0x8c8),
|
||||
DRIVE_PINGROUP(SDIO1, 0x8ec),
|
||||
DRIVE_PINGROUP(CRT, 0x8f8),
|
||||
DRIVE_PINGROUP(DDC, 0x8fc),
|
||||
DRIVE_PINGROUP(GMA, 0x900),
|
||||
DRIVE_PINGROUP(GMB, 0x904),
|
||||
DRIVE_PINGROUP(GMC, 0x908),
|
||||
DRIVE_PINGROUP(GMD, 0x90c),
|
||||
DRIVE_PINGROUP(GME, 0x910),
|
||||
DRIVE_PINGROUP(GMF, 0x914),
|
||||
DRIVE_PINGROUP(GMG, 0x918),
|
||||
DRIVE_PINGROUP(GMH, 0x91c),
|
||||
DRIVE_PINGROUP(OWR, 0x920),
|
||||
DRIVE_PINGROUP(UAD, 0x924),
|
||||
DRIVE_PINGROUP(GPV, 0x928),
|
||||
DRIVE_PINGROUP(DEV3, 0x92c),
|
||||
DRIVE_PINGROUP(CEC, 0x938),
|
||||
};
|
||||
|
||||
#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
|
||||
[TEGRA_PINGROUP_ ## pg_name] = { \
|
||||
.name = #pg_name, \
|
||||
.vddio = TEGRA_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
TEGRA_MUX_ ## f0, \
|
||||
TEGRA_MUX_ ## f1, \
|
||||
TEGRA_MUX_ ## f2, \
|
||||
TEGRA_MUX_ ## f3, \
|
||||
}, \
|
||||
.func_safe = TEGRA_MUX_ ## fs, \
|
||||
.tri_bank = 1, \
|
||||
.tri_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.tri_bit = 4, \
|
||||
.mux_bank = 1, \
|
||||
.mux_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.mux_bit = 0, \
|
||||
.pupd_bank = 1, \
|
||||
.pupd_reg = ((reg) - MUXCTL_REG_A), \
|
||||
.pupd_bit = 2, \
|
||||
.io_default = TEGRA_PIN_ ## iod, \
|
||||
.od_bit = 6, \
|
||||
.lock_bit = 7, \
|
||||
.ioreset_bit = 8, \
|
||||
}
|
||||
|
||||
static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
|
||||
/* NAME VDD f0 f1 f2 f3 fSafe io reg */
|
||||
PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
|
||||
PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
|
||||
PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
|
||||
PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
|
||||
PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
|
||||
PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
|
||||
PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
|
||||
PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
|
||||
PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
|
||||
PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
|
||||
PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
|
||||
PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
|
||||
PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
|
||||
PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
|
||||
PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
|
||||
PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
|
||||
PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
|
||||
PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
|
||||
PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
|
||||
PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
|
||||
PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
|
||||
PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
|
||||
PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
|
||||
PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
|
||||
PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
|
||||
PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
|
||||
PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
|
||||
PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
|
||||
PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
|
||||
PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
|
||||
PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
|
||||
PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
|
||||
PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
|
||||
PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
|
||||
PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
|
||||
PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
|
||||
PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
|
||||
PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
|
||||
PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
|
||||
PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
|
||||
PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
|
||||
PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
|
||||
PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
|
||||
PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
|
||||
PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
|
||||
PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
|
||||
PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
|
||||
PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
|
||||
PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
|
||||
PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
|
||||
PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
|
||||
PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
|
||||
PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
|
||||
PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
|
||||
PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
|
||||
PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
|
||||
PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
|
||||
PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
|
||||
PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
|
||||
PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
|
||||
PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
|
||||
PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
|
||||
PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
|
||||
PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
|
||||
PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
|
||||
PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
|
||||
PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
|
||||
PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
|
||||
PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
|
||||
PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
|
||||
PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
|
||||
PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
|
||||
PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
|
||||
PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
|
||||
PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
|
||||
PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
|
||||
PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
|
||||
PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
|
||||
PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
|
||||
PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
|
||||
PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
|
||||
PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
|
||||
PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
|
||||
PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
|
||||
PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
|
||||
PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
|
||||
PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
|
||||
PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
|
||||
PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
|
||||
PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
|
||||
PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
|
||||
PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
|
||||
PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
|
||||
PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
|
||||
PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
|
||||
PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
|
||||
PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
|
||||
PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
|
||||
PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
|
||||
PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
|
||||
PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
|
||||
PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
|
||||
PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
|
||||
PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
|
||||
PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
|
||||
PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
|
||||
PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
|
||||
PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
|
||||
PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
|
||||
PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
|
||||
PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
|
||||
PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
|
||||
PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
|
||||
PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
|
||||
PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
|
||||
PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
|
||||
PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
|
||||
PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
|
||||
PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
|
||||
PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
|
||||
PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
|
||||
PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
|
||||
PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
|
||||
PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
|
||||
PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
|
||||
PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
|
||||
PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
|
||||
PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
|
||||
PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
|
||||
PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
|
||||
PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
|
||||
PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
|
||||
PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
|
||||
PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
|
||||
PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
|
||||
PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
|
||||
PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
|
||||
PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
|
||||
PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
|
||||
PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
|
||||
PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
|
||||
PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
|
||||
PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
|
||||
PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
|
||||
PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
|
||||
PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
|
||||
PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
|
||||
PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
|
||||
PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
|
||||
PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
|
||||
PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
|
||||
PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
|
||||
PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
|
||||
PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
|
||||
PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
|
||||
PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
|
||||
PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
|
||||
PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
|
||||
PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
|
||||
PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
|
||||
PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
|
||||
PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
|
||||
PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
|
||||
PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
|
||||
PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
|
||||
PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
|
||||
PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
|
||||
PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
|
||||
PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
|
||||
PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
|
||||
PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
|
||||
PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
|
||||
PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
|
||||
PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
|
||||
PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
|
||||
PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
|
||||
PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
|
||||
PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
|
||||
PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
|
||||
PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
|
||||
PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
|
||||
PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
|
||||
PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
|
||||
PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
|
||||
PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
|
||||
PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
|
||||
PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
|
||||
PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
|
||||
PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
|
||||
PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
|
||||
PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
|
||||
PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
|
||||
PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
|
||||
PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
|
||||
PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
|
||||
PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
|
||||
PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
|
||||
PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
|
||||
PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
|
||||
PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
|
||||
PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
|
||||
PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
|
||||
PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
|
||||
PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
|
||||
PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
|
||||
PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
|
||||
PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
|
||||
PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
|
||||
PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
|
||||
PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
|
||||
PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
|
||||
PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
|
||||
PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
|
||||
PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
|
||||
PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
|
||||
PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
|
||||
PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
|
||||
PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
|
||||
PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
|
||||
PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
|
||||
PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
|
||||
PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
|
||||
PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
|
||||
PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
|
||||
PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
|
||||
PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
|
||||
PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
|
||||
PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
|
||||
PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
|
||||
PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
|
||||
PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
|
||||
PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
|
||||
PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
|
||||
PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
|
||||
PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
|
||||
PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
|
||||
PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
|
||||
PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
|
||||
PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
|
||||
PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
|
||||
PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
|
||||
PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
|
||||
PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
|
||||
PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
|
||||
PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
|
||||
PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
|
||||
PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
|
||||
PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
|
||||
PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
|
||||
};
|
||||
|
||||
void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
|
||||
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
|
||||
int *pgdrive_max)
|
||||
{
|
||||
*pg = tegra_soc_pingroups;
|
||||
*pg_max = TEGRA_MAX_PINGROUP;
|
||||
*pgdrive = tegra_soc_drive_pingroups;
|
||||
*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
|
||||
}
|
||||
|
||||
|
|
@ -1,987 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-tegra/pinmux.c
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#define HSM_EN(reg) (((reg) >> 2) & 0x1)
|
||||
#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
|
||||
#define LPMD(reg) (((reg) >> 4) & 0x3)
|
||||
#define DRVDN(reg) (((reg) >> 12) & 0x1f)
|
||||
#define DRVUP(reg) (((reg) >> 20) & 0x1f)
|
||||
#define SLWR(reg) (((reg) >> 28) & 0x3)
|
||||
#define SLWF(reg) (((reg) >> 30) & 0x3)
|
||||
|
||||
static const struct tegra_pingroup_desc *pingroups;
|
||||
static const struct tegra_drive_pingroup_desc *drive_pingroups;
|
||||
static int pingroup_max;
|
||||
static int drive_max;
|
||||
|
||||
static char *tegra_mux_names[TEGRA_MAX_MUX] = {
|
||||
[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
|
||||
[TEGRA_MUX_APB_CLK] = "APB_CLK",
|
||||
[TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
|
||||
[TEGRA_MUX_CRT] = "CRT",
|
||||
[TEGRA_MUX_DAP1] = "DAP1",
|
||||
[TEGRA_MUX_DAP2] = "DAP2",
|
||||
[TEGRA_MUX_DAP3] = "DAP3",
|
||||
[TEGRA_MUX_DAP4] = "DAP4",
|
||||
[TEGRA_MUX_DAP5] = "DAP5",
|
||||
[TEGRA_MUX_DISPLAYA] = "DISPLAYA",
|
||||
[TEGRA_MUX_DISPLAYB] = "DISPLAYB",
|
||||
[TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
|
||||
[TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
|
||||
[TEGRA_MUX_GMI] = "GMI",
|
||||
[TEGRA_MUX_GMI_INT] = "GMI_INT",
|
||||
[TEGRA_MUX_HDMI] = "HDMI",
|
||||
[TEGRA_MUX_I2C] = "I2C",
|
||||
[TEGRA_MUX_I2C2] = "I2C2",
|
||||
[TEGRA_MUX_I2C3] = "I2C3",
|
||||
[TEGRA_MUX_IDE] = "IDE",
|
||||
[TEGRA_MUX_IRDA] = "IRDA",
|
||||
[TEGRA_MUX_KBC] = "KBC",
|
||||
[TEGRA_MUX_MIO] = "MIO",
|
||||
[TEGRA_MUX_MIPI_HS] = "MIPI_HS",
|
||||
[TEGRA_MUX_NAND] = "NAND",
|
||||
[TEGRA_MUX_OSC] = "OSC",
|
||||
[TEGRA_MUX_OWR] = "OWR",
|
||||
[TEGRA_MUX_PCIE] = "PCIE",
|
||||
[TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
|
||||
[TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
|
||||
[TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
|
||||
[TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
|
||||
[TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
|
||||
[TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
|
||||
[TEGRA_MUX_PWM] = "PWM",
|
||||
[TEGRA_MUX_PWR_INTR] = "PWR_INTR",
|
||||
[TEGRA_MUX_PWR_ON] = "PWR_ON",
|
||||
[TEGRA_MUX_RTCK] = "RTCK",
|
||||
[TEGRA_MUX_SDIO1] = "SDIO1",
|
||||
[TEGRA_MUX_SDIO2] = "SDIO2",
|
||||
[TEGRA_MUX_SDIO3] = "SDIO3",
|
||||
[TEGRA_MUX_SDIO4] = "SDIO4",
|
||||
[TEGRA_MUX_SFLASH] = "SFLASH",
|
||||
[TEGRA_MUX_SPDIF] = "SPDIF",
|
||||
[TEGRA_MUX_SPI1] = "SPI1",
|
||||
[TEGRA_MUX_SPI2] = "SPI2",
|
||||
[TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
|
||||
[TEGRA_MUX_SPI3] = "SPI3",
|
||||
[TEGRA_MUX_SPI4] = "SPI4",
|
||||
[TEGRA_MUX_TRACE] = "TRACE",
|
||||
[TEGRA_MUX_TWC] = "TWC",
|
||||
[TEGRA_MUX_UARTA] = "UARTA",
|
||||
[TEGRA_MUX_UARTB] = "UARTB",
|
||||
[TEGRA_MUX_UARTC] = "UARTC",
|
||||
[TEGRA_MUX_UARTD] = "UARTD",
|
||||
[TEGRA_MUX_UARTE] = "UARTE",
|
||||
[TEGRA_MUX_ULPI] = "ULPI",
|
||||
[TEGRA_MUX_VI] = "VI",
|
||||
[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
|
||||
[TEGRA_MUX_XIO] = "XIO",
|
||||
[TEGRA_MUX_BLINK] = "BLINK",
|
||||
[TEGRA_MUX_CEC] = "CEC",
|
||||
[TEGRA_MUX_CLK12] = "CLK12",
|
||||
[TEGRA_MUX_DAP] = "DAP",
|
||||
[TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
|
||||
[TEGRA_MUX_DDR] = "DDR",
|
||||
[TEGRA_MUX_DEV3] = "DEV3",
|
||||
[TEGRA_MUX_DTV] = "DTV",
|
||||
[TEGRA_MUX_VI_ALT1] = "VI_ALT1",
|
||||
[TEGRA_MUX_VI_ALT2] = "VI_ALT2",
|
||||
[TEGRA_MUX_VI_ALT3] = "VI_ALT3",
|
||||
[TEGRA_MUX_EMC_DLL] = "EMC_DLL",
|
||||
[TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
|
||||
[TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
|
||||
[TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
|
||||
[TEGRA_MUX_GMI_ALT] = "GMI_ALT",
|
||||
[TEGRA_MUX_HDA] = "HDA",
|
||||
[TEGRA_MUX_HSI] = "HSI",
|
||||
[TEGRA_MUX_I2C4] = "I2C4",
|
||||
[TEGRA_MUX_I2C5] = "I2C5",
|
||||
[TEGRA_MUX_I2CPWR] = "I2CPWR",
|
||||
[TEGRA_MUX_I2S0] = "I2S0",
|
||||
[TEGRA_MUX_I2S1] = "I2S1",
|
||||
[TEGRA_MUX_I2S2] = "I2S2",
|
||||
[TEGRA_MUX_I2S3] = "I2S3",
|
||||
[TEGRA_MUX_I2S4] = "I2S4",
|
||||
[TEGRA_MUX_NAND_ALT] = "NAND_ALT",
|
||||
[TEGRA_MUX_POPSDIO4] = "POPSDIO4",
|
||||
[TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
|
||||
[TEGRA_MUX_PWM0] = "PWM0",
|
||||
[TEGRA_MUX_PWM1] = "PWM2",
|
||||
[TEGRA_MUX_PWM2] = "PWM2",
|
||||
[TEGRA_MUX_PWM3] = "PWM3",
|
||||
[TEGRA_MUX_SATA] = "SATA",
|
||||
[TEGRA_MUX_SPI5] = "SPI5",
|
||||
[TEGRA_MUX_SPI6] = "SPI6",
|
||||
[TEGRA_MUX_SYSCLK] = "SYSCLK",
|
||||
[TEGRA_MUX_VGP1] = "VGP1",
|
||||
[TEGRA_MUX_VGP2] = "VGP2",
|
||||
[TEGRA_MUX_VGP3] = "VGP3",
|
||||
[TEGRA_MUX_VGP4] = "VGP4",
|
||||
[TEGRA_MUX_VGP5] = "VGP5",
|
||||
[TEGRA_MUX_VGP6] = "VGP6",
|
||||
[TEGRA_MUX_SAFE] = "<safe>",
|
||||
};
|
||||
|
||||
static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
|
||||
[TEGRA_DRIVE_DIV_8] = "DIV_8",
|
||||
[TEGRA_DRIVE_DIV_4] = "DIV_4",
|
||||
[TEGRA_DRIVE_DIV_2] = "DIV_2",
|
||||
[TEGRA_DRIVE_DIV_1] = "DIV_1",
|
||||
};
|
||||
|
||||
static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
|
||||
[TEGRA_SLEW_FASTEST] = "FASTEST",
|
||||
[TEGRA_SLEW_FAST] = "FAST",
|
||||
[TEGRA_SLEW_SLOW] = "SLOW",
|
||||
[TEGRA_SLEW_SLOWEST] = "SLOWEST",
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(mux_lock);
|
||||
|
||||
static const char *pingroup_name(int pg)
|
||||
{
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return pingroups[pg].name;
|
||||
}
|
||||
|
||||
static const char *func_name(enum tegra_mux_func func)
|
||||
{
|
||||
if (func == TEGRA_MUX_RSVD1)
|
||||
return "RSVD1";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD2)
|
||||
return "RSVD2";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD3)
|
||||
return "RSVD3";
|
||||
|
||||
if (func == TEGRA_MUX_RSVD4)
|
||||
return "RSVD4";
|
||||
|
||||
if (func == TEGRA_MUX_NONE)
|
||||
return "NONE";
|
||||
|
||||
if (func < 0 || func >= TEGRA_MAX_MUX)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_mux_names[func];
|
||||
}
|
||||
|
||||
|
||||
static const char *tri_name(unsigned long val)
|
||||
{
|
||||
return val ? "TRISTATE" : "NORMAL";
|
||||
}
|
||||
|
||||
static const char *pupd_name(unsigned long val)
|
||||
{
|
||||
switch (val) {
|
||||
case 0:
|
||||
return "NORMAL";
|
||||
|
||||
case 1:
|
||||
return "PULL_DOWN";
|
||||
|
||||
case 2:
|
||||
return "PULL_UP";
|
||||
|
||||
default:
|
||||
return "RSVD";
|
||||
}
|
||||
}
|
||||
|
||||
static int nbanks;
|
||||
static void __iomem **regs;
|
||||
|
||||
static inline u32 pg_readl(u32 bank, u32 reg)
|
||||
{
|
||||
return readl(regs[bank] + reg);
|
||||
}
|
||||
|
||||
static inline void pg_writel(u32 val, u32 bank, u32 reg)
|
||||
{
|
||||
writel(val, regs[bank] + reg);
|
||||
}
|
||||
|
||||
static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
|
||||
{
|
||||
int mux = -1;
|
||||
int i;
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
int pg = config->pingroup;
|
||||
enum tegra_mux_func func = config->func;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].mux_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (func < 0)
|
||||
return -ERANGE;
|
||||
|
||||
if (func == TEGRA_MUX_SAFE)
|
||||
func = pingroups[pg].func_safe;
|
||||
|
||||
if (func & TEGRA_MUX_RSVD) {
|
||||
mux = func & 0x3;
|
||||
} else {
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (pingroups[pg].funcs[i] == func) {
|
||||
mux = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mux < 0)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
|
||||
reg &= ~(0x3 << pingroups[pg].mux_bit);
|
||||
reg |= mux << pingroups[pg].mux_bit;
|
||||
pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].tri_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
|
||||
reg &= ~(0x1 << pingroups[pg].tri_bit);
|
||||
if (tristate)
|
||||
reg |= 1 << pingroups[pg].tri_bit;
|
||||
pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
|
||||
{
|
||||
unsigned long reg;
|
||||
unsigned long flags;
|
||||
|
||||
if (pg < 0 || pg >= pingroup_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pingroups[pg].pupd_reg < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (pupd != TEGRA_PUPD_NORMAL &&
|
||||
pupd != TEGRA_PUPD_PULL_DOWN &&
|
||||
pupd != TEGRA_PUPD_PULL_UP)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
|
||||
reg &= ~(0x3 << pingroups[pg].pupd_bit);
|
||||
reg |= pupd << pingroups[pg].pupd_bit;
|
||||
pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
|
||||
{
|
||||
int pingroup = config->pingroup;
|
||||
enum tegra_mux_func func = config->func;
|
||||
enum tegra_pullupdown pupd = config->pupd;
|
||||
enum tegra_tristate tristate = config->tristate;
|
||||
int err;
|
||||
|
||||
if (pingroups[pingroup].mux_reg >= 0) {
|
||||
err = tegra_pinmux_set_func(config);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
|
||||
pingroup_name(pingroup), func_name(func), err);
|
||||
}
|
||||
|
||||
if (pingroups[pingroup].pupd_reg >= 0) {
|
||||
err = tegra_pinmux_set_pullupdown(pingroup, pupd);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
|
||||
pingroup_name(pingroup), pupd_name(pupd), err);
|
||||
}
|
||||
|
||||
if (pingroups[pingroup].tri_reg >= 0) {
|
||||
err = tegra_pinmux_set_tristate(pingroup, tristate);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
|
||||
pingroup_name(pingroup), tri_name(func), err);
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
tegra_pinmux_config_pingroup(&config[i]);
|
||||
}
|
||||
|
||||
static const char *drive_pinmux_name(int pg)
|
||||
{
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return drive_pingroups[pg].name;
|
||||
}
|
||||
|
||||
static const char *enable_name(unsigned long val)
|
||||
{
|
||||
return val ? "ENABLE" : "DISABLE";
|
||||
}
|
||||
|
||||
static const char *drive_name(unsigned long val)
|
||||
{
|
||||
if (val >= TEGRA_MAX_DRIVE)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_drive_names[val];
|
||||
}
|
||||
|
||||
static const char *slew_name(unsigned long val)
|
||||
{
|
||||
if (val >= TEGRA_MAX_SLEW)
|
||||
return "<UNKNOWN>";
|
||||
|
||||
return tegra_slew_names[val];
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
if (hsm == TEGRA_HSM_ENABLE)
|
||||
reg |= (1 << 2);
|
||||
else
|
||||
reg &= ~(1 << 2);
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
if (schmitt == TEGRA_SCHMITT_ENABLE)
|
||||
reg |= (1 << 3);
|
||||
else
|
||||
reg &= ~(1 << 3);
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 4);
|
||||
reg |= drive << 4;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_pull_down(int pg,
|
||||
enum tegra_pull_strength pull_down)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x1f << 12);
|
||||
reg |= pull_down << 12;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_pull_up(int pg,
|
||||
enum tegra_pull_strength pull_up)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x1f << 12);
|
||||
reg |= pull_up << 12;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_slew_rising(int pg,
|
||||
enum tegra_slew slew_rising)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 28);
|
||||
reg |= slew_rising << 28;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drive_pinmux_set_slew_falling(int pg,
|
||||
enum tegra_slew slew_falling)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
if (pg < 0 || pg >= drive_max)
|
||||
return -ERANGE;
|
||||
|
||||
if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&mux_lock, flags);
|
||||
|
||||
reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
reg &= ~(0x3 << 30);
|
||||
reg |= slew_falling << 30;
|
||||
pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
|
||||
|
||||
spin_unlock_irqrestore(&mux_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_drive_pinmux_config_pingroup(int pingroup,
|
||||
enum tegra_hsm hsm,
|
||||
enum tegra_schmitt schmitt,
|
||||
enum tegra_drive drive,
|
||||
enum tegra_pull_strength pull_down,
|
||||
enum tegra_pull_strength pull_up,
|
||||
enum tegra_slew slew_rising,
|
||||
enum tegra_slew slew_falling)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
enable_name(hsm), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
enable_name(schmitt), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_drive(pingroup, drive);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
drive_name(drive), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
pull_down, err);
|
||||
|
||||
err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
pull_up, err);
|
||||
|
||||
err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
slew_name(slew_rising), err);
|
||||
|
||||
err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
|
||||
drive_pinmux_name(pingroup),
|
||||
slew_name(slew_falling), err);
|
||||
}
|
||||
|
||||
void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
tegra_drive_pinmux_config_pingroup(config[i].pingroup,
|
||||
config[i].hsm,
|
||||
config[i].schmitt,
|
||||
config[i].drive,
|
||||
config[i].pull_down,
|
||||
config[i].pull_up,
|
||||
config[i].slew_rising,
|
||||
config[i].slew_falling);
|
||||
}
|
||||
|
||||
void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
struct tegra_pingroup_config c;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
int err;
|
||||
c = config[i];
|
||||
if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
|
||||
WARN_ON(1);
|
||||
continue;
|
||||
}
|
||||
c.func = pingroups[c.pingroup].func_safe;
|
||||
err = tegra_pinmux_set_func(&c);
|
||||
if (err < 0)
|
||||
pr_err("%s: tegra_pinmux_set_func returned %d setting "
|
||||
"%s to %s\n", __func__, err,
|
||||
pingroup_name(c.pingroup), func_name(c.func));
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
int err;
|
||||
if (config[i].pingroup < 0 ||
|
||||
config[i].pingroup >= pingroup_max) {
|
||||
WARN_ON(1);
|
||||
continue;
|
||||
}
|
||||
err = tegra_pinmux_set_func(&config[i]);
|
||||
if (err < 0)
|
||||
pr_err("%s: tegra_pinmux_set_func returned %d setting "
|
||||
"%s to %s\n", __func__, err,
|
||||
pingroup_name(config[i].pingroup),
|
||||
func_name(config[i].func));
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_tristate tristate)
|
||||
{
|
||||
int i;
|
||||
int err;
|
||||
int pingroup;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
pingroup = config[i].pingroup;
|
||||
if (pingroups[pingroup].tri_reg >= 0) {
|
||||
err = tegra_pinmux_set_tristate(pingroup, tristate);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s tristate"
|
||||
" to %s: %d\n", pingroup_name(pingroup),
|
||||
tri_name(tristate), err);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
|
||||
int len, enum tegra_pullupdown pupd)
|
||||
{
|
||||
int i;
|
||||
int err;
|
||||
int pingroup;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
pingroup = config[i].pingroup;
|
||||
if (pingroups[pingroup].pupd_reg >= 0) {
|
||||
err = tegra_pinmux_set_pullupdown(pingroup, pupd);
|
||||
if (err < 0)
|
||||
pr_err("pinmux: can't set pingroup %s pullupdown"
|
||||
" to %s: %d\n", pingroup_name(pingroup),
|
||||
pupd_name(pupd), err);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
{ .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
{ .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
|
||||
static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int i;
|
||||
int config_bad = 0;
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
|
||||
|
||||
if (match)
|
||||
((pinmux_init)(match->data))(&pingroups, &pingroup_max,
|
||||
&drive_pingroups, &drive_max);
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
else
|
||||
/* no device tree available, so we must be on tegra20 */
|
||||
tegra20_pinmux_init(&pingroups, &pingroup_max,
|
||||
&drive_pingroups, &drive_max);
|
||||
#else
|
||||
pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
|
||||
#endif
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res)
|
||||
break;
|
||||
}
|
||||
nbanks = i;
|
||||
|
||||
for (i = 0; i < pingroup_max; i++) {
|
||||
if (pingroups[i].tri_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
|
||||
if (pingroups[i].mux_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
|
||||
if (pingroups[i].pupd_bank >= nbanks) {
|
||||
dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < drive_max; i++) {
|
||||
if (drive_pingroups[i].reg_bank >= nbanks) {
|
||||
dev_err(&pdev->dev,
|
||||
"drive pingroup %d: bad reg_bank\n", i);
|
||||
config_bad = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (config_bad)
|
||||
return -ENODEV;
|
||||
|
||||
regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "Can't alloc regs pointer\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
for (i = 0; i < nbanks; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "Missing MEM resource\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, res->start,
|
||||
resource_size(res),
|
||||
dev_name(&pdev->dev))) {
|
||||
dev_err(&pdev->dev,
|
||||
"Couldn't request MEM resource %d\n", i);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
regs[i] = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!regs) {
|
||||
dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_pinmux_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-pinmux",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_pinmux_of_match,
|
||||
},
|
||||
.probe = tegra_pinmux_probe,
|
||||
};
|
||||
|
||||
static int __init tegra_pinmux_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_pinmux_driver);
|
||||
}
|
||||
postcore_initcall(tegra_pinmux_init);
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static void dbg_pad_field(struct seq_file *s, int len)
|
||||
{
|
||||
seq_putc(s, ',');
|
||||
|
||||
while (len-- > -1)
|
||||
seq_putc(s, ' ');
|
||||
}
|
||||
|
||||
static int dbg_pinmux_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
int i;
|
||||
int len;
|
||||
|
||||
for (i = 0; i < pingroup_max; i++) {
|
||||
unsigned long reg;
|
||||
unsigned long tri;
|
||||
unsigned long mux;
|
||||
unsigned long pupd;
|
||||
|
||||
seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
|
||||
len = strlen(pingroups[i].name);
|
||||
dbg_pad_field(s, 5 - len);
|
||||
|
||||
if (pingroups[i].mux_reg < 0) {
|
||||
seq_printf(s, "TEGRA_MUX_NONE");
|
||||
len = strlen("NONE");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].mux_bank,
|
||||
pingroups[i].mux_reg);
|
||||
mux = (reg >> pingroups[i].mux_bit) & 0x3;
|
||||
if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
|
||||
seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
|
||||
len = 5;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_MUX_%s",
|
||||
tegra_mux_names[pingroups[i].funcs[mux]]);
|
||||
len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
|
||||
}
|
||||
}
|
||||
dbg_pad_field(s, 13-len);
|
||||
|
||||
if (pingroups[i].pupd_reg < 0) {
|
||||
seq_printf(s, "TEGRA_PUPD_NORMAL");
|
||||
len = strlen("NORMAL");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].pupd_bank,
|
||||
pingroups[i].pupd_reg);
|
||||
pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
|
||||
seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
|
||||
len = strlen(pupd_name(pupd));
|
||||
}
|
||||
dbg_pad_field(s, 9 - len);
|
||||
|
||||
if (pingroups[i].tri_reg < 0) {
|
||||
seq_printf(s, "TEGRA_TRI_NORMAL");
|
||||
} else {
|
||||
reg = pg_readl(pingroups[i].tri_bank,
|
||||
pingroups[i].tri_reg);
|
||||
tri = (reg >> pingroups[i].tri_bit) & 0x1;
|
||||
|
||||
seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
|
||||
}
|
||||
seq_printf(s, "},\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dbg_pinmux_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, dbg_pinmux_show, &inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations debug_fops = {
|
||||
.open = dbg_pinmux_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
int i;
|
||||
int len;
|
||||
|
||||
for (i = 0; i < drive_max; i++) {
|
||||
u32 reg;
|
||||
|
||||
seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
|
||||
drive_pingroups[i].name);
|
||||
len = strlen(drive_pingroups[i].name);
|
||||
dbg_pad_field(s, 7 - len);
|
||||
|
||||
|
||||
reg = pg_readl(drive_pingroups[i].reg_bank,
|
||||
drive_pingroups[i].reg);
|
||||
if (HSM_EN(reg)) {
|
||||
seq_printf(s, "TEGRA_HSM_ENABLE");
|
||||
len = 16;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_HSM_DISABLE");
|
||||
len = 17;
|
||||
}
|
||||
dbg_pad_field(s, 17 - len);
|
||||
|
||||
if (SCHMT_EN(reg)) {
|
||||
seq_printf(s, "TEGRA_SCHMITT_ENABLE");
|
||||
len = 21;
|
||||
} else {
|
||||
seq_printf(s, "TEGRA_SCHMITT_DISABLE");
|
||||
len = 22;
|
||||
}
|
||||
dbg_pad_field(s, 22 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
|
||||
len = strlen(drive_name(LPMD(reg)));
|
||||
dbg_pad_field(s, 5 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
|
||||
len = DRVDN(reg) < 10 ? 1 : 2;
|
||||
dbg_pad_field(s, 2 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
|
||||
len = DRVUP(reg) < 10 ? 1 : 2;
|
||||
dbg_pad_field(s, 2 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
|
||||
len = strlen(slew_name(SLWR(reg)));
|
||||
dbg_pad_field(s, 7 - len);
|
||||
|
||||
seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
|
||||
|
||||
seq_printf(s, "},\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations debug_drive_fops = {
|
||||
.open = dbg_drive_pinmux_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int __init tegra_pinmux_debuginit(void)
|
||||
{
|
||||
(void) debugfs_create_file("tegra_pinmux", S_IRUGO,
|
||||
NULL, NULL, &debug_fops);
|
||||
(void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
|
||||
NULL, NULL, &debug_drive_fops);
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tegra_pinmux_debuginit);
|
||||
#endif
|
||||
|
|
@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
|
|||
err = -ENXIO;
|
||||
goto err1;
|
||||
}
|
||||
tegra_gpio_enable(ulpi_config->reset_gpio);
|
||||
gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
|
||||
gpio_direction_output(ulpi_config->reset_gpio, 0);
|
||||
phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
|
||||
|
|
|
|||
|
|
@ -26,10 +26,10 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/gpio-tegra.h>
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/suspend.h>
|
||||
|
||||
|
|
@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
|
|||
tegra_gpio_writel(val, reg);
|
||||
}
|
||||
|
||||
void tegra_gpio_enable(int gpio)
|
||||
static void tegra_gpio_enable(int gpio)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_gpio_enable);
|
||||
|
||||
void tegra_gpio_disable(int gpio)
|
||||
static void tegra_gpio_disable(int gpio)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_gpio_disable);
|
||||
|
||||
int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_request_gpio(offset);
|
||||
}
|
||||
|
||||
void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
pinctrl_free_gpio(offset);
|
||||
tegra_gpio_disable(offset);
|
||||
}
|
||||
|
||||
static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
|
||||
|
|
@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|||
static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
|
||||
tegra_gpio_enable(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
|||
{
|
||||
tegra_gpio_set(chip, offset, value);
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
|
||||
tegra_gpio_enable(offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|||
|
||||
static struct gpio_chip tegra_gpio_chip = {
|
||||
.label = "tegra-gpio",
|
||||
.request = tegra_gpio_request,
|
||||
.free = tegra_gpio_free,
|
||||
.direction_input = tegra_gpio_direction_input,
|
||||
.get = tegra_gpio_get,
|
||||
.direction_output = tegra_gpio_direction_output,
|
||||
.set = tegra_gpio_set,
|
||||
.to_irq = tegra_gpio_to_irq,
|
||||
.base = 0,
|
||||
.ngpio = TEGRA_NR_GPIOS,
|
||||
};
|
||||
|
||||
static void tegra_gpio_irq_ack(struct irq_data *d)
|
||||
|
|
@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
|
||||
spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
|
||||
|
||||
tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
|
||||
tegra_gpio_enable(gpio);
|
||||
|
||||
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
||||
__irq_set_handler_locked(d->irq, handle_level_irq);
|
||||
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
|
|
@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
|
|||
}
|
||||
postcore_initcall(tegra_gpio_init);
|
||||
|
||||
void tegra_gpio_config(struct tegra_gpio_table *table, int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
int gpio = table[i].gpio;
|
||||
|
||||
if (table[i].enable)
|
||||
tegra_gpio_enable(gpio);
|
||||
else
|
||||
tegra_gpio_disable(gpio);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
|
|
|
|||
|
|
@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate power gpio\n");
|
||||
goto err_power_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->power_gpio);
|
||||
gpio_direction_output(plat->power_gpio, 1);
|
||||
}
|
||||
|
||||
|
|
@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate cd gpio\n");
|
||||
goto err_cd_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->cd_gpio);
|
||||
gpio_direction_input(plat->cd_gpio);
|
||||
|
||||
rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
|
||||
|
|
@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
"failed to allocate wp gpio\n");
|
||||
goto err_wp_req;
|
||||
}
|
||||
tegra_gpio_enable(plat->wp_gpio);
|
||||
gpio_direction_input(plat->wp_gpio);
|
||||
}
|
||||
|
||||
|
|
@ -329,23 +326,17 @@ err_add_host:
|
|||
clk_disable(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
err_clk_get:
|
||||
if (gpio_is_valid(plat->wp_gpio)) {
|
||||
tegra_gpio_disable(plat->wp_gpio);
|
||||
if (gpio_is_valid(plat->wp_gpio))
|
||||
gpio_free(plat->wp_gpio);
|
||||
}
|
||||
err_wp_req:
|
||||
if (gpio_is_valid(plat->cd_gpio))
|
||||
free_irq(gpio_to_irq(plat->cd_gpio), host);
|
||||
err_cd_irq_req:
|
||||
if (gpio_is_valid(plat->cd_gpio)) {
|
||||
tegra_gpio_disable(plat->cd_gpio);
|
||||
if (gpio_is_valid(plat->cd_gpio))
|
||||
gpio_free(plat->cd_gpio);
|
||||
}
|
||||
err_cd_req:
|
||||
if (gpio_is_valid(plat->power_gpio)) {
|
||||
tegra_gpio_disable(plat->power_gpio);
|
||||
if (gpio_is_valid(plat->power_gpio))
|
||||
gpio_free(plat->power_gpio);
|
||||
}
|
||||
err_power_req:
|
||||
err_no_plat:
|
||||
sdhci_pltfm_free(pdev);
|
||||
|
|
@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
|
|||
|
||||
sdhci_remove_host(host, dead);
|
||||
|
||||
if (gpio_is_valid(plat->wp_gpio)) {
|
||||
tegra_gpio_disable(plat->wp_gpio);
|
||||
if (gpio_is_valid(plat->wp_gpio))
|
||||
gpio_free(plat->wp_gpio);
|
||||
}
|
||||
|
||||
if (gpio_is_valid(plat->cd_gpio)) {
|
||||
free_irq(gpio_to_irq(plat->cd_gpio), host);
|
||||
tegra_gpio_disable(plat->cd_gpio);
|
||||
gpio_free(plat->cd_gpio);
|
||||
}
|
||||
|
||||
if (gpio_is_valid(plat->power_gpio)) {
|
||||
tegra_gpio_disable(plat->power_gpio);
|
||||
if (gpio_is_valid(plat->power_gpio))
|
||||
gpio_free(plat->power_gpio);
|
||||
}
|
||||
|
||||
clk_disable(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
|
|
|
|||
|
|
@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
|
|||
return id;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_alias_get_id);
|
||||
|
||||
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
|
||||
u32 *pu)
|
||||
{
|
||||
const void *curv = cur;
|
||||
|
||||
if (!prop)
|
||||
return NULL;
|
||||
|
||||
if (!cur) {
|
||||
curv = prop->value;
|
||||
goto out_val;
|
||||
}
|
||||
|
||||
curv += sizeof(*cur);
|
||||
if (curv >= prop->value + prop->length)
|
||||
return NULL;
|
||||
|
||||
out_val:
|
||||
*pu = be32_to_cpup(curv);
|
||||
return curv;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_prop_next_u32);
|
||||
|
||||
const char *of_prop_next_string(struct property *prop, const char *cur)
|
||||
{
|
||||
const void *curv = cur;
|
||||
|
||||
if (!prop)
|
||||
return NULL;
|
||||
|
||||
if (!cur)
|
||||
return prop->value;
|
||||
|
||||
curv += strlen(cur) + 1;
|
||||
if (curv >= prop->value + prop->length)
|
||||
return NULL;
|
||||
|
||||
return curv;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_prop_next_string);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@
|
|||
|
||||
config PINCTRL
|
||||
bool
|
||||
depends on EXPERIMENTAL
|
||||
|
||||
if PINCTRL
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,9 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
|
|||
obj-$(CONFIG_PINCTRL) += core.o
|
||||
obj-$(CONFIG_PINMUX) += pinmux.o
|
||||
obj-$(CONFIG_PINCONF) += pinconf.o
|
||||
ifeq ($(CONFIG_OF),y)
|
||||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
|
||||
obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
|
||||
|
|
|
|||
|
|
@ -23,9 +23,11 @@
|
|||
#include <linux/sysfs.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include "core.h"
|
||||
#include "devicetree.h"
|
||||
#include "pinmux.h"
|
||||
#include "pinconf.h"
|
||||
|
||||
|
|
@ -45,7 +47,7 @@ struct pinctrl_maps {
|
|||
DEFINE_MUTEX(pinctrl_mutex);
|
||||
|
||||
/* Global list of pin control devices (struct pinctrl_dev) */
|
||||
static LIST_HEAD(pinctrldev_list);
|
||||
LIST_HEAD(pinctrldev_list);
|
||||
|
||||
/* List of pin controller handles (struct pinctrl) */
|
||||
static LIST_HEAD(pinctrl_list);
|
||||
|
|
@ -123,6 +125,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* pin_get_name_from_id() - look up a pin name from a pin id
|
||||
* @pctldev: the pin control device to lookup the pin on
|
||||
* @name: the name of the pin to look up
|
||||
*/
|
||||
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
|
||||
{
|
||||
const struct pin_desc *desc;
|
||||
|
||||
desc = pin_desc_get(pctldev, pin);
|
||||
if (desc == NULL) {
|
||||
dev_err(pctldev->dev, "failed to get pin(%d) name\n",
|
||||
pin);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return desc->name;
|
||||
}
|
||||
|
||||
/**
|
||||
* pin_is_valid() - check if pin exists on controller
|
||||
* @pctldev: the pin control device to check the pin on
|
||||
|
|
@ -318,9 +339,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
|
|||
const char *pin_group)
|
||||
{
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
unsigned ngroups = pctlops->get_groups_count(pctldev);
|
||||
unsigned group_selector = 0;
|
||||
|
||||
while (pctlops->list_groups(pctldev, group_selector) >= 0) {
|
||||
while (group_selector < ngroups) {
|
||||
const char *gname = pctlops->get_group_name(pctldev,
|
||||
group_selector);
|
||||
if (!strcmp(gname, pin_group)) {
|
||||
|
|
@ -516,11 +538,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
|
|||
|
||||
setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
|
||||
if (setting->pctldev == NULL) {
|
||||
dev_err(p->dev, "unknown pinctrl device %s in map entry",
|
||||
dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
|
||||
map->ctrl_dev_name);
|
||||
kfree(setting);
|
||||
/* Eventually, this should trigger deferred probe */
|
||||
return -ENODEV;
|
||||
/*
|
||||
* OK let us guess that the driver is not there yet, and
|
||||
* let's defer obtaining this pinctrl handle to later...
|
||||
*/
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
switch (map->type) {
|
||||
|
|
@ -579,6 +604,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
|
|||
}
|
||||
p->dev = dev;
|
||||
INIT_LIST_HEAD(&p->states);
|
||||
INIT_LIST_HEAD(&p->dt_maps);
|
||||
|
||||
ret = pinctrl_dt_to_map(p);
|
||||
if (ret < 0) {
|
||||
kfree(p);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
devname = dev_name(dev);
|
||||
|
||||
|
|
@ -662,6 +694,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
|
|||
kfree(state);
|
||||
}
|
||||
|
||||
pinctrl_dt_free_maps(p);
|
||||
|
||||
if (inlist)
|
||||
list_del(&p->node);
|
||||
kfree(p);
|
||||
|
|
@ -787,15 +821,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_select_state);
|
||||
|
||||
static void devm_pinctrl_release(struct device *dev, void *res)
|
||||
{
|
||||
pinctrl_put(*(struct pinctrl **)res);
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. This should probably be
|
||||
* marked with __initdata so it can be discarded after boot. This
|
||||
* function will perform a shallow copy for the mapping entries.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
* struct devm_pinctrl_get() - Resource managed pinctrl_get()
|
||||
* @dev: the device to obtain the handle for
|
||||
*
|
||||
* If there is a need to explicitly destroy the returned struct pinctrl,
|
||||
* devm_pinctrl_put() should be used, rather than plain pinctrl_put().
|
||||
*/
|
||||
int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
unsigned num_maps)
|
||||
struct pinctrl *devm_pinctrl_get(struct device *dev)
|
||||
{
|
||||
struct pinctrl **ptr, *p;
|
||||
|
||||
ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
|
||||
if (!ptr)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
p = pinctrl_get(dev);
|
||||
if (!IS_ERR(p)) {
|
||||
*ptr = p;
|
||||
devres_add(dev, ptr);
|
||||
} else {
|
||||
devres_free(ptr);
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_get);
|
||||
|
||||
static int devm_pinctrl_match(struct device *dev, void *res, void *data)
|
||||
{
|
||||
struct pinctrl **p = res;
|
||||
|
||||
return *p == data;
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_pinctrl_put() - Resource managed pinctrl_put()
|
||||
* @p: the pinctrl handle to release
|
||||
*
|
||||
* Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
|
||||
* this function will not need to be called and the resource management
|
||||
* code will ensure that the resource is freed.
|
||||
*/
|
||||
void devm_pinctrl_put(struct pinctrl *p)
|
||||
{
|
||||
WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
|
||||
devm_pinctrl_match, p));
|
||||
pinctrl_put(p);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
|
||||
|
||||
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
|
||||
bool dup, bool locked)
|
||||
{
|
||||
int i, ret;
|
||||
struct pinctrl_maps *maps_node;
|
||||
|
|
@ -851,20 +933,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
|||
}
|
||||
|
||||
maps_node->num_maps = num_maps;
|
||||
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
|
||||
if (!maps_node->maps) {
|
||||
pr_err("failed to duplicate mapping table\n");
|
||||
kfree(maps_node);
|
||||
return -ENOMEM;
|
||||
if (dup) {
|
||||
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
|
||||
GFP_KERNEL);
|
||||
if (!maps_node->maps) {
|
||||
pr_err("failed to duplicate mapping table\n");
|
||||
kfree(maps_node);
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
maps_node->maps = maps;
|
||||
}
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
if (!locked)
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
list_add_tail(&maps_node->node, &pinctrl_maps);
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
if (!locked)
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. This should probably be
|
||||
* marked with __initdata so it can be discarded after boot. This
|
||||
* function will perform a shallow copy for the mapping entries.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
*/
|
||||
int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
unsigned num_maps)
|
||||
{
|
||||
return pinctrl_register_map(maps, num_maps, true, false);
|
||||
}
|
||||
|
||||
void pinctrl_unregister_map(struct pinctrl_map const *map)
|
||||
{
|
||||
struct pinctrl_maps *maps_node;
|
||||
|
||||
list_for_each_entry(maps_node, &pinctrl_maps, node) {
|
||||
if (maps_node->maps == map) {
|
||||
list_del(&maps_node->node);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
static int pinctrl_pins_show(struct seq_file *s, void *what)
|
||||
|
|
@ -906,15 +1020,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
|
|||
{
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
unsigned selector = 0;
|
||||
unsigned ngroups, selector = 0;
|
||||
|
||||
ngroups = ops->get_groups_count(pctldev);
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
seq_puts(s, "registered pin groups:\n");
|
||||
while (ops->list_groups(pctldev, selector) >= 0) {
|
||||
while (selector < ngroups) {
|
||||
const unsigned *pins;
|
||||
unsigned num_pins;
|
||||
const char *gname = ops->get_group_name(pctldev, selector);
|
||||
const char *pname;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
|
|
@ -924,10 +1040,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
|
|||
seq_printf(s, "%s [ERROR GETTING PINS]\n",
|
||||
gname);
|
||||
else {
|
||||
seq_printf(s, "group: %s, pins = [ ", gname);
|
||||
for (i = 0; i < num_pins; i++)
|
||||
seq_printf(s, "%d ", pins[i]);
|
||||
seq_puts(s, "]\n");
|
||||
seq_printf(s, "group: %s\n", gname);
|
||||
for (i = 0; i < num_pins; i++) {
|
||||
pname = pin_get_name(pctldev, pins[i]);
|
||||
if (WARN_ON(!pname))
|
||||
return -EINVAL;
|
||||
seq_printf(s, "pin %d (%s)\n", pins[i], pname);
|
||||
}
|
||||
seq_puts(s, "\n");
|
||||
}
|
||||
selector++;
|
||||
}
|
||||
|
|
@ -1226,11 +1346,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
|
|||
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
|
||||
if (!ops ||
|
||||
!ops->list_groups ||
|
||||
!ops->get_groups_count ||
|
||||
!ops->get_group_name ||
|
||||
!ops->get_group_pins)
|
||||
return -EINVAL;
|
||||
|
||||
if (ops->dt_node_to_map && !ops->dt_free_map)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -52,12 +52,15 @@ struct pinctrl_dev {
|
|||
* @dev: the device using this pin control handle
|
||||
* @states: a list of states for this device
|
||||
* @state: the current state
|
||||
* @dt_maps: the mapping table chunks dynamically parsed from device tree for
|
||||
* this device, if any
|
||||
*/
|
||||
struct pinctrl {
|
||||
struct list_head node;
|
||||
struct device *dev;
|
||||
struct list_head states;
|
||||
struct pinctrl_state *state;
|
||||
struct list_head dt_maps;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
|
|||
* struct pinctrl_setting - an individual mux or config setting
|
||||
* @node: list node for struct pinctrl_settings's @settings field
|
||||
* @type: the type of setting
|
||||
* @pctldev: pin control device handling to be programmed
|
||||
* @pctldev: pin control device handling to be programmed. Not used for
|
||||
* PIN_MAP_TYPE_DUMMY_STATE.
|
||||
* @data: Data specific to the setting type
|
||||
*/
|
||||
struct pinctrl_setting {
|
||||
|
|
@ -144,6 +148,7 @@ struct pin_desc {
|
|||
|
||||
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
|
||||
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
|
||||
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
|
||||
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
|
||||
const char *pin_group);
|
||||
|
||||
|
|
@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
|
|||
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
|
||||
}
|
||||
|
||||
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
|
||||
bool dup, bool locked);
|
||||
void pinctrl_unregister_map(struct pinctrl_map const *map);
|
||||
|
||||
extern struct mutex pinctrl_mutex;
|
||||
extern struct list_head pinctrldev_list;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* Device tree integration for the pin control subsystem
|
||||
*
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "devicetree.h"
|
||||
|
||||
/**
|
||||
* struct pinctrl_dt_map - mapping table chunk parsed from device tree
|
||||
* @node: list node for struct pinctrl's @dt_maps field
|
||||
* @pctldev: the pin controller that allocated this struct, and will free it
|
||||
* @maps: the mapping table entries
|
||||
*/
|
||||
struct pinctrl_dt_map {
|
||||
struct list_head node;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_map *map;
|
||||
unsigned num_maps;
|
||||
};
|
||||
|
||||
static void dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
if (pctldev) {
|
||||
struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
ops->dt_free_map(pctldev, map, num_maps);
|
||||
} else {
|
||||
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
|
||||
kfree(map);
|
||||
}
|
||||
}
|
||||
|
||||
void pinctrl_dt_free_maps(struct pinctrl *p)
|
||||
{
|
||||
struct pinctrl_dt_map *dt_map, *n1;
|
||||
|
||||
list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
|
||||
pinctrl_unregister_map(dt_map->map);
|
||||
list_del(&dt_map->node);
|
||||
dt_free_map(dt_map->pctldev, dt_map->map,
|
||||
dt_map->num_maps);
|
||||
kfree(dt_map);
|
||||
}
|
||||
|
||||
of_node_put(p->dev->of_node);
|
||||
}
|
||||
|
||||
static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
|
||||
struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
int i;
|
||||
struct pinctrl_dt_map *dt_map;
|
||||
|
||||
/* Initialize common mapping table entry fields */
|
||||
for (i = 0; i < num_maps; i++) {
|
||||
map[i].dev_name = dev_name(p->dev);
|
||||
map[i].name = statename;
|
||||
if (pctldev)
|
||||
map[i].ctrl_dev_name = dev_name(pctldev->dev);
|
||||
}
|
||||
|
||||
/* Remember the converted mapping table entries */
|
||||
dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
|
||||
if (!dt_map) {
|
||||
dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
|
||||
dt_free_map(pctldev, map, num_maps);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dt_map->pctldev = pctldev;
|
||||
dt_map->map = map;
|
||||
dt_map->num_maps = num_maps;
|
||||
list_add_tail(&dt_map->node, &p->dt_maps);
|
||||
|
||||
return pinctrl_register_map(map, num_maps, false, true);
|
||||
}
|
||||
|
||||
static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
|
||||
list_for_each_entry(pctldev, &pinctrldev_list, node)
|
||||
if (pctldev->dev->of_node == np)
|
||||
return pctldev;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
|
||||
struct device_node *np_config)
|
||||
{
|
||||
struct device_node *np_pctldev;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_ops *ops;
|
||||
int ret;
|
||||
struct pinctrl_map *map;
|
||||
unsigned num_maps;
|
||||
|
||||
/* Find the pin controller containing np_config */
|
||||
np_pctldev = of_node_get(np_config);
|
||||
for (;;) {
|
||||
np_pctldev = of_get_next_parent(np_pctldev);
|
||||
if (!np_pctldev || of_node_is_root(np_pctldev)) {
|
||||
dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
|
||||
np_config->full_name);
|
||||
of_node_put(np_pctldev);
|
||||
/* OK let's just assume this will appear later then */
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
pctldev = find_pinctrl_by_of_node(np_pctldev);
|
||||
if (pctldev)
|
||||
break;
|
||||
}
|
||||
of_node_put(np_pctldev);
|
||||
|
||||
/*
|
||||
* Call pinctrl driver to parse device tree node, and
|
||||
* generate mapping table entries
|
||||
*/
|
||||
ops = pctldev->desc->pctlops;
|
||||
if (!ops->dt_node_to_map) {
|
||||
dev_err(p->dev, "pctldev %s doesn't support DT\n",
|
||||
dev_name(pctldev->dev));
|
||||
return -ENODEV;
|
||||
}
|
||||
ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Stash the mapping table chunk away for later use */
|
||||
return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
|
||||
}
|
||||
|
||||
static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
|
||||
{
|
||||
struct pinctrl_map *map;
|
||||
|
||||
map = kzalloc(sizeof(*map), GFP_KERNEL);
|
||||
if (!map) {
|
||||
dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
|
||||
map->type = PIN_MAP_TYPE_DUMMY_STATE;
|
||||
|
||||
return dt_remember_or_free_map(p, statename, NULL, map, 1);
|
||||
}
|
||||
|
||||
int pinctrl_dt_to_map(struct pinctrl *p)
|
||||
{
|
||||
struct device_node *np = p->dev->of_node;
|
||||
int state, ret;
|
||||
char *propname;
|
||||
struct property *prop;
|
||||
const char *statename;
|
||||
const __be32 *list;
|
||||
int size, config;
|
||||
phandle phandle;
|
||||
struct device_node *np_config;
|
||||
|
||||
/* CONFIG_OF enabled, p->dev not instantiated from DT */
|
||||
if (!np) {
|
||||
dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We may store pointers to property names within the node */
|
||||
of_node_get(np);
|
||||
|
||||
/* For each defined state ID */
|
||||
for (state = 0; ; state++) {
|
||||
/* Retrieve the pinctrl-* property */
|
||||
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
|
||||
prop = of_find_property(np, propname, &size);
|
||||
kfree(propname);
|
||||
if (!prop)
|
||||
break;
|
||||
list = prop->value;
|
||||
size /= sizeof(*list);
|
||||
|
||||
/* Determine whether pinctrl-names property names the state */
|
||||
ret = of_property_read_string_index(np, "pinctrl-names",
|
||||
state, &statename);
|
||||
/*
|
||||
* If not, statename is just the integer state ID. But rather
|
||||
* than dynamically allocate it and have to free it later,
|
||||
* just point part way into the property name for the string.
|
||||
*/
|
||||
if (ret < 0) {
|
||||
/* strlen("pinctrl-") == 8 */
|
||||
statename = prop->name + 8;
|
||||
}
|
||||
|
||||
/* For every referenced pin configuration node in it */
|
||||
for (config = 0; config < size; config++) {
|
||||
phandle = be32_to_cpup(list++);
|
||||
|
||||
/* Look up the pin configuration node */
|
||||
np_config = of_find_node_by_phandle(phandle);
|
||||
if (!np_config) {
|
||||
dev_err(p->dev,
|
||||
"prop %s index %i invalid phandle\n",
|
||||
prop->name, config);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Parse the node */
|
||||
ret = dt_to_map_one_config(p, statename, np_config);
|
||||
of_node_put(np_config);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* No entries in DT? Generate a dummy state table entry */
|
||||
if (!size) {
|
||||
ret = dt_remember_dummy_state(p, statename);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
pinctrl_dt_free_maps(p);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Internal interface to pinctrl device tree integration
|
||||
*
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
void pinctrl_dt_free_maps(struct pinctrl *p);
|
||||
int pinctrl_dt_to_map(struct pinctrl *p);
|
||||
|
||||
#else
|
||||
|
||||
static inline int pinctrl_dt_to_map(struct pinctrl *p)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void pinctrl_dt_free_maps(struct pinctrl *p)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -379,8 +379,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
|
|||
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
const struct pinconf_ops *confops;
|
||||
int i;
|
||||
|
||||
pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
|
||||
if (pctldev)
|
||||
confops = pctldev->desc->confops;
|
||||
else
|
||||
confops = NULL;
|
||||
|
||||
switch (map->type) {
|
||||
case PIN_MAP_TYPE_CONFIGS_PIN:
|
||||
seq_printf(s, "pin ");
|
||||
|
|
@ -394,8 +402,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
|
|||
|
||||
seq_printf(s, "%s\n", map->data.configs.group_or_pin);
|
||||
|
||||
for (i = 0; i < map->data.configs.num_configs; i++)
|
||||
seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
|
||||
for (i = 0; i < map->data.configs.num_configs; i++) {
|
||||
seq_printf(s, "config ");
|
||||
if (confops && confops->pin_config_config_dbg_show)
|
||||
confops->pin_config_config_dbg_show(pctldev, s,
|
||||
map->data.configs.configs[i]);
|
||||
else
|
||||
seq_printf(s, "%08lx", map->data.configs.configs[i]);
|
||||
seq_printf(s, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
|
|
@ -403,6 +418,7 @@ void pinconf_show_setting(struct seq_file *s,
|
|||
{
|
||||
struct pinctrl_dev *pctldev = setting->pctldev;
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
const struct pinconf_ops *confops = pctldev->desc->confops;
|
||||
struct pin_desc *desc;
|
||||
int i;
|
||||
|
||||
|
|
@ -428,8 +444,15 @@ void pinconf_show_setting(struct seq_file *s,
|
|||
* FIXME: We should really get the pin controler to dump the config
|
||||
* values, so they can be decoded to something meaningful.
|
||||
*/
|
||||
for (i = 0; i < setting->data.configs.num_configs; i++)
|
||||
seq_printf(s, " %08lx", setting->data.configs.configs[i]);
|
||||
for (i = 0; i < setting->data.configs.num_configs; i++) {
|
||||
seq_printf(s, " ");
|
||||
if (confops && confops->pin_config_config_dbg_show)
|
||||
confops->pin_config_config_dbg_show(pctldev, s,
|
||||
setting->data.configs.configs[i]);
|
||||
else
|
||||
seq_printf(s, "%08lx",
|
||||
setting->data.configs.configs[i]);
|
||||
}
|
||||
|
||||
seq_printf(s, "\n");
|
||||
}
|
||||
|
|
@ -448,10 +471,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
|
|||
static int pinconf_pins_show(struct seq_file *s, void *what)
|
||||
{
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinconf_ops *ops = pctldev->desc->confops;
|
||||
unsigned i, pin;
|
||||
|
||||
if (!ops || !ops->pin_config_get)
|
||||
return 0;
|
||||
|
||||
seq_puts(s, "Pin config settings per pin\n");
|
||||
seq_puts(s, "Format: pin (name): pinmux setting array\n");
|
||||
seq_puts(s, "Format: pin (name): configs\n");
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
|
|
@ -495,17 +522,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
|
|||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
const struct pinconf_ops *ops = pctldev->desc->confops;
|
||||
unsigned ngroups = pctlops->get_groups_count(pctldev);
|
||||
unsigned selector = 0;
|
||||
|
||||
if (!ops || !ops->pin_config_group_get)
|
||||
return 0;
|
||||
|
||||
seq_puts(s, "Pin config settings per pin group\n");
|
||||
seq_puts(s, "Format: group (name): pinmux setting array\n");
|
||||
seq_puts(s, "Format: group (name): configs\n");
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
while (pctlops->list_groups(pctldev, selector) >= 0) {
|
||||
while (selector < ngroups) {
|
||||
const char *gname = pctlops->get_group_name(pctldev, selector);
|
||||
|
||||
seq_printf(s, "%u (%s):", selector, gname);
|
||||
|
|
|
|||
|
|
@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
|
|||
struct pinctrl_setting *setting);
|
||||
void pinconf_free_setting(struct pinctrl_setting const *setting);
|
||||
int pinconf_apply_setting(struct pinctrl_setting const *setting);
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinconf_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
/*
|
||||
* You will only be interested in these if you're using PINCONF
|
||||
|
|
@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
|
||||
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinconf_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
#else
|
||||
|
||||
static inline void pinconf_show_map(struct seq_file *s,
|
||||
struct pinctrl_map const *map)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ struct u300_gpio_confdata {
|
|||
|
||||
|
||||
/* Initial configuration */
|
||||
static const struct __initdata u300_gpio_confdata
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
/* Port 0, pins 0-7 */
|
||||
{
|
||||
|
|
@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
|||
}
|
||||
};
|
||||
|
||||
static const struct __initdata u300_gpio_confdata
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
/* Port 0, pins 0-7 */
|
||||
{
|
||||
|
|
|
|||
|
|
@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
|
|||
.pin_base = 0,
|
||||
};
|
||||
|
||||
static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
|
||||
static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
|
||||
{
|
||||
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
if (selector >= info->num_grps)
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
|
||||
return info->num_grps;
|
||||
}
|
||||
|
||||
static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
|
||||
unsigned selector)
|
||||
{
|
||||
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
if (selector >= info->num_grps)
|
||||
return NULL;
|
||||
|
||||
return info->grps[selector].name;
|
||||
}
|
||||
|
||||
|
|
@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
|
|||
unsigned *num_pins)
|
||||
{
|
||||
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
if (selector >= info->num_grps)
|
||||
return -EINVAL;
|
||||
|
||||
*pins = info->grps[selector].pins;
|
||||
*num_pins = info->grps[selector].npins;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pinctrl_ops pxa3xx_pctrl_ops = {
|
||||
.list_groups = pxa3xx_list_groups,
|
||||
.get_groups_count = pxa3xx_get_groups_count,
|
||||
.get_group_name = pxa3xx_get_group_name,
|
||||
.get_group_pins = pxa3xx_get_group_pins,
|
||||
};
|
||||
|
||||
static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
|
||||
static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
|
||||
{
|
||||
struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
||||
if (func >= info->num_funcs)
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
|
||||
return info->num_funcs;
|
||||
}
|
||||
|
||||
static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
|
||||
|
|
@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
|
|||
}
|
||||
|
||||
static struct pinmux_ops pxa3xx_pmx_ops = {
|
||||
.list_functions = pxa3xx_pmx_list_func,
|
||||
.get_functions_count = pxa3xx_pmx_get_funcs_count,
|
||||
.get_function_name = pxa3xx_pmx_get_func_name,
|
||||
.get_function_groups = pxa3xx_pmx_get_groups,
|
||||
.enable = pxa3xx_pmx_enable,
|
||||
|
|
|
|||
|
|
@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
|
|||
SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
|
||||
};
|
||||
|
||||
static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(sirfsoc_pin_groups);
|
||||
}
|
||||
|
||||
static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
|
||||
return NULL;
|
||||
return sirfsoc_pin_groups[selector].name;
|
||||
}
|
||||
|
||||
|
|
@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
|
|||
const unsigned **pins,
|
||||
unsigned *num_pins)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
|
||||
return -EINVAL;
|
||||
*pins = sirfsoc_pin_groups[selector].pins;
|
||||
*num_pins = sirfsoc_pin_groups[selector].num_pins;
|
||||
return 0;
|
||||
|
|
@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
|
|||
}
|
||||
|
||||
static struct pinctrl_ops sirfsoc_pctrl_ops = {
|
||||
.list_groups = sirfsoc_list_groups,
|
||||
.get_groups_count = sirfsoc_get_groups_count,
|
||||
.get_group_name = sirfsoc_get_group_name,
|
||||
.get_group_pins = sirfsoc_get_group_pins,
|
||||
.pin_dbg_show = sirfsoc_pin_dbg_show,
|
||||
|
|
@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
|
|||
sirfsoc_pinmux_endisable(spmx, selector, false);
|
||||
}
|
||||
|
||||
static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
|
||||
static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(sirfsoc_pmx_functions);
|
||||
}
|
||||
|
||||
static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
|
|||
}
|
||||
|
||||
static struct pinmux_ops sirfsoc_pinmux_ops = {
|
||||
.list_functions = sirfsoc_pinmux_list_funcs,
|
||||
.enable = sirfsoc_pinmux_enable,
|
||||
.disable = sirfsoc_pinmux_disable,
|
||||
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
|
||||
.get_function_name = sirfsoc_pinmux_get_func_name,
|
||||
.get_function_groups = sirfsoc_pinmux_get_groups,
|
||||
.gpio_request_enable = sirfsoc_pinmux_request_gpio,
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Driver for the NVIDIA Tegra pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Derived from code:
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
|
|
@ -22,17 +22,19 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <mach/pinconf-tegra.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "pinctrl-tegra.h"
|
||||
|
||||
#define DRIVER_NAME "tegra-pinmux-disabled"
|
||||
|
||||
struct tegra_pmx {
|
||||
struct device *dev;
|
||||
struct pinctrl_dev *pctl;
|
||||
|
|
@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
|
|||
writel(val, pmx->regs[bank] + reg);
|
||||
}
|
||||
|
||||
static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned group)
|
||||
static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
return pmx->soc->ngroups;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return NULL;
|
||||
|
||||
return pmx->soc->groups[group].name;
|
||||
}
|
||||
|
||||
|
|
@ -82,38 +77,259 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return -EINVAL;
|
||||
|
||||
*pins = pmx->soc->groups[group].pins;
|
||||
*num_pins = pmx->soc->groups[group].npins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, " " DRIVER_NAME);
|
||||
seq_printf(s, " %s", dev_name(pctldev->dev));
|
||||
}
|
||||
#endif
|
||||
|
||||
static int reserve_map(struct device *dev, struct pinctrl_map **map,
|
||||
unsigned *reserved_maps, unsigned *num_maps,
|
||||
unsigned reserve)
|
||||
{
|
||||
unsigned old_num = *reserved_maps;
|
||||
unsigned new_num = *num_maps + reserve;
|
||||
struct pinctrl_map *new_map;
|
||||
|
||||
if (old_num >= new_num)
|
||||
return 0;
|
||||
|
||||
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
|
||||
if (!new_map) {
|
||||
dev_err(dev, "krealloc(map) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
|
||||
|
||||
*map = new_map;
|
||||
*reserved_maps = new_num;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
|
||||
unsigned *num_maps, const char *group,
|
||||
const char *function)
|
||||
{
|
||||
if (WARN_ON(*num_maps == *reserved_maps))
|
||||
return -ENOSPC;
|
||||
|
||||
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
(*map)[*num_maps].data.mux.group = group;
|
||||
(*map)[*num_maps].data.mux.function = function;
|
||||
(*num_maps)++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int add_map_configs(struct device *dev, struct pinctrl_map **map,
|
||||
unsigned *reserved_maps, unsigned *num_maps,
|
||||
const char *group, unsigned long *configs,
|
||||
unsigned num_configs)
|
||||
{
|
||||
unsigned long *dup_configs;
|
||||
|
||||
if (WARN_ON(*num_maps == *reserved_maps))
|
||||
return -ENOSPC;
|
||||
|
||||
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
|
||||
GFP_KERNEL);
|
||||
if (!dup_configs) {
|
||||
dev_err(dev, "kmemdup(configs) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
||||
(*map)[*num_maps].data.configs.group_or_pin = group;
|
||||
(*map)[*num_maps].data.configs.configs = dup_configs;
|
||||
(*map)[*num_maps].data.configs.num_configs = num_configs;
|
||||
(*num_maps)++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int add_config(struct device *dev, unsigned long **configs,
|
||||
unsigned *num_configs, unsigned long config)
|
||||
{
|
||||
unsigned old_num = *num_configs;
|
||||
unsigned new_num = old_num + 1;
|
||||
unsigned long *new_configs;
|
||||
|
||||
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
|
||||
GFP_KERNEL);
|
||||
if (!new_configs) {
|
||||
dev_err(dev, "krealloc(configs) failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
new_configs[old_num] = config;
|
||||
|
||||
*configs = new_configs;
|
||||
*num_configs = new_num;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_maps; i++)
|
||||
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
|
||||
kfree(map[i].data.configs.configs);
|
||||
|
||||
kfree(map);
|
||||
}
|
||||
|
||||
static const struct cfg_param {
|
||||
const char *property;
|
||||
enum tegra_pinconf_param param;
|
||||
} cfg_params[] = {
|
||||
{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
|
||||
{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
|
||||
{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
|
||||
{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
|
||||
{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
|
||||
{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
|
||||
{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
|
||||
{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
|
||||
{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
|
||||
{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
|
||||
{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
|
||||
{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
|
||||
{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
|
||||
};
|
||||
|
||||
int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
|
||||
struct device_node *np,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *reserved_maps,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
int ret, i;
|
||||
const char *function;
|
||||
u32 val;
|
||||
unsigned long config;
|
||||
unsigned long *configs = NULL;
|
||||
unsigned num_configs = 0;
|
||||
unsigned reserve;
|
||||
struct property *prop;
|
||||
const char *group;
|
||||
|
||||
ret = of_property_read_string(np, "nvidia,function", &function);
|
||||
if (ret < 0) {
|
||||
/* EINVAL=missing, which is fine since it's optional */
|
||||
if (ret != -EINVAL)
|
||||
dev_err(dev,
|
||||
"could not parse property nvidia,function\n");
|
||||
function = NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
ret = of_property_read_u32(np, cfg_params[i].property, &val);
|
||||
if (!ret) {
|
||||
config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
|
||||
ret = add_config(dev, &configs, &num_configs, config);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
/* EINVAL=missing, which is fine since it's optional */
|
||||
} else if (ret != -EINVAL) {
|
||||
dev_err(dev, "could not parse property %s\n",
|
||||
cfg_params[i].property);
|
||||
}
|
||||
}
|
||||
|
||||
reserve = 0;
|
||||
if (function != NULL)
|
||||
reserve++;
|
||||
if (num_configs)
|
||||
reserve++;
|
||||
ret = of_property_count_strings(np, "nvidia,pins");
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "could not parse property nvidia,pins\n");
|
||||
goto exit;
|
||||
}
|
||||
reserve *= ret;
|
||||
|
||||
ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
|
||||
of_property_for_each_string(np, "nvidia,pins", prop, group) {
|
||||
if (function) {
|
||||
ret = add_map_mux(map, reserved_maps, num_maps,
|
||||
group, function);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (num_configs) {
|
||||
ret = add_map_configs(dev, map, reserved_maps,
|
||||
num_maps, group, configs,
|
||||
num_configs);
|
||||
if (ret < 0)
|
||||
goto exit;
|
||||
}
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
exit:
|
||||
kfree(configs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np_config,
|
||||
struct pinctrl_map **map, unsigned *num_maps)
|
||||
{
|
||||
unsigned reserved_maps;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
reserved_maps = 0;
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
for_each_child_of_node(np_config, np) {
|
||||
ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
|
||||
&reserved_maps, num_maps);
|
||||
if (ret < 0) {
|
||||
tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pinctrl_ops tegra_pinctrl_ops = {
|
||||
.list_groups = tegra_pinctrl_list_groups,
|
||||
.get_groups_count = tegra_pinctrl_get_groups_count,
|
||||
.get_group_name = tegra_pinctrl_get_group_name,
|
||||
.get_group_pins = tegra_pinctrl_get_group_pins,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
|
||||
#endif
|
||||
.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
|
||||
.dt_free_map = tegra_pinctrl_dt_free_map,
|
||||
};
|
||||
|
||||
static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
|
||||
unsigned function)
|
||||
static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (function >= pmx->soc->nfunctions)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
return pmx->soc->nfunctions;
|
||||
}
|
||||
|
||||
static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -121,9 +337,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (function >= pmx->soc->nfunctions)
|
||||
return NULL;
|
||||
|
||||
return pmx->soc->functions[function].name;
|
||||
}
|
||||
|
||||
|
|
@ -134,9 +347,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
if (function >= pmx->soc->nfunctions)
|
||||
return -EINVAL;
|
||||
|
||||
*groups = pmx->soc->functions[function].groups;
|
||||
*num_groups = pmx->soc->functions[function].ngroups;
|
||||
|
||||
|
|
@ -151,18 +361,16 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
|
|||
int i;
|
||||
u32 val;
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return -EINVAL;
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
if (g->mux_reg < 0)
|
||||
if (WARN_ON(g->mux_reg < 0))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
|
||||
if (g->funcs[i] == function)
|
||||
break;
|
||||
}
|
||||
if (i == ARRAY_SIZE(g->funcs))
|
||||
if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
|
||||
return -EINVAL;
|
||||
|
||||
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
||||
|
|
@ -180,11 +388,9 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
|
|||
const struct tegra_pingroup *g;
|
||||
u32 val;
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return;
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
if (g->mux_reg < 0)
|
||||
if (WARN_ON(g->mux_reg < 0))
|
||||
return;
|
||||
|
||||
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
|
||||
|
|
@ -194,7 +400,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
|
||||
static struct pinmux_ops tegra_pinmux_ops = {
|
||||
.list_functions = tegra_pinctrl_list_funcs,
|
||||
.get_functions_count = tegra_pinctrl_get_funcs_count,
|
||||
.get_function_name = tegra_pinctrl_get_func_name,
|
||||
.get_function_groups = tegra_pinctrl_get_func_groups,
|
||||
.enable = tegra_pinctrl_enable,
|
||||
|
|
@ -204,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
|
|||
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
||||
const struct tegra_pingroup *g,
|
||||
enum tegra_pinconf_param param,
|
||||
bool report_err,
|
||||
s8 *bank, s16 *reg, s8 *bit, s8 *width)
|
||||
{
|
||||
switch (param) {
|
||||
|
|
@ -291,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
|||
}
|
||||
|
||||
if (*reg < 0) {
|
||||
dev_err(pmx->dev,
|
||||
"Config param %04x not supported on group %s\n",
|
||||
param, g->name);
|
||||
if (report_err)
|
||||
dev_err(pmx->dev,
|
||||
"Config param %04x not supported on group %s\n",
|
||||
param, g->name);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
|
@ -303,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
|||
static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long *config)
|
||||
{
|
||||
dev_err(pctldev->dev, "pin_config_get op not supported\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
|
||||
unsigned pin, unsigned long config)
|
||||
{
|
||||
dev_err(pctldev->dev, "pin_config_set op not supported\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
|
|
@ -324,11 +534,10 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|||
s16 reg;
|
||||
u32 val, mask;
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return -EINVAL;
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
||||
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
||||
&width);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -353,11 +562,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
s16 reg;
|
||||
u32 val, mask;
|
||||
|
||||
if (group >= pmx->soc->ngroups)
|
||||
return -EINVAL;
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
|
||||
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
|
||||
&width);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -365,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
|
||||
/* LOCK can't be cleared */
|
||||
if (param == TEGRA_PINCONF_PARAM_LOCK) {
|
||||
if ((val & BIT(bit)) && !arg)
|
||||
if ((val & BIT(bit)) && !arg) {
|
||||
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Special-case Boolean values; allow any non-zero as true */
|
||||
|
|
@ -375,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
|
||||
/* Range-check user-supplied value */
|
||||
mask = (1 << width) - 1;
|
||||
if (arg & ~mask)
|
||||
if (arg & ~mask) {
|
||||
dev_err(pctldev->dev,
|
||||
"config %lx: %x too big for %d bit register\n",
|
||||
config, arg, width);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Update register */
|
||||
val &= ~(mask << bit);
|
||||
|
|
@ -386,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned offset)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned selector)
|
||||
static const char *strip_prefix(const char *s)
|
||||
{
|
||||
const char *comma = strchr(s, ',');
|
||||
if (!comma)
|
||||
return s;
|
||||
|
||||
return comma + 1;
|
||||
}
|
||||
|
||||
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned group)
|
||||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct tegra_pingroup *g;
|
||||
int i, ret;
|
||||
s8 bank, bit, width;
|
||||
s16 reg;
|
||||
u32 val;
|
||||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
|
||||
&bank, ®, &bit, &width);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
||||
val = pmx_readl(pmx, bank, reg);
|
||||
val >>= bit;
|
||||
val &= (1 << width) - 1;
|
||||
|
||||
seq_printf(s, "\n\t%s=%u",
|
||||
strip_prefix(cfg_params[i].property), val);
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned long config)
|
||||
{
|
||||
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
|
||||
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
|
||||
const char *pname = "unknown";
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
|
||||
if (cfg_params[i].param == param) {
|
||||
pname = cfg_params[i].property;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
seq_printf(s, "%s=%d", strip_prefix(pname), arg);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct pinconf_ops tegra_pinconf_ops = {
|
||||
.pin_config_get = tegra_pinconf_get,
|
||||
.pin_config_set = tegra_pinconf_set,
|
||||
.pin_config_group_get = tegra_pinconf_group_get,
|
||||
.pin_config_group_set = tegra_pinconf_group_set,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.pin_config_dbg_show = tegra_pinconf_dbg_show,
|
||||
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
|
||||
.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
||||
|
|
@ -412,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
|
|||
};
|
||||
|
||||
static struct pinctrl_desc tegra_pinctrl_desc = {
|
||||
.name = DRIVER_NAME,
|
||||
.pctlops = &tegra_pinctrl_ops,
|
||||
.pmxops = &tegra_pinmux_ops,
|
||||
.confops = &tegra_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
|
||||
#ifdef CONFIG_PINCTRL_TEGRA20
|
||||
{
|
||||
.compatible = "nvidia,tegra20-pinmux-disabled",
|
||||
.data = tegra20_pinctrl_init,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_TEGRA30
|
||||
{
|
||||
.compatible = "nvidia,tegra30-pinmux-disabled",
|
||||
.data = tegra30_pinctrl_init,
|
||||
},
|
||||
#endif
|
||||
{},
|
||||
};
|
||||
|
||||
static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
|
||||
int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct tegra_pinctrl_soc_data *soc_data)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
tegra_pinctrl_soc_initf initf = NULL;
|
||||
struct tegra_pmx *pmx;
|
||||
struct resource *res;
|
||||
int i;
|
||||
|
||||
match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
|
||||
if (match)
|
||||
initf = (tegra_pinctrl_soc_initf)match->data;
|
||||
#ifdef CONFIG_PINCTRL_TEGRA20
|
||||
if (!initf)
|
||||
initf = tegra20_pinctrl_init;
|
||||
#endif
|
||||
if (!initf) {
|
||||
dev_err(&pdev->dev,
|
||||
"Could not determine SoC-specific init func\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
|
||||
if (!pmx) {
|
||||
dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
pmx->dev = &pdev->dev;
|
||||
|
||||
(*initf)(&pmx->soc);
|
||||
pmx->soc = soc_data;
|
||||
|
||||
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
|
||||
tegra_pinctrl_desc.name = dev_name(&pdev->dev);
|
||||
tegra_pinctrl_desc.pins = pmx->soc->pins;
|
||||
tegra_pinctrl_desc.npins = pmx->soc->npins;
|
||||
|
||||
|
|
@ -520,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
|
||||
|
||||
static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
||||
int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
|
||||
|
||||
|
|
@ -530,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra_pinctrl_init);
|
||||
|
||||
static void __exit tegra_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
|
||||
EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
|
||||
|
|
|
|||
|
|
@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
|
|||
unsigned ngroups;
|
||||
};
|
||||
|
||||
/**
|
||||
* tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC.
|
||||
* @soc_data: This pointer must be updated to point at a struct containing
|
||||
* details of the SoC.
|
||||
*/
|
||||
typedef void (*tegra_pinctrl_soc_initf)(
|
||||
const struct tegra_pinctrl_soc_data **soc_data);
|
||||
|
||||
/**
|
||||
* tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
|
||||
* @soc_data: This pointer will be updated to point at a struct containing
|
||||
* details of Tegra20's pin controller.
|
||||
*/
|
||||
void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
|
||||
/**
|
||||
* tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
|
||||
* @soc_data: This pointer will be updated to point at a struct containing
|
||||
* details of Tegra30's pin controller.
|
||||
*/
|
||||
void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
|
||||
int tegra_pinctrl_probe(struct platform_device *pdev,
|
||||
const struct tegra_pinctrl_soc_data *soc_data);
|
||||
int tegra_pinctrl_remove(struct platform_device *pdev);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Pinctrl data for the NVIDIA Tegra20 pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Derived from code:
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
|
|
@ -17,6 +17,8 @@
|
|||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
|
|||
.ngroups = ARRAY_SIZE(tegra20_groups),
|
||||
};
|
||||
|
||||
void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
|
||||
static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
*soc = &tegra20_pinctrl;
|
||||
return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
|
||||
}
|
||||
|
||||
static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "nvidia,tegra20-pinmux", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver tegra20_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "tegra20-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra20_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra20_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra20_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra20_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra20_pinctrl_init);
|
||||
|
||||
static void __exit tegra20_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra20_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra20_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Pinctrl data for the NVIDIA Tegra30 pinmux
|
||||
*
|
||||
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -13,6 +13,8 @@
|
|||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
|
|||
.ngroups = ARRAY_SIZE(tegra30_groups),
|
||||
};
|
||||
|
||||
void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
|
||||
static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
*soc = &tegra30_pinctrl;
|
||||
return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
|
||||
}
|
||||
|
||||
static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "nvidia,tegra30-pinmux", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver tegra30_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "tegra30-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra30_pinctrl_of_match,
|
||||
},
|
||||
.probe = tegra30_pinctrl_probe,
|
||||
.remove = __devexit_p(tegra_pinctrl_remove),
|
||||
};
|
||||
|
||||
static int __init tegra30_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra30_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(tegra30_pinctrl_init);
|
||||
|
||||
static void __exit tegra30_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra30_pinctrl_driver);
|
||||
}
|
||||
module_exit(tegra30_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
|
||||
|
|
|
|||
|
|
@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int u300_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(u300_pin_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(u300_pin_groups);
|
||||
}
|
||||
|
||||
static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned selector)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(u300_pin_groups))
|
||||
return NULL;
|
||||
return u300_pin_groups[selector].name;
|
||||
}
|
||||
|
||||
|
|
@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
const unsigned **pins,
|
||||
unsigned *num_pins)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(u300_pin_groups))
|
||||
return -EINVAL;
|
||||
*pins = u300_pin_groups[selector].pins;
|
||||
*num_pins = u300_pin_groups[selector].num_pins;
|
||||
return 0;
|
||||
|
|
@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
|||
}
|
||||
|
||||
static struct pinctrl_ops u300_pctrl_ops = {
|
||||
.list_groups = u300_list_groups,
|
||||
.get_groups_count = u300_get_groups_count,
|
||||
.get_group_name = u300_get_group_name,
|
||||
.get_group_pins = u300_get_group_pins,
|
||||
.pin_dbg_show = u300_pin_dbg_show,
|
||||
|
|
@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
u300_pmx_endisable(upmx, selector, false);
|
||||
}
|
||||
|
||||
static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(u300_pmx_functions))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(u300_pmx_functions);
|
||||
}
|
||||
|
||||
static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
}
|
||||
|
||||
static struct pinmux_ops u300_pmx_ops = {
|
||||
.list_functions = u300_pmx_list_funcs,
|
||||
.get_functions_count = u300_pmx_get_funcs_count,
|
||||
.get_function_name = u300_pmx_get_func_name,
|
||||
.get_function_groups = u300_pmx_get_groups,
|
||||
.enable = u300_pmx_enable,
|
||||
|
|
|
|||
|
|
@ -33,10 +33,12 @@
|
|||
int pinmux_check_ops(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
const struct pinmux_ops *ops = pctldev->desc->pmxops;
|
||||
unsigned nfuncs;
|
||||
unsigned selector = 0;
|
||||
|
||||
/* Check that we implement required operations */
|
||||
if (!ops->list_functions ||
|
||||
if (!ops ||
|
||||
!ops->get_functions_count ||
|
||||
!ops->get_function_name ||
|
||||
!ops->get_function_groups ||
|
||||
!ops->enable ||
|
||||
|
|
@ -44,11 +46,12 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
|
|||
return -EINVAL;
|
||||
|
||||
/* Check that all functions registered have names */
|
||||
while (ops->list_functions(pctldev, selector) >= 0) {
|
||||
nfuncs = ops->get_functions_count(pctldev);
|
||||
while (selector < nfuncs) {
|
||||
const char *fname = ops->get_function_name(pctldev,
|
||||
selector);
|
||||
if (!fname) {
|
||||
pr_err("pinmux ops has no name for function%u\n",
|
||||
dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
|
||||
selector);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -85,8 +88,6 @@ static int pin_request(struct pinctrl_dev *pctldev,
|
|||
const struct pinmux_ops *ops = pctldev->desc->pmxops;
|
||||
int status = -EINVAL;
|
||||
|
||||
dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
|
||||
|
||||
desc = pin_desc_get(pctldev, pin);
|
||||
if (desc == NULL) {
|
||||
dev_err(pctldev->dev,
|
||||
|
|
@ -94,6 +95,9 @@ static int pin_request(struct pinctrl_dev *pctldev,
|
|||
goto out;
|
||||
}
|
||||
|
||||
dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
|
||||
pin, desc->name, owner);
|
||||
|
||||
if (gpio_range) {
|
||||
/* There's no need to support multiple GPIO requests */
|
||||
if (desc->gpio_owner) {
|
||||
|
|
@ -287,10 +291,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
|
|||
const char *function)
|
||||
{
|
||||
const struct pinmux_ops *ops = pctldev->desc->pmxops;
|
||||
unsigned nfuncs = ops->get_functions_count(pctldev);
|
||||
unsigned selector = 0;
|
||||
|
||||
/* See if this pctldev has this function */
|
||||
while (ops->list_functions(pctldev, selector) >= 0) {
|
||||
while (selector < nfuncs) {
|
||||
const char *fname = ops->get_function_name(pctldev,
|
||||
selector);
|
||||
|
||||
|
|
@ -319,6 +324,11 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
|
|||
const unsigned *pins;
|
||||
unsigned num_pins;
|
||||
|
||||
if (!pmxops) {
|
||||
dev_err(pctldev->dev, "does not support mux function\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
setting->data.mux.func =
|
||||
pinmux_func_name_to_selector(pctldev, map->data.mux.function);
|
||||
if (setting->data.mux.func < 0)
|
||||
|
|
@ -477,11 +487,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
|
|||
{
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
|
||||
unsigned nfuncs;
|
||||
unsigned func_selector = 0;
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
if (!pmxops)
|
||||
return 0;
|
||||
|
||||
while (pmxops->list_functions(pctldev, func_selector) >= 0) {
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
nfuncs = pmxops->get_functions_count(pctldev);
|
||||
while (func_selector < nfuncs) {
|
||||
const char *func = pmxops->get_function_name(pctldev,
|
||||
func_selector);
|
||||
const char * const *groups;
|
||||
|
|
@ -515,6 +529,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
|
|||
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
|
||||
unsigned i, pin;
|
||||
|
||||
if (!pmxops)
|
||||
return 0;
|
||||
|
||||
seq_puts(s, "Pinmux settings per pin\n");
|
||||
seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
|
|||
int pinmux_enable_setting(struct pinctrl_setting const *setting);
|
||||
void pinmux_disable_setting(struct pinctrl_setting const *setting);
|
||||
|
||||
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinmux_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinmux_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
#else
|
||||
|
||||
static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
|
||||
|
|
@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
|
|||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
|
||||
|
||||
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinmux_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinmux_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
#else
|
||||
|
||||
static inline void pinmux_show_map(struct seq_file *s,
|
||||
struct pinctrl_map const *map)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -436,15 +436,16 @@ static const struct hc_driver tegra_ehci_hc_driver = {
|
|||
.port_handed_over = ehci_port_handed_over,
|
||||
};
|
||||
|
||||
static int setup_vbus_gpio(struct platform_device *pdev)
|
||||
static int setup_vbus_gpio(struct platform_device *pdev,
|
||||
struct tegra_ehci_platform_data *pdata)
|
||||
{
|
||||
int err = 0;
|
||||
int gpio;
|
||||
|
||||
if (!pdev->dev.of_node)
|
||||
return 0;
|
||||
|
||||
gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
|
||||
gpio = pdata->vbus_gpio;
|
||||
if (!gpio_is_valid(gpio))
|
||||
gpio = of_get_named_gpio(pdev->dev.of_node,
|
||||
"nvidia,vbus-gpio", 0);
|
||||
if (!gpio_is_valid(gpio))
|
||||
return 0;
|
||||
|
||||
|
|
@ -664,7 +665,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
|
|||
if (!pdev->dev.dma_mask)
|
||||
pdev->dev.dma_mask = &tegra_ehci_dma_mask;
|
||||
|
||||
setup_vbus_gpio(pdev);
|
||||
setup_vbus_gpio(pdev, pdata);
|
||||
|
||||
tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
|
||||
if (!tegra)
|
||||
|
|
|
|||
|
|
@ -259,6 +259,37 @@ extern void of_detach_node(struct device_node *);
|
|||
#endif
|
||||
|
||||
#define of_match_ptr(_ptr) (_ptr)
|
||||
|
||||
/*
|
||||
* struct property *prop;
|
||||
* const __be32 *p;
|
||||
* u32 u;
|
||||
*
|
||||
* of_property_for_each_u32(np, "propname", prop, p, u)
|
||||
* printk("U32 value: %x\n", u);
|
||||
*/
|
||||
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
|
||||
u32 *pu);
|
||||
#define of_property_for_each_u32(np, propname, prop, p, u) \
|
||||
for (prop = of_find_property(np, propname, NULL), \
|
||||
p = of_prop_next_u32(prop, NULL, &u); \
|
||||
p; \
|
||||
p = of_prop_next_u32(prop, p, &u))
|
||||
|
||||
/*
|
||||
* struct property *prop;
|
||||
* const char *s;
|
||||
*
|
||||
* of_property_for_each_string(np, "propname", prop, s)
|
||||
* printk("String value: %s\n", s);
|
||||
*/
|
||||
const char *of_prop_next_string(struct property *prop, const char *cur);
|
||||
#define of_property_for_each_string(np, propname, prop, s) \
|
||||
for (prop = of_find_property(np, propname, NULL), \
|
||||
s = of_prop_next_string(prop, NULL); \
|
||||
s; \
|
||||
s = of_prop_next_string(prop, s))
|
||||
|
||||
#else /* CONFIG_OF */
|
||||
|
||||
static inline bool of_have_populated_dt(void)
|
||||
|
|
@ -349,6 +380,10 @@ static inline int of_machine_is_compatible(const char *compat)
|
|||
|
||||
#define of_match_ptr(_ptr) NULL
|
||||
#define of_match_node(_matches, _node) NULL
|
||||
#define of_property_for_each_u32(np, propname, prop, p, u) \
|
||||
while (0)
|
||||
#define of_property_for_each_string(np, propname, prop, s) \
|
||||
while (0)
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -36,6 +36,9 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
|
|||
const char *name);
|
||||
extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
|
||||
|
||||
extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
|
||||
extern void devm_pinctrl_put(struct pinctrl *p);
|
||||
|
||||
#else /* !CONFIG_PINCTRL */
|
||||
|
||||
static inline int pinctrl_request_gpio(unsigned gpio)
|
||||
|
|
@ -79,6 +82,15 @@ static inline int pinctrl_select_state(struct pinctrl *p,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void devm_pinctrl_put(struct pinctrl *p)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PINCTRL */
|
||||
|
||||
static inline struct pinctrl * __must_check pinctrl_get_select(
|
||||
|
|
@ -113,6 +125,38 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default(
|
|||
return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
|
||||
}
|
||||
|
||||
static inline struct pinctrl * __must_check devm_pinctrl_get_select(
|
||||
struct device *dev, const char *name)
|
||||
{
|
||||
struct pinctrl *p;
|
||||
struct pinctrl_state *s;
|
||||
int ret;
|
||||
|
||||
p = devm_pinctrl_get(dev);
|
||||
if (IS_ERR(p))
|
||||
return p;
|
||||
|
||||
s = pinctrl_lookup_state(p, name);
|
||||
if (IS_ERR(s)) {
|
||||
devm_pinctrl_put(p);
|
||||
return ERR_PTR(PTR_ERR(s));
|
||||
}
|
||||
|
||||
ret = pinctrl_select_state(p, s);
|
||||
if (ret < 0) {
|
||||
devm_pinctrl_put(p);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
|
||||
struct device *dev)
|
||||
{
|
||||
return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PINCONF
|
||||
|
||||
extern int pin_config_get(const char *dev_name, const char *name,
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ struct seq_file;
|
|||
* per-device info for a certain pin in debugfs
|
||||
* @pin_config_group_dbg_show: optional debugfs display hook that will provide
|
||||
* per-device info for a certain group in debugfs
|
||||
* @pin_config_config_dbg_show: optional debugfs display hook that will decode
|
||||
* and display a driver's pin configuration parameter
|
||||
*/
|
||||
struct pinconf_ops {
|
||||
#ifdef CONFIG_GENERIC_PINCONF
|
||||
|
|
@ -56,6 +58,9 @@ struct pinconf_ops {
|
|||
void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned selector);
|
||||
void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned long config);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
|
||||
struct device;
|
||||
struct pinctrl_dev;
|
||||
struct pinctrl_map;
|
||||
struct pinmux_ops;
|
||||
struct pinconf_ops;
|
||||
struct gpio_chip;
|
||||
struct device_node;
|
||||
|
||||
/**
|
||||
* struct pinctrl_pin_desc - boards/machines provide information on their
|
||||
|
|
@ -64,9 +66,7 @@ struct pinctrl_gpio_range {
|
|||
/**
|
||||
* struct pinctrl_ops - global pin control operations, to be implemented by
|
||||
* pin controller drivers.
|
||||
* @list_groups: list the number of selectable named groups available
|
||||
* in this pinmux driver, the core will begin on 0 and call this
|
||||
* repeatedly as long as it returns >= 0 to enumerate the groups
|
||||
* @get_groups_count: Returns the count of total number of groups registered.
|
||||
* @get_group_name: return the group name of the pin group
|
||||
* @get_group_pins: return an array of pins corresponding to a certain
|
||||
* group selector @pins, and the size of the array in @num_pins
|
||||
|
|
@ -74,7 +74,7 @@ struct pinctrl_gpio_range {
|
|||
* info for a certain pin in debugfs
|
||||
*/
|
||||
struct pinctrl_ops {
|
||||
int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
|
||||
int (*get_groups_count) (struct pinctrl_dev *pctldev);
|
||||
const char *(*get_group_name) (struct pinctrl_dev *pctldev,
|
||||
unsigned selector);
|
||||
int (*get_group_pins) (struct pinctrl_dev *pctldev,
|
||||
|
|
@ -83,6 +83,11 @@ struct pinctrl_ops {
|
|||
unsigned *num_pins);
|
||||
void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
|
||||
unsigned offset);
|
||||
int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
|
||||
struct device_node *np_config,
|
||||
struct pinctrl_map **map, unsigned *num_maps);
|
||||
void (*dt_free_map) (struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps);
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,9 +29,8 @@ struct pinctrl_dev;
|
|||
* is allowed to answer "no" by returning a negative error code
|
||||
* @free: the reverse function of the request() callback, frees a pin after
|
||||
* being requested
|
||||
* @list_functions: list the number of selectable named functions available
|
||||
* in this pinmux driver, the core will begin on 0 and call this
|
||||
* repeatedly as long as it returns >= 0 to enumerate mux settings
|
||||
* @get_functions_count: returns number of selectable named functions available
|
||||
* in this pinmux driver
|
||||
* @get_function_name: return the function name of the muxing selector,
|
||||
* called by the core to figure out which mux setting it shall map a
|
||||
* certain device to
|
||||
|
|
@ -62,7 +61,7 @@ struct pinctrl_dev;
|
|||
struct pinmux_ops {
|
||||
int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
|
||||
int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
|
||||
int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
|
||||
int (*get_functions_count) (struct pinctrl_dev *pctldev);
|
||||
const char *(*get_function_name) (struct pinctrl_dev *pctldev,
|
||||
unsigned selector);
|
||||
int (*get_function_groups) (struct pinctrl_dev *pctldev,
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
|
|||
/* power down the phy on bus suspend */
|
||||
int power_down_on_bus_suspend;
|
||||
void *phy_config;
|
||||
int vbus_gpio;
|
||||
};
|
||||
|
||||
#endif /* _TEGRA_USB_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue