microblaze/pci: Move the remains of pci_32.c to pci-common.c
There's no point in keeping this separate. Even if microblaze grows a 64-bit variant, it will probably be able to re-use that code as-is Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
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@ -2,5 +2,5 @@
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# Makefile
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#
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obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o
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obj-$(CONFIG_PCI) += pci-common.o indirect_pci.o iomap.o
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obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
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@ -50,6 +50,11 @@ unsigned int pci_flags;
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static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
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unsigned long isa_io_base;
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unsigned long pci_dram_offset;
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static int pci_bus_count;
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void set_pci_dma_ops(struct dma_map_ops *dma_ops)
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{
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pci_dma_ops = dma_ops;
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@ -1558,6 +1563,112 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
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(unsigned long)hose->io_base_virt - _IO_BASE);
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}
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return of_node_get(hose->dn);
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}
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static void __devinit pcibios_scan_phb(struct pci_controller *hose)
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{
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struct pci_bus *bus;
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struct device_node *node = hose->dn;
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unsigned long io_offset;
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struct resource *res = &hose->io_resource;
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pr_debug("PCI: Scanning PHB %s\n",
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node ? node->full_name : "<NO NAME>");
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/* Create an empty bus for the toplevel */
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bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
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if (bus == NULL) {
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printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
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hose->global_number);
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return;
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}
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bus->secondary = hose->first_busno;
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hose->bus = bus;
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/* Fixup IO space offset */
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io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
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res->start = (res->start + io_offset) & 0xffffffffu;
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res->end = (res->end + io_offset) & 0xffffffffu;
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/* Wire up PHB bus resources */
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pcibios_setup_phb_resources(hose);
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/* Scan children */
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hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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int next_busno = 0;
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printk(KERN_INFO "PCI: Probing PCI hardware\n");
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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hose->last_busno = 0xff;
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pcibios_scan_phb(hose);
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printk(KERN_INFO "calling pci_bus_add_devices()\n");
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pci_bus_add_devices(hose->bus);
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if (next_busno <= hose->last_busno)
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next_busno = hose->last_busno + 1;
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}
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pci_bus_count = next_busno;
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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return 0;
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}
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subsys_initcall(pcibios_init);
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static struct pci_controller *pci_bus_to_hose(int bus)
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{
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struct pci_controller *hose, *tmp;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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return NULL;
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}
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/* Provide information on locations of various I/O regions in physical
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* memory. Do this on a per-card basis so that we choose the right
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* root bridge.
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* Note that the returned IO or memory base is a physical address
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*/
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long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
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{
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struct pci_controller *hose;
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long result = -EOPNOTSUPP;
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hose = pci_bus_to_hose(bus);
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if (!hose)
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return -ENODEV;
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switch (which) {
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case IOBASE_BRIDGE_NUMBER:
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return (long)hose->first_busno;
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case IOBASE_MEMORY:
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return (long)hose->pci_mem_offset;
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case IOBASE_IO:
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return (long)hose->io_base_phys;
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case IOBASE_ISA_IO:
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return (long)isa_io_base;
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case IOBASE_ISA_MEM:
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return (long)isa_mem_base;
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}
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return result;
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}
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/*
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* Null PCI config access functions, for the case when we can't
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* find a hose.
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@ -1626,3 +1737,4 @@ int early_find_capability(struct pci_controller *hose, int bus, int devfn,
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{
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return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
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}
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@ -1,138 +0,0 @@
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/*
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* Common pmac/prep/chrp pci routines. -- Cort
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/capability.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/sections.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/uaccess.h>
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#undef DEBUG
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unsigned long isa_io_base;
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unsigned long pci_dram_offset;
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static int pci_bus_count;
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return of_node_get(hose->dn);
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}
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static void __devinit pcibios_scan_phb(struct pci_controller *hose)
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{
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struct pci_bus *bus;
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struct device_node *node = hose->dn;
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unsigned long io_offset;
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struct resource *res = &hose->io_resource;
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pr_debug("PCI: Scanning PHB %s\n",
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node ? node->full_name : "<NO NAME>");
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/* Create an empty bus for the toplevel */
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bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
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if (bus == NULL) {
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printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
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hose->global_number);
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return;
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}
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bus->secondary = hose->first_busno;
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hose->bus = bus;
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/* Fixup IO space offset */
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io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
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res->start = (res->start + io_offset) & 0xffffffffu;
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res->end = (res->end + io_offset) & 0xffffffffu;
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/* Wire up PHB bus resources */
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pcibios_setup_phb_resources(hose);
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/* Scan children */
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hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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int next_busno = 0;
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printk(KERN_INFO "PCI: Probing PCI hardware\n");
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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hose->last_busno = 0xff;
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pcibios_scan_phb(hose);
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printk(KERN_INFO "calling pci_bus_add_devices()\n");
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pci_bus_add_devices(hose->bus);
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if (next_busno <= hose->last_busno)
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next_busno = hose->last_busno + 1;
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}
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pci_bus_count = next_busno;
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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return 0;
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}
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subsys_initcall(pcibios_init);
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static struct pci_controller*
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pci_bus_to_hose(int bus)
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{
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struct pci_controller *hose, *tmp;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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return NULL;
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}
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/* Provide information on locations of various I/O regions in physical
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* memory. Do this on a per-card basis so that we choose the right
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* root bridge.
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* Note that the returned IO or memory base is a physical address
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*/
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long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
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{
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struct pci_controller *hose;
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long result = -EOPNOTSUPP;
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hose = pci_bus_to_hose(bus);
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if (!hose)
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return -ENODEV;
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switch (which) {
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case IOBASE_BRIDGE_NUMBER:
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return (long)hose->first_busno;
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case IOBASE_MEMORY:
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return (long)hose->pci_mem_offset;
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case IOBASE_IO:
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return (long)hose->io_base_phys;
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case IOBASE_ISA_IO:
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return (long)isa_io_base;
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case IOBASE_ISA_MEM:
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return (long)isa_mem_base;
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}
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return result;
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}
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