habanalabs: refactoring in goya.c
This patch does some refactoring in goya.c to make code more reusable between goya code and the goya simulator code (which is not upstreamed). In addition, the patch removes some dead functions from goya.c which are not used by the current upstream code Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Oded Gabbay
parent
90027296ad
commit
bedd14425d
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@ -78,7 +78,6 @@
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#define GOYA_RESET_WAIT_MSEC 1 /* 1ms */
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#define GOYA_CPU_RESET_WAIT_MSEC 100 /* 100ms */
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#define GOYA_PLDM_RESET_WAIT_MSEC 1000 /* 1s */
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#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */
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#define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */
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#define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100)
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#define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30)
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@ -298,12 +297,6 @@ static u32 goya_all_events[] = {
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GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
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};
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static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
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static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
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static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
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static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
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u64 phys_addr);
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static void goya_get_fixed_properties(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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@ -511,6 +504,28 @@ static int goya_early_fini(struct hl_device *hdev)
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return 0;
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}
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static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
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{
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/* mask to zero the MMBP and ASID bits */
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WREG32_AND(reg, ~0x7FF);
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WREG32_OR(reg, asid);
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}
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static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
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{
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struct goya_device *goya = hdev->asic_specific;
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if (!(goya->hw_cap_initialized & HW_CAP_MMU))
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return;
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if (secure)
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WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
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else
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WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
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RREG32(mmDMA_QM_0_GLBL_PROT);
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}
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/*
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* goya_fetch_psoc_frequency - Fetch PSOC frequency values
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*
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@ -633,6 +648,9 @@ static int goya_sw_init(struct hl_device *hdev)
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goya->tpc_clk = GOYA_PLL_FREQ_LOW;
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goya->ic_clk = GOYA_PLL_FREQ_LOW;
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goya->mmu_prepare_reg = goya_mmu_prepare_reg;
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goya->qman0_set_security = goya_qman0_set_security;
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hdev->asic_specific = goya;
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/* Create DMA pool for small allocations */
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@ -2324,6 +2342,38 @@ out:
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return 0;
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}
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static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
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u64 phys_addr)
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{
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u32 status, timeout_usec;
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int rc;
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if (hdev->pldm)
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timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
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else
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timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
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WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
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WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
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WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
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rc = hl_poll_timeout(
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hdev,
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MMU_ASID_BUSY,
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status,
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!(status & 0x80000000),
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1000,
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timeout_usec);
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if (rc) {
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dev_err(hdev->dev,
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"Timeout during MMU hop0 config of asid %d\n", asid);
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return rc;
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}
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return 0;
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}
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static int goya_mmu_init(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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@ -2798,10 +2848,7 @@ static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
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*fence_ptr = 0;
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if (goya->hw_cap_initialized & HW_CAP_MMU) {
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WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
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RREG32(mmDMA_QM_0_GLBL_PROT);
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}
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goya->qman0_set_security(hdev, true);
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/*
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* goya cs parser saves space for 2xpacket_msg_prot at end of CB. For
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@ -2843,10 +2890,7 @@ free_fence_ptr:
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hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
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fence_dma_addr);
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if (goya->hw_cap_initialized & HW_CAP_MMU) {
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WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
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RREG32(mmDMA_QM_0_GLBL_PROT);
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}
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goya->qman0_set_security(hdev, false);
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return rc;
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}
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@ -2953,7 +2997,7 @@ int goya_test_cpu_queue(struct hl_device *hdev)
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return hl_fw_test_cpu_queue(hdev);
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}
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static int goya_test_queues(struct hl_device *hdev)
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int goya_test_queues(struct hl_device *hdev)
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{
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int i, rc, ret_val = 0;
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@ -2987,14 +3031,14 @@ static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
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dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
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}
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static void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev,
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size_t size, dma_addr_t *dma_handle)
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void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
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dma_addr_t *dma_handle)
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{
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return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
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}
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static void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev,
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size_t size, void *vaddr)
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void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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void *vaddr)
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{
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hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
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}
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@ -4211,8 +4255,8 @@ static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
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pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
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ARMCP_PKT_CTL_OPCODE_SHIFT);
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rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
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total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result);
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rc = goya_send_cpu_message(hdev, (u32 *) pkt, total_pkt_size,
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HL_DEVICE_TIMEOUT_USEC, &result);
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if (rc)
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dev_err(hdev->dev, "failed to unmask IRQ array\n");
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@ -4244,7 +4288,7 @@ static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
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ARMCP_PKT_CTL_OPCODE_SHIFT);
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pkt.value = cpu_to_le64(event_type);
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rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
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rc = goya_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
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HL_DEVICE_TIMEOUT_USEC, &result);
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if (rc)
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@ -4466,7 +4510,7 @@ static int goya_context_switch(struct hl_device *hdev, u32 asid)
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return 0;
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}
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static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
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int goya_mmu_clear_pgt_range(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct goya_device *goya = hdev->asic_specific;
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@ -4480,7 +4524,7 @@ static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
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return goya_memset_device_memory(hdev, addr, size, 0, true);
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}
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static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
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int goya_mmu_set_dram_default_page(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
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@ -4493,7 +4537,7 @@ static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
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return goya_memset_device_memory(hdev, addr, size, val, true);
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}
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static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
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void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
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{
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struct goya_device *goya = hdev->asic_specific;
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int i;
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@ -4507,10 +4551,8 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
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}
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/* zero the MMBP and ASID bits and then set the ASID */
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for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++) {
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WREG32_AND(goya_mmu_regs[i], ~0x7FF);
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WREG32_OR(goya_mmu_regs[i], asid);
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}
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for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
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goya->mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
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}
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static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
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@ -4601,38 +4643,6 @@ static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
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"Timeout when waiting for MMU cache invalidation\n");
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}
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static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
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u64 phys_addr)
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{
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u32 status, timeout_usec;
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int rc;
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if (hdev->pldm)
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timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
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else
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timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
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WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
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WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
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WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
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rc = hl_poll_timeout(
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hdev,
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MMU_ASID_BUSY,
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status,
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!(status & 0x80000000),
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1000,
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timeout_usec);
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if (rc) {
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dev_err(hdev->dev,
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"Timeout during MMU hop0 config of asid %d\n", asid);
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return rc;
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}
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return 0;
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}
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int goya_send_heartbeat(struct hl_device *hdev)
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{
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struct goya_device *goya = hdev->asic_specific;
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@ -4674,16 +4684,6 @@ int goya_armcp_info_get(struct hl_device *hdev)
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return 0;
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}
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static void goya_init_clock_gating(struct hl_device *hdev)
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{
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}
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static void goya_disable_clock_gating(struct hl_device *hdev)
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{
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}
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static bool goya_is_device_idle(struct hl_device *hdev, char *buf, size_t size)
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{
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u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg;
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@ -4814,8 +4814,6 @@ static const struct hl_asic_funcs goya_funcs = {
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.mmu_invalidate_cache = goya_mmu_invalidate_cache,
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.mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
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.send_heartbeat = goya_send_heartbeat,
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.enable_clock_gating = goya_init_clock_gating,
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.disable_clock_gating = goya_disable_clock_gating,
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.debug_coresight = goya_debug_coresight,
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.is_device_idle = goya_is_device_idle,
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.soft_reset_late_init = goya_soft_reset_late_init,
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@ -39,11 +39,13 @@
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#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
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#endif
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#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
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#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
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#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */
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#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */
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#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
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#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
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#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */
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#define TPC_ENABLED_MASK 0xFF
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@ -145,6 +147,9 @@ enum goya_fw_component {
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};
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struct goya_device {
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void (*mmu_prepare_reg)(struct hl_device *hdev, u64 reg, u32 asid);
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void (*qman0_set_security)(struct hl_device *hdev, bool secure);
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/* TODO: remove hw_queues_lock after moving to scheduler code */
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spinlock_t hw_queues_lock;
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@ -180,6 +185,10 @@ void goya_init_security(struct hl_device *hdev);
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int goya_debug_coresight(struct hl_device *hdev, void *data);
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u64 goya_get_max_power(struct hl_device *hdev);
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void goya_set_max_power(struct hl_device *hdev, u64 value);
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int goya_test_queues(struct hl_device *hdev);
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void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
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int goya_mmu_clear_pgt_range(struct hl_device *hdev);
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int goya_mmu_set_dram_default_page(struct hl_device *hdev);
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void goya_late_fini(struct hl_device *hdev);
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int goya_suspend(struct hl_device *hdev);
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@ -195,5 +204,9 @@ void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
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u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
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int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
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int goya_send_heartbeat(struct hl_device *hdev);
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void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
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dma_addr_t *dma_handle);
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void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
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void *vaddr);
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#endif /* GOYAP_H_ */
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@ -481,8 +481,6 @@ enum hl_pll_frequency {
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* @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
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* ASID-VA-size mask.
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* @send_heartbeat: send is-alive packet to ArmCP and verify response.
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* @enable_clock_gating: enable clock gating for reducing power consumption.
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* @disable_clock_gating: disable clock for accessing registers on HBW.
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* @debug_coresight: perform certain actions on Coresight for debugging.
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* @is_device_idle: return true if device is idle, false otherwise.
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* @soft_reset_late_init: perform certain actions needed after soft reset.
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@ -556,8 +554,6 @@ struct hl_asic_funcs {
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void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
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u32 asid, u64 va, u64 size);
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int (*send_heartbeat)(struct hl_device *hdev);
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void (*enable_clock_gating)(struct hl_device *hdev);
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void (*disable_clock_gating)(struct hl_device *hdev);
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int (*debug_coresight)(struct hl_device *hdev, void *data);
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bool (*is_device_idle)(struct hl_device *hdev, char *buf, size_t size);
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int (*soft_reset_late_init)(struct hl_device *hdev);
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