[PATCH] kbuild: more Makefile cleanups
This adds the remaining changes which should have been part of the review process. - the define command is inappropriate (it's primarily for rule definitions) - execute commands in the current dir as all other commands - .*.tmp (but not .*.null) files are also removed up by "make clean" - printf has other side effects, just use "echo -e" - proper quoting - proper indentation Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Roman Zippel
Linus Torvalds
parent
2fd592e45b
commit
beda9f3a13
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@ -1,7 +1,7 @@
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####
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# kbuild: Generic definitions
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# Convenient constants
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# Convenient variables
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comma := ,
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squote := '
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empty :=
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@ -56,44 +56,48 @@ endef
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# gcc support functions
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# See documentation in Documentation/kbuild/makefiles.txt
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# checker-shell
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# Usage: option = $(call checker-shell,$(CC)...-o $$OUT,option-ok,otherwise)
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# Exit code chooses option. $$OUT is safe location for needless output.
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define checker-shell
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$(shell set -e; \
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DIR=$(KBUILD_EXTMOD); \
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cd $${DIR:-$(objtree)}; \
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OUT=$$PWD/.$$$$.null; \
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if $(1) >/dev/null 2>&1; \
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then echo "$(2)"; \
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else echo "$(3)"; \
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fi; \
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rm -f $$OUT)
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endef
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# output directory for tests below
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TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/)
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# try-run
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# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise)
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# Exit code chooses option. "$$TMP" is can be used as temporary file and
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# is automatically cleaned up.
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try-run = $(shell set -e; \
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TMP="$(TMPOUT).$$$$.tmp"; \
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if ($(1)) >/dev/null 2>&1; \
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then echo "$(2)"; \
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else echo "$(3)"; \
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fi; \
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rm -f "$$TMP")
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# as-option
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# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,)
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as-option = $(call checker-shell,\
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$(CC) $(CFLAGS) $(1) -c -xassembler /dev/null -o $$OUT,$(1),$(2))
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as-option = $(call try-run,\
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$(CC) $(CFLAGS) $(1) -c -xassembler /dev/null -o "$$TMP",$(1),$(2))
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# as-instr
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# Usage: cflags-y += $(call as-instr,instr,option1,option2)
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as-instr = $(call checker-shell,\
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printf "$(1)" | $(CC) $(AFLAGS) -c -xassembler -o $$OUT -,$(2),$(3))
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as-instr = $(call try-run,\
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echo -e "$(1)" | $(CC) $(AFLAGS) -c -xassembler -o "$$TMP" -,$(2),$(3))
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# cc-option
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# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586)
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cc-option = $(call checker-shell,\
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$(CC) $(CFLAGS) $(if $(3),$(3),$(1)) -S -xc /dev/null -o $$OUT,$(1),$(2))
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cc-option = $(call try-run,\
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$(CC) $(CFLAGS) $(1) -S -xc /dev/null -o "$$TMP",$(1),$(2))
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# cc-option-yn
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# Usage: flag := $(call cc-option-yn,-march=winchip-c6)
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cc-option-yn = $(call cc-option,"y","n",$(1))
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cc-option-yn = $(call try-run,\
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$(CC) $(CFLAGS) $(1) -S -xc /dev/null -o "$$TMP",y,n)
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# cc-option-align
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# Prefix align with either -falign or -malign
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cc-option-align = $(subst -functions=0,,\
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$(call cc-option,-falign-functions=0,-malign-functions=0))
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$(call cc-option,-falign-functions=0,-malign-functions=0))
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# cc-version
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# Usage gcc-ver := $(call cc-version,$(CC))
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@ -105,24 +109,22 @@ cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3))
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# ld-option
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# Usage: ldflags += $(call ld-option, -Wl$(comma)--hash-style=both)
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ld-option = $(call checker-shell,\
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$(CC) $(1) -nostdlib -xc /dev/null -o $$OUT,$(1),$(2))
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ld-option = $(call try-run,\
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$(CC) $(1) -nostdlib -xc /dev/null -o "$$TMP",$(1),$(2))
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######
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###
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# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
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# Usage:
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# $(Q)$(MAKE) $(build)=dir
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build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
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# Prefix -I with $(srctree) if it is not an absolute path,
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# add original to the end
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addtree = $(if \
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$(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1)
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# Prefix -I with $(srctree) if it is not an absolute path.
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addtree = $(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1)
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# Find all -I options and call addtree
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flags = $(foreach o,$($(1)),\
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$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
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flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
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# echo command.
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# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
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@ -144,7 +146,7 @@ objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o)))
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# See Documentation/kbuild/makefiles.txt for more info
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ifneq ($(KBUILD_NOCMDDEP),1)
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# Check if both arguments has same arguments. Result is empty string, if equal.
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# Check if both arguments has same arguments. Result is empty string if equal.
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# User may override this check using make KBUILD_NOCMDDEP=1
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arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
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$(filter-out $(cmd_$@), $(cmd_$(1))) )
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@ -168,7 +170,6 @@ if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
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echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
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# Execute the command and also postprocess generated .d dependencies file.
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#
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if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
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@set -e; \
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$(echo-cmd) $(cmd_$(1)); \
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@ -176,10 +177,9 @@ if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
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rm -f $(depfile); \
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mv -f $(dot-target).tmp $(dot-target).cmd)
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# Will check if $(cmd_foo) changed, or any of the prerequisites changed,
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# and if so will execute $(rule_foo).
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# Usage: $(call if_changed_rule,foo)
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#
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# Will check if $(cmd_foo) or any of the prerequisites changed,
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# and if so will execute $(rule_foo).
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if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \
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@set -e; \
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$(rule_$(1)))
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