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ARM: SoC low-priority fixes for 3.13 

A set of fixes for various platforms that weren't considered bad enough
 to include in 3.12 (nor -stable). Mostly simple typo fixes, etc.
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Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC low-priority fixes from Olof Johansson:
 "A set of fixes for various platforms that weren't considered bad
  enough to include in 3.12 (nor -stable).  Mostly simple typo fixes,
  etc"

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: OMAP2+: irq, AM33XX add missing register check
  ARM: OMAP2+: wakeupgen: AM43x adaptation
  ARM: OMAP1: Fix a bunch of GPIO related section warnings after initdata got corrected
  ARM: dts: fix PL330 MDMA1 address in DT for Universal C210 board
  ARM: dts: Work around lack of cpufreq regulator lookup for exynos4210-origen and trats boards
  ARM: dts: Fix typo earlyprintk in exynos5440-sd5v1 and ssdk5440 boards
  ARM: dts: Correct typo in use of samsung,pin-drv for exynos5250
  ARM: rockchip: remove obsolete rockchip,config properties
  ARM: rockchip: fix wrong use of non-existent CONFIG_LOCAL_TIMERS
  ARM: mach-omap1: Fix omap1510_fpga_init_irq() implicit declarations.
  ARM: OMAP1: fix incorrect placement of __initdata tag
  ARM: OMAP: remove deprecated IRQF_DISABLED
  ARM: OMAP2+: throw the die id into the entropy pool
This commit is contained in:
Linus Torvalds 2013-11-11 16:35:29 +09:00
parent 05ad391dbc 462fb38f3d
commit beb5bfe424
21 changed files with 104 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -192,7 +192,12 @@
};
buck1_reg: BUCK1 {
regulator-name = "VDD_ARM_1.2V";
/*
* HACK: The real name is VDD_ARM_1.2V,
* but exynos-cpufreq does not support
* DT-based regulator lookup yet.
*/
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;

7
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -290,7 +290,12 @@
};
varm_breg: BUCK1 {
regulator-name = "VARM_1.2V_C210";
/*
* HACK: The real name is VARM_1.2V_C210,
* but exynos-cpufreq does not support
* DT-based regulator lookup yet.
*/
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;

4
arch/arm/boot/dts/exynos4210-universal_c210.dts
View File

@ -350,3 +350,7 @@
status = "okay";
};
};
&mdma1 {
reg = <0x12840000 0x1000>;
};

44
arch/arm/boot/dts/exynos5250-pinctrl.dtsi
View File

@ -210,21 +210,21 @@
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c2_hs_bus: i2c2-hs-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
@ -238,21 +238,21 @@
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c3_hs_bus: i2c3-hs-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
uart3_data: uart3-data {
@ -273,14 +273,14 @@
samsung,pins = "gpa2-0", "gpa2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c5_bus: i2c5-bus {
samsung,pins = "gpa2-2", "gpa2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
@ -376,14 +376,14 @@
samsung,pins = "gpb3-0", "gpb3-1";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
i2c1_hs_bus: i2c1-hs-bus {
samsung,pins = "gpb3-2", "gpb3-3";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
sd0_clk: sd0-clk {
@ -551,14 +551,14 @@
samsung,pins = "gpd0-2", "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
dp_hpd: dp_hpd {
samsung,pins = "gpx0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
};
@ -649,42 +649,42 @@
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_i2c2_bus: cam-i2c2-bus {
samsung,pins = "gpe0-6", "gpe1-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_spi1_bus: cam-spi1-bus {
samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_i2c1_bus: cam-i2c1-bus {
samsung,pins = "gpf0-2", "gpf0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_i2c0_bus: cam-i2c0-bus {
samsung,pins = "gpf0-0", "gpf0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_spi0_bus: cam-spi0-bus {
samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_bayrgb_bus: cam-bayrgb-bus {
@ -695,7 +695,7 @@
"gpg2-0", "gpg2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
cam_port_a: cam-port-a {
@ -704,7 +704,7 @@
"gph1-4", "gph1-5", "gph1-6", "gph1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
};
@ -756,7 +756,7 @@
"gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
c2c_txd: c2c-txd {
@ -766,7 +766,7 @@
"gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
samsung,pin-drv = <0>;
};
};

2
arch/arm/boot/dts/exynos5440-sd5v1.dts
View File

@ -17,7 +17,7 @@
compatible = "samsung,sd5v1", "samsung,exynos5440";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
};
fixed-rate-clocks {

2
arch/arm/boot/dts/exynos5440-ssdk5440.dts
View File

@ -17,7 +17,7 @@
compatible = "samsung,ssdk5440", "samsung,exynos5440";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
};
spi_0: spi@D0000 {

22
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -191,17 +191,14 @@
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
};
@ -209,17 +206,14 @@
uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
};
@ -227,7 +221,6 @@
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};
@ -236,44 +229,36 @@
uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd0_bus4: sd0-bus-width4 {
@ -281,34 +266,28 @@
<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
sd1_bus4: sd1-bus-width4 {
@ -316,7 +295,6 @@
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
rockchip,config = <&pcfg_pull_default>;
};
};
};

3
arch/arm/mach-omap1/common.h
View File

@ -46,6 +46,9 @@ static inline void omap7xx_map_io(void)
void omap1510_fpga_init_irq(void);
void omap15xx_map_io(void);
#else
static inline void omap1510_fpga_init_irq(void)
{
}
static inline void omap15xx_map_io(void)
{
}

3
arch/arm/mach-omap1/fpga.c
View File

@ -135,8 +135,7 @@ static struct irq_chip omap_fpga_irq = {
* mask_ack routine for all of the FPGA interrupts has been changed from
* fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
* being serviced is left unmasked. We can do this because the FPGA cascade
* interrupt is installed with the IRQF_DISABLED flag, which leaves all
* interrupts masked at the CPU while an FPGA interrupt handler executes.
* interrupt is run with all interrupts masked.
*
* Limited testing indicates that this workaround appears to be effective
* for the smc9194 Ethernet driver used on the Innovator. It should work

8
arch/arm/mach-omap1/gpio15xx.c
View File

@ -25,7 +25,7 @@
#define OMAP1510_GPIO_BASE 0xFFFCE000
/* gpio1 */
static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
static struct resource omap15xx_mpu_gpio_resources[] = {
{
.start = OMAP1_MPUIO_VBASE,
.end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
@ -48,7 +48,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
static struct omap_gpio_platform_data omap15xx_mpu_gpio_config = {
.is_mpuio = true,
.bank_width = 16,
.bank_stride = 1,
@ -66,7 +66,7 @@ static struct platform_device omap15xx_mpu_gpio = {
};
/* gpio2 */
static struct __initdata resource omap15xx_gpio_resources[] = {
static struct resource omap15xx_gpio_resources[] = {
{
.start = OMAP1510_GPIO_BASE,
.end = OMAP1510_GPIO_BASE + SZ_2K - 1,
@ -90,7 +90,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.pinctrl = OMAP1510_GPIO_PIN_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
static struct omap_gpio_platform_data omap15xx_gpio_config = {
.bank_width = 16,
.regs = &omap15xx_gpio_regs,
};

22
arch/arm/mach-omap1/gpio16xx.c
View File

@ -31,7 +31,7 @@
#define SYSCONFIG_WORD 0x14
/* mpu gpio */
static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
static struct resource omap16xx_mpu_gpio_resources[] = {
{
.start = OMAP1_MPUIO_VBASE,
.end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
@ -54,7 +54,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
static struct omap_gpio_platform_data omap16xx_mpu_gpio_config = {
.is_mpuio = true,
.bank_width = 16,
.bank_stride = 1,
@ -72,7 +72,7 @@ static struct platform_device omap16xx_mpu_gpio = {
};
/* gpio1 */
static struct __initdata resource omap16xx_gpio1_resources[] = {
static struct resource omap16xx_gpio1_resources[] = {
{
.start = OMAP1610_GPIO1_BASE,
.end = OMAP1610_GPIO1_BASE + SZ_2K - 1,
@ -100,7 +100,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
static struct omap_gpio_platform_data omap16xx_gpio1_config = {
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@ -116,7 +116,7 @@ static struct platform_device omap16xx_gpio1 = {
};
/* gpio2 */
static struct __initdata resource omap16xx_gpio2_resources[] = {
static struct resource omap16xx_gpio2_resources[] = {
{
.start = OMAP1610_GPIO2_BASE,
.end = OMAP1610_GPIO2_BASE + SZ_2K - 1,
@ -128,7 +128,7 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
static struct omap_gpio_platform_data omap16xx_gpio2_config = {
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@ -144,7 +144,7 @@ static struct platform_device omap16xx_gpio2 = {
};
/* gpio3 */
static struct __initdata resource omap16xx_gpio3_resources[] = {
static struct resource omap16xx_gpio3_resources[] = {
{
.start = OMAP1610_GPIO3_BASE,
.end = OMAP1610_GPIO3_BASE + SZ_2K - 1,
@ -156,7 +156,7 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
static struct omap_gpio_platform_data omap16xx_gpio3_config = {
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@ -172,7 +172,7 @@ static struct platform_device omap16xx_gpio3 = {
};
/* gpio4 */
static struct __initdata resource omap16xx_gpio4_resources[] = {
static struct resource omap16xx_gpio4_resources[] = {
{
.start = OMAP1610_GPIO4_BASE,
.end = OMAP1610_GPIO4_BASE + SZ_2K - 1,
@ -184,7 +184,7 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
static struct omap_gpio_platform_data omap16xx_gpio4_config = {
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@ -199,7 +199,7 @@ static struct platform_device omap16xx_gpio4 = {
.resource = omap16xx_gpio4_resources,
};
static struct __initdata platform_device * omap16xx_gpio_dev[] = {
static struct platform_device *omap16xx_gpio_dev[] __initdata = {
&omap16xx_mpu_gpio,
&omap16xx_gpio1,
&omap16xx_gpio2,

30
arch/arm/mach-omap1/gpio7xx.c
View File

@ -30,7 +30,7 @@
#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
/* mpu gpio */
static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
static struct resource omap7xx_mpu_gpio_resources[] = {
{
.start = OMAP1_MPUIO_VBASE,
.end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
@ -53,7 +53,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
.irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
};
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.is_mpuio = true,
.bank_width = 16,
.bank_stride = 2,
@ -71,7 +71,7 @@ static struct platform_device omap7xx_mpu_gpio = {
};
/* gpio1 */
static struct __initdata resource omap7xx_gpio1_resources[] = {
static struct resource omap7xx_gpio1_resources[] = {
{
.start = OMAP7XX_GPIO1_BASE,
.end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
@ -94,7 +94,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
.irqctrl = OMAP7XX_GPIO_INT_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
static struct omap_gpio_platform_data omap7xx_gpio1_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -110,7 +110,7 @@ static struct platform_device omap7xx_gpio1 = {
};
/* gpio2 */
static struct __initdata resource omap7xx_gpio2_resources[] = {
static struct resource omap7xx_gpio2_resources[] = {
{
.start = OMAP7XX_GPIO2_BASE,
.end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
@ -122,7 +122,7 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
static struct omap_gpio_platform_data omap7xx_gpio2_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -138,7 +138,7 @@ static struct platform_device omap7xx_gpio2 = {
};
/* gpio3 */
static struct __initdata resource omap7xx_gpio3_resources[] = {
static struct resource omap7xx_gpio3_resources[] = {
{
.start = OMAP7XX_GPIO3_BASE,
.end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
@ -150,7 +150,7 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
static struct omap_gpio_platform_data omap7xx_gpio3_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -166,7 +166,7 @@ static struct platform_device omap7xx_gpio3 = {
};
/* gpio4 */
static struct __initdata resource omap7xx_gpio4_resources[] = {
static struct resource omap7xx_gpio4_resources[] = {
{
.start = OMAP7XX_GPIO4_BASE,
.end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
@ -178,7 +178,7 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
static struct omap_gpio_platform_data omap7xx_gpio4_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -194,7 +194,7 @@ static struct platform_device omap7xx_gpio4 = {
};
/* gpio5 */
static struct __initdata resource omap7xx_gpio5_resources[] = {
static struct resource omap7xx_gpio5_resources[] = {
{
.start = OMAP7XX_GPIO5_BASE,
.end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
@ -206,7 +206,7 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
static struct omap_gpio_platform_data omap7xx_gpio5_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -222,7 +222,7 @@ static struct platform_device omap7xx_gpio5 = {
};
/* gpio6 */
static struct __initdata resource omap7xx_gpio6_resources[] = {
static struct resource omap7xx_gpio6_resources[] = {
{
.start = OMAP7XX_GPIO6_BASE,
.end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
@ -234,7 +234,7 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
},
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
static struct omap_gpio_platform_data omap7xx_gpio6_config = {
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@ -249,7 +249,7 @@ static struct platform_device omap7xx_gpio6 = {
.resource = omap7xx_gpio6_resources,
};
static struct __initdata platform_device * omap7xx_gpio_dev[] = {
static struct platform_device *omap7xx_gpio_dev[] __initdata = {
&omap7xx_mpu_gpio,
&omap7xx_gpio1,
&omap7xx_gpio2,

1
arch/arm/mach-omap1/pm.c
View File

@ -628,7 +628,6 @@ static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
static struct irqaction omap_wakeup_irq = {
.name = "peripheral wakeup",
.flags = IRQF_DISABLED,
.handler = omap_wakeup_interrupt
};

2
arch/arm/mach-omap1/time.c
View File

@ -160,7 +160,7 @@ static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
static struct irqaction omap_mpu_timer1_irq = {
.name = "mpu_timer1",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = omap_mpu_timer1_interrupt,
};

2
arch/arm/mach-omap1/timer32k.c
View File

@ -156,7 +156,7 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
static struct irqaction omap_32k_timer_irq = {
.name = "32KHz timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = omap_32k_timer_interrupt,
};

12
arch/arm/mach-omap2/id.c
View File

@ -18,6 +18,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/random.h>
#include <linux/slab.h>
#ifdef CONFIG_SOC_BUS
@ -130,6 +131,17 @@ void omap_get_die_id(struct omap_die_id *odi)
odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}
static int __init omap_feed_randpool(void)
{
struct omap_die_id odi;
/* Throw the die ID into the entropy pool at boot */
omap_get_die_id(&odi);
add_device_randomness(&odi, sizeof(odi));
return 0;
}
omap_device_initcall(omap_feed_randpool);
void __init omap2xxx_check_revision(void)
{
int i, j;

2
arch/arm/mach-omap2/irq.c
View File

@ -233,7 +233,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
goto out;
irqnr = readl_relaxed(base_addr + 0xd8);
#ifdef CONFIG_SOC_TI81XX
#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
if (irqnr)
goto out;
irqnr = readl_relaxed(base_addr + 0xf8);

18
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -33,8 +33,12 @@
#include "omap4-sar-layout.h"
#include "common.h"
#define MAX_NR_REG_BANKS 5
#define MAX_IRQS 160
#define AM43XX_NR_REG_BANKS 7
#define AM43XX_IRQS 224
#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
#define MAX_IRQS AM43XX_IRQS
#define DEFAULT_NR_REG_BANKS 5
#define DEFAULT_IRQS 160
#define WKG_MASK_ALL 0x00000000
#define WKG_UNMASK_ALL 0xffffffff
#define CPU_ENA_OFFSET 0x400
@ -47,8 +51,8 @@ static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = MAX_NR_REG_BANKS;
static unsigned int max_irqs = MAX_IRQS;
static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
static unsigned int max_irqs = DEFAULT_IRQS;
static unsigned int omap_secure_apis;
/*
@ -418,12 +422,16 @@ int __init omap_wakeupgen_init(void)
irq_banks = OMAP4_NR_BANKS;
max_irqs = OMAP4_NR_IRQS;
omap_secure_apis = 1;
} else if (soc_is_am43xx()) {
irq_banks = AM43XX_NR_REG_BANKS;
max_irqs = AM43XX_IRQS;
}
/* Clear all IRQ bitmasks at wakeupGen level */
for (i = 0; i < irq_banks; i++) {
wakeupgen_writel(0, i, CPU0_ID);
wakeupgen_writel(0, i, CPU1_ID);
if (!soc_is_am43xx())
wakeupgen_writel(0, i, CPU1_ID);
}
/*

2
arch/arm/mach-omap2/timer.c
View File

@ -78,7 +78,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
static struct irqaction omap2_gp_timer_irq = {
.name = "gp_timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = omap2_gp_timer_interrupt,
};

3
arch/arm/mach-rockchip/Kconfig
View File

@ -5,9 +5,8 @@ config ARCH_ROCKCHIP
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select CACHE_L2X0
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select LOCAL_TIMERS if SMP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select DW_APB_TIMER_OF

1
arch/arm/plat-omap/dma.c
View File

@ -1965,7 +1965,6 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
static struct irqaction omap24xx_dma_irq = {
.name = "DMA",
.handler = omap2_dma_irq_handler,
.flags = IRQF_DISABLED
};
#else