clocksource/drivers/rockchip: Add support for the rk3399 SoC
The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -19,7 +19,8 @@
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_CONTROL_REG3288 0x10
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#define TIMER_CONTROL_REG3399 0x1c
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#define TIMER_INT_STATUS 0x18
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#define TIMER_DISABLE 0x0
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@ -31,6 +32,7 @@
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struct bc_timer {
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struct clock_event_device ce;
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void __iomem *base;
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void __iomem *ctrl;
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u32 freq;
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};
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@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct clock_event_device *ce)
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return rk_timer(ce)->base;
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}
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static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
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{
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return rk_timer(ce)->ctrl;
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}
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static inline void rk_timer_disable(struct clock_event_device *ce)
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{
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writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
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writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
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}
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static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
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{
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writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
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rk_base(ce) + TIMER_CONTROL_REG);
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rk_ctrl(ce));
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}
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static void rk_timer_update_counter(unsigned long cycles,
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@ -106,7 +113,7 @@ static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static void __init rk_timer_init(struct device_node *np)
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static void __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
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{
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struct clock_event_device *ce = &bc_timer.ce;
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struct clk *timer_clk;
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@ -118,6 +125,7 @@ static void __init rk_timer_init(struct device_node *np)
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pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
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return;
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}
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bc_timer.ctrl = bc_timer.base + ctrl_reg;
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pclk = of_clk_get_by_name(np, "pclk");
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if (IS_ERR(pclk)) {
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@ -180,4 +188,17 @@ out_unmap:
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iounmap(bc_timer.base);
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}
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CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);
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static void __init rk3288_timer_init(struct device_node *np)
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{
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rk_timer_init(np, TIMER_CONTROL_REG3288);
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}
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static void __init rk3399_timer_init(struct device_node *np)
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{
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rk_timer_init(np, TIMER_CONTROL_REG3399);
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}
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CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
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rk3288_timer_init);
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CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
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rk3399_timer_init);
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