lan78xx: Remove phy defines in lan78xx.h and use defines in include/linux/microchipphy.h
Remove phy defines in lan78xx.h and use defines in include/linux/microchipphy.h. Signed-off-by: Woojung Huh <woojung.huh@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Woojung.Huh@microchip.com
David S. Miller
parent
ce85e13ad6
commit
bdfba55e0d
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@ -30,6 +30,7 @@
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#include <linux/ipv6.h>
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#include <linux/mdio.h>
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#include <net/ip6_checksum.h>
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#include <linux/microchipphy.h>
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#include "lan78xx.h"
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#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
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@ -837,8 +838,7 @@ static int lan78xx_link_reset(struct lan78xx_net *dev)
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u32 buf;
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/* clear PHY interrupt status */
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/* VTSE PHY */
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ret = phy_read(phydev, PHY_VTSE_INT_STS);
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ret = phy_read(phydev, LAN88XX_INT_STS);
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if (unlikely(ret < 0))
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return -EIO;
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@ -866,7 +866,7 @@ static int lan78xx_link_reset(struct lan78xx_net *dev)
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phy_ethtool_gset(phydev, &ecmd);
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ret = phy_read(phydev, PHY_VTSE_INT_STS);
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ret = phy_read(phydev, LAN88XX_INT_STS);
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if (dev->udev->speed == USB_SPEED_SUPER) {
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if (ethtool_cmd_speed(&ecmd) == 1000) {
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@ -1188,18 +1188,18 @@ static int lan78xx_get_settings(struct net_device *net, struct ethtool_cmd *cmd)
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ret = phy_ethtool_gset(phydev, cmd);
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phy_write(phydev, PHY_EXT_GPIO_PAGE, PHY_EXT_GPIO_PAGE_SPACE_1);
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buf = phy_read(phydev, PHY_EXT_MODE_CTRL);
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phy_write(phydev, PHY_EXT_GPIO_PAGE, PHY_EXT_GPIO_PAGE_SPACE_0);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
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buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
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buf &= PHY_EXT_MODE_CTRL_MDIX_MASK_;
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if (buf == PHY_EXT_MODE_CTRL_AUTO_MDIX_) {
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buf &= LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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if (buf == LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_) {
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cmd->eth_tp_mdix = ETH_TP_MDI_AUTO;
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cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
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} else if (buf == PHY_EXT_MODE_CTRL_MDI_) {
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} else if (buf == LAN88XX_EXT_MODE_CTRL_MDI_) {
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cmd->eth_tp_mdix = ETH_TP_MDI;
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cmd->eth_tp_mdix_ctrl = ETH_TP_MDI;
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} else if (buf == PHY_EXT_MODE_CTRL_MDI_X_) {
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} else if (buf == LAN88XX_EXT_MODE_CTRL_MDI_X_) {
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cmd->eth_tp_mdix = ETH_TP_MDI_X;
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cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_X;
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}
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@ -1222,32 +1222,32 @@ static int lan78xx_set_settings(struct net_device *net, struct ethtool_cmd *cmd)
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if (dev->mdix_ctrl != cmd->eth_tp_mdix_ctrl) {
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if (cmd->eth_tp_mdix_ctrl == ETH_TP_MDI) {
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_1);
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temp = phy_read(phydev, PHY_EXT_MODE_CTRL);
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temp &= ~PHY_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, PHY_EXT_MODE_CTRL,
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temp | PHY_EXT_MODE_CTRL_MDI_);
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_0);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_1);
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temp = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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temp &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
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temp | LAN88XX_EXT_MODE_CTRL_MDI_);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_0);
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} else if (cmd->eth_tp_mdix_ctrl == ETH_TP_MDI_X) {
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_1);
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temp = phy_read(phydev, PHY_EXT_MODE_CTRL);
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temp &= ~PHY_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, PHY_EXT_MODE_CTRL,
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temp | PHY_EXT_MODE_CTRL_MDI_X_);
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_0);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_1);
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temp = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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temp &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
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temp | LAN88XX_EXT_MODE_CTRL_MDI_X_);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_0);
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} else if (cmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) {
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_1);
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temp = phy_read(phydev, PHY_EXT_MODE_CTRL);
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temp &= ~PHY_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, PHY_EXT_MODE_CTRL,
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temp | PHY_EXT_MODE_CTRL_AUTO_MDIX_);
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phy_write(phydev, PHY_EXT_GPIO_PAGE,
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PHY_EXT_GPIO_PAGE_SPACE_0);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_1);
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temp = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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temp &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
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temp | LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS,
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LAN88XX_EXT_PAGE_SPACE_0);
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}
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}
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@ -1504,12 +1504,12 @@ static int lan78xx_phy_init(struct lan78xx_net *dev)
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}
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/* set to AUTOMDIX */
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phy_write(phydev, PHY_EXT_GPIO_PAGE, PHY_EXT_GPIO_PAGE_SPACE_1);
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ret = phy_read(phydev, PHY_EXT_MODE_CTRL);
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ret &= ~PHY_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, PHY_EXT_MODE_CTRL,
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ret | PHY_EXT_MODE_CTRL_AUTO_MDIX_);
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phy_write(phydev, PHY_EXT_GPIO_PAGE, PHY_EXT_GPIO_PAGE_SPACE_0);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
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ret = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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ret &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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phy_write(phydev, LAN88XX_EXT_MODE_CTRL,
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ret | LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
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dev->mdix_ctrl = ETH_TP_MDI_AUTO;
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/* MAC doesn't support 1000T Half */
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@ -874,196 +874,4 @@
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#define OTP_TPVSR_VAL (OTP_BASE_ADDR + 4 * 0x3A)
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#define OTP_TPVHR_VAL (OTP_BASE_ADDR + 4 * 0x3B)
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#define OTP_TPVSA_VAL (OTP_BASE_ADDR + 4 * 0x3C)
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#define PHY_ID1 (0x02)
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#define PHY_ID2 (0x03)
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#define PHY_DEV_ID_OUI_VTSE (0x04001C)
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#define PHY_DEV_ID_MODEL_VTSE_8502 (0x23)
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#define PHY_AUTONEG_ADV (0x04)
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#define NWAY_AR_NEXT_PAGE_ (0x8000)
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#define NWAY_AR_REMOTE_FAULT_ (0x2000)
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#define NWAY_AR_ASM_DIR_ (0x0800)
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#define NWAY_AR_PAUSE_ (0x0400)
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#define NWAY_AR_100T4_CAPS_ (0x0200)
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#define NWAY_AR_100TX_FD_CAPS_ (0x0100)
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#define NWAY_AR_SELECTOR_FIELD_ (0x001F)
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#define NWAY_AR_100TX_HD_CAPS_ (0x0080)
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#define NWAY_AR_10T_FD_CAPS_ (0x0040)
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#define NWAY_AR_10T_HD_CAPS_ (0x0020)
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#define NWAY_AR_ALL_CAPS_ (NWAY_AR_10T_HD_CAPS_ | \
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NWAY_AR_10T_FD_CAPS_ | \
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NWAY_AR_100TX_HD_CAPS_ | \
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NWAY_AR_100TX_FD_CAPS_)
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#define NWAY_AR_PAUSE_MASK (NWAY_AR_PAUSE_ | NWAY_AR_ASM_DIR_)
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#define PHY_LP_ABILITY (0x05)
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#define NWAY_LPAR_NEXT_PAGE_ (0x8000)
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#define NWAY_LPAR_ACKNOWLEDGE_ (0x4000)
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#define NWAY_LPAR_REMOTE_FAULT_ (0x2000)
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#define NWAY_LPAR_ASM_DIR_ (0x0800)
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#define NWAY_LPAR_PAUSE_ (0x0400)
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#define NWAY_LPAR_100T4_CAPS_ (0x0200)
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#define NWAY_LPAR_100TX_FD_CAPS_ (0x0100)
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#define NWAY_LPAR_100TX_HD_CAPS_ (0x0080)
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#define NWAY_LPAR_10T_FD_CAPS_ (0x0040)
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#define NWAY_LPAR_10T_HD_CAPS_ (0x0020)
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#define NWAY_LPAR_SELECTOR_FIELD_ (0x001F)
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#define PHY_AUTONEG_EXP (0x06)
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#define NWAY_ER_PAR_DETECT_FAULT_ (0x0010)
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#define NWAY_ER_LP_NEXT_PAGE_CAPS_ (0x0008)
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#define NWAY_ER_NEXT_PAGE_CAPS_ (0x0004)
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#define NWAY_ER_PAGE_RXD_ (0x0002)
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#define NWAY_ER_LP_NWAY_CAPS_ (0x0001)
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#define PHY_NEXT_PAGE_TX (0x07)
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#define NPTX_NEXT_PAGE_ (0x8000)
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#define NPTX_MSG_PAGE_ (0x2000)
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#define NPTX_ACKNOWLDGE2_ (0x1000)
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#define NPTX_TOGGLE_ (0x0800)
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#define NPTX_MSG_CODE_FIELD_ (0x0001)
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#define PHY_LP_NEXT_PAGE (0x08)
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#define LP_RNPR_NEXT_PAGE_ (0x8000)
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#define LP_RNPR_ACKNOWLDGE_ (0x4000)
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#define LP_RNPR_MSG_PAGE_ (0x2000)
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#define LP_RNPR_ACKNOWLDGE2_ (0x1000)
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#define LP_RNPR_TOGGLE_ (0x0800)
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#define LP_RNPR_MSG_CODE_FIELD_ (0x0001)
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#define PHY_1000T_CTRL (0x09)
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#define CR_1000T_TEST_MODE_4_ (0x8000)
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#define CR_1000T_TEST_MODE_3_ (0x6000)
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#define CR_1000T_TEST_MODE_2_ (0x4000)
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#define CR_1000T_TEST_MODE_1_ (0x2000)
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#define CR_1000T_MS_ENABLE_ (0x1000)
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#define CR_1000T_MS_VALUE_ (0x0800)
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#define CR_1000T_REPEATER_DTE_ (0x0400)
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#define CR_1000T_FD_CAPS_ (0x0200)
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#define CR_1000T_HD_CAPS_ (0x0100)
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#define CR_1000T_ASYM_PAUSE_ (0x0080)
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#define CR_1000T_TEST_MODE_NORMAL_ (0x0000)
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#define PHY_1000T_STATUS (0x0A)
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#define SR_1000T_MS_CONFIG_FAULT_ (0x8000)
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#define SR_1000T_MS_CONFIG_RES_ (0x4000)
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#define SR_1000T_LOCAL_RX_STATUS_ (0x2000)
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#define SR_1000T_REMOTE_RX_STATUS_ (0x1000)
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#define SR_1000T_LP_FD_CAPS_ (0x0800)
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#define SR_1000T_LP_HD_CAPS_ (0x0400)
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#define SR_1000T_ASYM_PAUSE_DIR_ (0x0100)
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#define SR_1000T_IDLE_ERROR_CNT_ (0x00FF)
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#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
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#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
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#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
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#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
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#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
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#define PHY_EXT_STATUS (0x0F)
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#define IEEE_ESR_1000X_FD_CAPS_ (0x8000)
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#define IEEE_ESR_1000X_HD_CAPS_ (0x4000)
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#define IEEE_ESR_1000T_FD_CAPS_ (0x2000)
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#define IEEE_ESR_1000T_HD_CAPS_ (0x1000)
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#define PHY_TX_POLARITY_MASK_ (0x0100)
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#define PHY_TX_NORMAL_POLARITY_ (0x0000)
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#define AUTO_POLARITY_DISABLE_ (0x0010)
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#define PHY_MMD_CTL (0x0D)
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#define PHY_MMD_CTRL_OP_MASK_ (0xC000)
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#define PHY_MMD_CTRL_OP_REG_ (0x0000)
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#define PHY_MMD_CTRL_OP_DNI_ (0x4000)
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#define PHY_MMD_CTRL_OP_DPIRW_ (0x8000)
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#define PHY_MMD_CTRL_OP_DPIWO_ (0xC000)
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#define PHY_MMD_CTRL_DEV_ADDR_MASK_ (0x001F)
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#define PHY_MMD_REG_DATA (0x0E)
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/* VTSE Vendor Specific registers */
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#define PHY_VTSE_BYPASS (0x12)
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#define PHY_VTSE_BYPASS_DISABLE_PAIR_SWAP_ (0x0020)
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#define PHY_VTSE_INT_MASK (0x19)
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#define PHY_VTSE_INT_MASK_MDINTPIN_EN_ (0x8000)
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#define PHY_VTSE_INT_MASK_SPEED_CHANGE_ (0x4000)
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#define PHY_VTSE_INT_MASK_LINK_CHANGE_ (0x2000)
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#define PHY_VTSE_INT_MASK_FDX_CHANGE_ (0x1000)
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#define PHY_VTSE_INT_MASK_AUTONEG_ERR_ (0x0800)
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#define PHY_VTSE_INT_MASK_AUTONEG_DONE_ (0x0400)
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#define PHY_VTSE_INT_MASK_POE_DETECT_ (0x0200)
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#define PHY_VTSE_INT_MASK_SYMBOL_ERR_ (0x0100)
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#define PHY_VTSE_INT_MASK_FAST_LINK_FAIL_ (0x0080)
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#define PHY_VTSE_INT_MASK_WOL_EVENT_ (0x0040)
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#define PHY_VTSE_INT_MASK_EXTENDED_INT_ (0x0020)
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#define PHY_VTSE_INT_MASK_RESERVED_ (0x0010)
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#define PHY_VTSE_INT_MASK_FALSE_CARRIER_ (0x0008)
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#define PHY_VTSE_INT_MASK_LINK_SPEED_DS_ (0x0004)
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#define PHY_VTSE_INT_MASK_MASTER_SLAVE_DONE_ (0x0002)
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#define PHY_VTSE_INT_MASK_RX__ER_ (0x0001)
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#define PHY_VTSE_INT_STS (0x1A)
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#define PHY_VTSE_INT_STS_INT_ACTIVE_ (0x8000)
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#define PHY_VTSE_INT_STS_SPEED_CHANGE_ (0x4000)
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#define PHY_VTSE_INT_STS_LINK_CHANGE_ (0x2000)
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#define PHY_VTSE_INT_STS_FDX_CHANGE_ (0x1000)
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#define PHY_VTSE_INT_STS_AUTONEG_ERR_ (0x0800)
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#define PHY_VTSE_INT_STS_AUTONEG_DONE_ (0x0400)
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#define PHY_VTSE_INT_STS_POE_DETECT_ (0x0200)
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#define PHY_VTSE_INT_STS_SYMBOL_ERR_ (0x0100)
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#define PHY_VTSE_INT_STS_FAST_LINK_FAIL_ (0x0080)
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#define PHY_VTSE_INT_STS_WOL_EVENT_ (0x0040)
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#define PHY_VTSE_INT_STS_EXTENDED_INT_ (0x0020)
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#define PHY_VTSE_INT_STS_RESERVED_ (0x0010)
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#define PHY_VTSE_INT_STS_FALSE_CARRIER_ (0x0008)
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#define PHY_VTSE_INT_STS_LINK_SPEED_DS_ (0x0004)
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#define PHY_VTSE_INT_STS_MASTER_SLAVE_DONE_ (0x0002)
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#define PHY_VTSE_INT_STS_RX_ER_ (0x0001)
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/* VTSE PHY registers */
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#define PHY_EXT_GPIO_PAGE (0x1F)
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#define PHY_EXT_GPIO_PAGE_SPACE_0 (0x0000)
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#define PHY_EXT_GPIO_PAGE_SPACE_1 (0x0001)
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#define PHY_EXT_GPIO_PAGE_SPACE_2 (0x0002)
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/* Extended Register Page 1 space */
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#define PHY_EXT_MODE_CTRL (0x13)
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#define PHY_EXT_MODE_CTRL_MDIX_MASK_ (0x000C)
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#define PHY_EXT_MODE_CTRL_AUTO_MDIX_ (0x0000)
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#define PHY_EXT_MODE_CTRL_MDI_ (0x0008)
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#define PHY_EXT_MODE_CTRL_MDI_X_ (0x000C)
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#define PHY_ANA_10BASE_T_HD 0x01
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#define PHY_ANA_10BASE_T_FD 0x02
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#define PHY_ANA_100BASE_TX_HD 0x04
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#define PHY_ANA_100BASE_TX_FD 0x08
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#define PHY_ANA_1000BASE_T_FD 0x10
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#define PHY_ANA_ALL_SUPPORTED_MEDIA (PHY_ANA_10BASE_T_HD | \
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PHY_ANA_10BASE_T_FD | \
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PHY_ANA_100BASE_TX_HD | \
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PHY_ANA_100BASE_TX_FD | \
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PHY_ANA_1000BASE_T_FD)
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/* PHY MMD registers */
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#define PHY_MMD_DEV_3 3
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#define PHY_EEE_PCS_STATUS (0x1)
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#define PHY_EEE_PCS_STATUS_TX_LPI_RCVD_ ((WORD)0x0800)
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#define PHY_EEE_PCS_STATUS_RX_LPI_RCVD_ ((WORD)0x0400)
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#define PHY_EEE_PCS_STATUS_TX_LPI_IND_ ((WORD)0x0200)
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#define PHY_EEE_PCS_STATUS_RX_LPI_IND_ ((WORD)0x0100)
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#define PHY_EEE_PCS_STATUS_PCS_RCV_LNK_STS_ ((WORD)0x0004)
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#define PHY_EEE_CAPABILITIES (0x14)
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#define PHY_EEE_CAPABILITIES_1000BT_EEE_ ((WORD)0x0004)
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#define PHY_EEE_CAPABILITIES_100BT_EEE_ ((WORD)0x0002)
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#define PHY_MMD_DEV_7 7
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#define PHY_EEE_ADVERTISEMENT (0x3C)
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#define PHY_EEE_ADVERTISEMENT_1000BT_EEE_ ((WORD)0x0004)
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#define PHY_EEE_ADVERTISEMENT_100BT_EEE_ ((WORD)0x0002)
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#define PHY_EEE_LP_ADVERTISEMENT (0x3D)
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#define PHY_EEE_1000BT_EEE_CAPABLE_ ((WORD)0x0004)
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#define PHY_EEE_100BT_EEE_CAPABLE_ ((WORD)0x0002)
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#endif /* _LAN78XX_H */
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||||
|
|
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Reference in New Issue