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drm/nouveau/msenc: rename from venc (no binary change) 

Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-01-14 12:37:00 +10:00
parent 8700287be2
commit bd8369ecf5
5 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -132,7 +132,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -56,7 +56,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_MSENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PM,
NVDEV_ENGINE_MSVLD,

2
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -239,7 +239,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
[NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,
[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
[NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
[NVDEV_ENGINE_MSENC] = NV_DEVICE_V0_DISABLE_MSENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
[NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
[NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC,

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
View File

@ -53,7 +53,7 @@ static const struct {
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
_(NVDEV_ENGINE_CE1 , 0),
_(NVDEV_ENGINE_VENC , 0),
_(NVDEV_ENGINE_MSENC , 0),
};
#undef _
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
@ -421,7 +421,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
case NVDEV_ENGINE_VENC : engn = 6; break;
case NVDEV_ENGINE_MSENC: engn = 6; break;
default:
return -1;
}
@ -626,7 +626,7 @@ nve0_fifo_fault_engine[] = {
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
{ 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
{ 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC },
{ 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
{}
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
View File

@ -77,7 +77,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
if (r022500 & 0x00000004)
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (r022500 & 0x00000008)
disable |= (1ULL << NVDEV_ENGINE_VENC);
disable |= (1ULL << NVDEV_ENGINE_MSENC);
if (r022500 & 0x00000100)
disable |= (1ULL << NVDEV_ENGINE_CE0);
if (r022500 & 0x00000200)