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mmc: sdhci-pci: Add support for Intel CNP 

Add PCI ids and enhanced strobe support for Intel CNP. This is combined
with GLK due to the pending CMDQ support which they both share.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Adrian Hunter 2017-06-01 12:10:07 +03:00 committed by Ulf Hansson
parent 87317c4d28
commit bc55dcd822
2 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/mmc/host/sdhci-pci-core.c
View File

@ -543,6 +543,23 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
} }
} }
#define INTEL_HS400_ES_REG 0x78
#define INTEL_HS400_ES_BIT BIT(0)
static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u32 val;
val = sdhci_readl(host, INTEL_HS400_ES_REG);
if (ios->enhanced_strobe)
val |= INTEL_HS400_ES_BIT;
else
val &= ~INTEL_HS400_ES_BIT;
sdhci_writel(host, val, INTEL_HS400_ES_REG);
}
static const struct sdhci_ops sdhci_intel_byt_ops = { static const struct sdhci_ops sdhci_intel_byt_ops = {
.set_clock = sdhci_set_clock, .set_clock = sdhci_set_clock,
.set_power = sdhci_intel_set_power, .set_power = sdhci_intel_set_power,
@ -579,6 +596,19 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
return 0; return 0;
} }
static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
int ret = byt_emmc_probe_slot(slot);
if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
slot->host->mmc_host_ops.hs400_enhanced_strobe =
intel_hs400_enhanced_strobe;
}
return ret;
}
#ifdef CONFIG_ACPI #ifdef CONFIG_ACPI
static int ni_set_max_freq(struct sdhci_pci_slot *slot) static int ni_set_max_freq(struct sdhci_pci_slot *slot)
{ {
@ -654,6 +684,17 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
.priv_size = sizeof(struct intel_host), .priv_size = sizeof(struct intel_host),
}; };
static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
.allow_runtime_pm = true,
.probe_slot = glk_emmc_probe_slot,
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
SDHCI_QUIRK2_STOP_WITH_TC,
.ops = &sdhci_intel_byt_ops,
.priv_size = sizeof(struct intel_host),
};
static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
.quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
@ -1225,9 +1266,12 @@ static const struct pci_device_id pci_ids[] = {
SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_byt_emmc), SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
SDHCI_PCI_DEVICE(O2, 8120, o2), SDHCI_PCI_DEVICE(O2, 8120, o2),
SDHCI_PCI_DEVICE(O2, 8220, o2), SDHCI_PCI_DEVICE(O2, 8220, o2),
SDHCI_PCI_DEVICE(O2, 8221, o2), SDHCI_PCI_DEVICE(O2, 8221, o2),

3
drivers/mmc/host/sdhci-pci.h
View File

@ -37,6 +37,9 @@
#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
#define PCI_DEVICE_ID_VIA_95D0 0x95d0 #define PCI_DEVICE_ID_VIA_95D0 0x95d0