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ARM: imx: pllv3 needs relock in .set_rate() call 

The pllv3 nees relock not only when powering up but also when rate
changes.  The patch creates a helper function clk_pllv3_wait_lock() and
moves the relock code from clk_pllv3_prepare() into there, so that
both .prepare() and .set_rate() hooks of pllv3 can call into the helper
for relocking.

Since relock is only needed when PLL is powered up while clk_set_rate()
could be called before clk is prepared, we need to add a check in
clk_pllv3_wait_lock() to skip the relock if PLL is not powered.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo 2013-10-30 15:56:22 +08:00
parent 322503a157
commit bc3b84da8a
1 changed files with 25 additions and 18 deletions
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43
arch/arm/mach-imx/clk-pllv3.c
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@ -46,10 +46,30 @@ struct clk_pllv3 {
#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
unsigned long timeout = jiffies + msecs_to_jiffies(10);
u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
/* No need to wait for lock when pll is not powered up */
if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
return 0;
/* Wait for PLL to lock */
do {
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
break;
if (time_after(jiffies, timeout))
break;
usleep_range(50, 500);
} while (1);
return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
}
static int clk_pllv3_prepare(struct clk_hw *hw) static int clk_pllv3_prepare(struct clk_hw *hw)
{ {
struct clk_pllv3 *pll = to_clk_pllv3(hw); struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long timeout;
u32 val; u32 val;
val = readl_relaxed(pll->base); val = readl_relaxed(pll->base);
@ -60,20 +80,7 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
val &= ~BM_PLL_POWER; val &= ~BM_PLL_POWER;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
timeout = jiffies + msecs_to_jiffies(10); return clk_pllv3_wait_lock(pll);
/* Wait for PLL to lock */
do {
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
break;
if (time_after(jiffies, timeout))
break;
usleep_range(50, 500);
} while (1);
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
return 0;
else
return -ETIMEDOUT;
} }
static void clk_pllv3_unprepare(struct clk_hw *hw) static void clk_pllv3_unprepare(struct clk_hw *hw)
@ -148,7 +155,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
val |= div; val |= div;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_ops = { static const struct clk_ops clk_pllv3_ops = {
@ -204,7 +211,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
val |= div; val |= div;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_sys_ops = { static const struct clk_ops clk_pllv3_sys_ops = {
@ -278,7 +285,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_av_ops = { static const struct clk_ops clk_pllv3_av_ops = {