Merge branch 'for-next/rng' into for-next/core
* for-next/rng: (2 commits) arm64: Use v8.5-RNG entropy for KASLR seed ...
This commit is contained in:
Will Deacon
commit
bc20606594
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@ -117,6 +117,8 @@ infrastructure:
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| RNDR | [63-60] | y |
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+------------------------------+---------+---------+
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| TS | [55-52] | y |
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+------------------------------+---------+---------+
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| FHM | [51-48] | y |
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@ -232,6 +232,10 @@ HWCAP2_DGH
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Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
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HWCAP2_RNG
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Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
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4. Unused AT_HWCAP bits
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-----------------------
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@ -1528,6 +1528,14 @@ config ARM64_E0PD
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This option enables E0PD for TTBR1 where available.
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config ARCH_RANDOM
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bool "Enable support for random number generation"
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default y
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help
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Random number generation (part of the ARMv8.5 Extensions)
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provides a high bandwidth, cryptographically secure
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hardware random number generator.
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endmenu
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config ARM64_SVE
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARCHRANDOM_H
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#define _ASM_ARCHRANDOM_H
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#ifdef CONFIG_ARCH_RANDOM
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#include <linux/random.h>
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#include <asm/cpufeature.h>
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static inline bool __arm64_rndr(unsigned long *v)
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{
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bool ok;
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/*
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* Reads of RNDR set PSTATE.NZCV to 0b0000 on success,
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* and set PSTATE.NZCV to 0b0100 otherwise.
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*/
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asm volatile(
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__mrs_s("%0", SYS_RNDR_EL0) "\n"
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" cset %w1, ne\n"
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: "=r" (*v), "=r" (ok)
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:
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: "cc");
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return ok;
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}
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static inline bool __must_check arch_get_random_long(unsigned long *v)
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{
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return false;
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}
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static inline bool __must_check arch_get_random_int(unsigned int *v)
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{
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return false;
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}
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static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
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{
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/*
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* Only support the generic interface after we have detected
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* the system wide capability, avoiding complexity with the
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* cpufeature code and with potential scheduling between CPUs
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* with and without the feature.
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*/
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if (!cpus_have_const_cap(ARM64_HAS_RNG))
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return false;
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return __arm64_rndr(v);
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}
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static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
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{
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unsigned long val;
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bool ok = arch_get_random_seed_long(&val);
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*v = val;
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return ok;
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}
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static inline bool __init __early_cpu_has_rndr(void)
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{
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/* Open code as we run prior to the first call to cpufeature. */
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unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1);
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return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf;
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}
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#else
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static inline bool __arm64_rndr(unsigned long *v) { return false; }
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static inline bool __init __early_cpu_has_rndr(void) { return false; }
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#endif /* CONFIG_ARCH_RANDOM */
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#endif /* _ASM_ARCHRANDOM_H */
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@ -57,7 +57,8 @@
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 48
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#define ARM64_HAS_E0PD 49
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#define ARM64_HAS_RNG 50
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#define ARM64_NCAPS 50
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#define ARM64_NCAPS 51
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#endif /* __ASM_CPUCAPS_H */
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@ -91,8 +91,9 @@
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#define KERNEL_HWCAP_SVEF64MM __khwcap2_feature(SVEF64MM)
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#define KERNEL_HWCAP_SVEBF16 __khwcap2_feature(SVEBF16)
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#define KERNEL_HWCAP_I8MM __khwcap2_feature(I8MM)
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#define KERNEL_HWCAP_DGH __khwcap2_feature(DGH)
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#define KERNEL_HWCAP_BF16 __khwcap2_feature(BF16)
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#define KERNEL_HWCAP_DGH __khwcap2_feature(DGH)
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#define KERNEL_HWCAP_RNG __khwcap2_feature(RNG)
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/*
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* This yields a mask that user programs can use to figure out what
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@ -366,6 +366,9 @@
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#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
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#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
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#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
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#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
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#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
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#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
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#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
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@ -552,6 +555,7 @@
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#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
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/* id_aa64isar0 */
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#define ID_AA64ISAR0_RNDR_SHIFT 60
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#define ID_AA64ISAR0_TS_SHIFT 52
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#define ID_AA64ISAR0_FHM_SHIFT 48
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#define ID_AA64ISAR0_DP_SHIFT 44
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@ -72,5 +72,6 @@
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#define HWCAP2_I8MM (1 << 13)
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#define HWCAP2_BF16 (1 << 14)
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#define HWCAP2_DGH (1 << 15)
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#define HWCAP2_RNG (1 << 16)
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -121,6 +121,7 @@ static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
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* sync with the documentation of the CPU feature register ABI.
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*/
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static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
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@ -1658,6 +1659,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.min_field_value = 1,
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.cpu_enable = cpu_enable_e0pd,
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},
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#endif
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#ifdef CONFIG_ARCH_RANDOM
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{
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.desc = "Random Number Generator",
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.capability = ARM64_HAS_RNG,
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_RNDR_SHIFT,
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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},
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#endif
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{},
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};
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@ -1736,6 +1749,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
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@ -91,6 +91,7 @@ static const char *const hwcap_str[] = {
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"i8mm",
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"bf16",
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"dgh",
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"rng",
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NULL
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};
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@ -120,6 +120,17 @@ u64 __init kaslr_early_init(u64 dt_phys)
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return 0;
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}
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/*
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* Mix in any entropy obtainable architecturally, open coded
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* since this runs extremely early.
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*/
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if (__early_cpu_has_rndr()) {
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unsigned long raw;
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if (__arm64_rndr(&raw))
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seed ^= raw;
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}
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if (!seed) {
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kaslr_status = KASLR_DISABLED_NO_SEED;
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return 0;
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