ath9k: merge noisefloor load implementations
AR5008+ and AR9003 currently use two separate implementations of the ath9k_hw_loadnf function. There are three main differences: - PHY registers for AR9003 are different - AR9003 always uses 3 chains, earlier versions are more selective - The AR9003 variant contains a fix for NF load timeouts This patch merges the two implementations into one, storing the register array in the ath_hw struct. The fix for NF load timeouts is not just relevant for AR9003, but also important for earlier hardware, so it's better to just keep one common implementation. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
b11b160def
commit
bbacee13f4
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@ -1516,77 +1516,6 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
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nfarray[5] = sign_extend(nf, 9);
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nfarray[5] = sign_extend(nf, 9);
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}
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}
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static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath9k_nfcal_hist *h;
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int i, j;
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int32_t val;
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const u32 ar5416_cca_regs[6] = {
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AR_PHY_CCA,
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AR_PHY_CH1_CCA,
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AR_PHY_CH2_CCA,
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AR_PHY_EXT_CCA,
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AR_PHY_CH1_EXT_CCA,
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AR_PHY_CH2_EXT_CCA
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};
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u8 chainmask, rx_chain_status;
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rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
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if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
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chainmask = 0x9;
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else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
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if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
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chainmask = 0x1B;
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else
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chainmask = 0x09;
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} else {
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if (rx_chain_status & 0x4)
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chainmask = 0x3F;
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else if (rx_chain_status & 0x2)
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chainmask = 0x1B;
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else
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chainmask = 0x09;
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}
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h = ah->nfCalHist;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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val = REG_READ(ah, ar5416_cca_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
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REG_WRITE(ah, ar5416_cca_regs[i], val);
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}
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}
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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for (j = 0; j < 5; j++) {
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if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_NF) == 0)
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break;
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udelay(50);
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}
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ENABLE_REGWRITE_BUFFER(ah);
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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val = REG_READ(ah, ar5416_cca_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (-50) << 1) & 0x1ff);
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REG_WRITE(ah, ar5416_cca_regs[i], val);
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}
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}
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REGWRITE_BUFFER_FLUSH(ah);
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DISABLE_REGWRITE_BUFFER(ah);
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}
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/*
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/*
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* Initialize the ANI register values with default (ini) values.
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* Initialize the ANI register values with default (ini) values.
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* This routine is called during a (full) hardware reset after
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* This routine is called during a (full) hardware reset after
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@ -1664,6 +1593,14 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
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void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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{
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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const u32 ar5416_cca_regs[6] = {
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AR_PHY_CCA,
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AR_PHY_CH1_CCA,
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AR_PHY_CH2_CCA,
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AR_PHY_EXT_CCA,
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AR_PHY_CH1_EXT_CCA,
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AR_PHY_CH2_EXT_CCA
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};
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priv_ops->rf_set_freq = ar5008_hw_set_channel;
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priv_ops->rf_set_freq = ar5008_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
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priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
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@ -1683,7 +1620,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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priv_ops->restore_chainmask = ar5008_restore_chainmask;
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priv_ops->restore_chainmask = ar5008_restore_chainmask;
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priv_ops->set_diversity = ar5008_set_diversity;
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priv_ops->set_diversity = ar5008_set_diversity;
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priv_ops->do_getnf = ar5008_hw_do_getnf;
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priv_ops->do_getnf = ar5008_hw_do_getnf;
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priv_ops->loadnf = ar5008_hw_loadnf;
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if (modparam_force_new_ani) {
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if (modparam_force_new_ani) {
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priv_ops->ani_control = ar5008_hw_ani_control_new;
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priv_ops->ani_control = ar5008_hw_ani_control_new;
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@ -1699,4 +1635,5 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
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priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
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ar5008_hw_set_nf_limits(ah);
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ar5008_hw_set_nf_limits(ah);
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memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
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}
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}
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@ -1049,106 +1049,6 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
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ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
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ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
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}
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}
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/*
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* Find out which of the RX chains are enabled
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*/
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static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
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{
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u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
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/*
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* The bits [2:0] indicate the rx chain mask and are to be
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* interpreted as follows:
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* 00x => Only chain 0 is enabled
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* 01x => Chain 1 and 0 enabled
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* 1xx => Chain 2,1 and 0 enabled
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*/
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return chain & 0x7;
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}
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static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath9k_nfcal_hist *h;
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unsigned i, j;
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int32_t val;
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const u32 ar9300_cca_regs[6] = {
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AR_PHY_CCA_0,
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AR_PHY_CCA_1,
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AR_PHY_CCA_2,
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AR_PHY_EXT_CCA,
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AR_PHY_EXT_CCA_1,
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AR_PHY_EXT_CCA_2,
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};
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u8 chainmask, rx_chain_status;
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struct ath_common *common = ath9k_hw_common(ah);
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rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
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chainmask = 0x3F;
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h = ah->nfCalHist;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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val = REG_READ(ah, ar9300_cca_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
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REG_WRITE(ah, ar9300_cca_regs[i], val);
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}
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}
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/*
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* Load software filtered NF value into baseband internal minCCApwr
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* variable.
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*/
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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/*
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* Wait for load to complete, should be fast, a few 10s of us.
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* The max delay was changed from an original 250us to 10000us
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* since 250us often results in NF load timeout and causes deaf
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* condition during stress testing 12/12/2009
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*/
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for (j = 0; j < 1000; j++) {
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if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_NF) == 0)
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break;
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udelay(10);
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}
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/*
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* We timed out waiting for the noisefloor to load, probably due to an
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* in-progress rx. Simply return here and allow the load plenty of time
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* to complete before the next calibration interval. We need to avoid
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* trying to load -50 (which happens below) while the previous load is
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* still in progress as this can cause rx deafness. Instead by returning
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* here, the baseband nf cal will just be capped by our present
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* noisefloor until the next calibration timer.
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*/
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if (j == 1000) {
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ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
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"to load: AR_PHY_AGC_CONTROL=0x%x\n",
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REG_READ(ah, AR_PHY_AGC_CONTROL));
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return;
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}
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/*
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* Restore maxCCAPower register parameter again so that we're not capped
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* by the median we just loaded. This will be initial (and max) value
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* of next noise floor calibration the baseband does.
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*/
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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val = REG_READ(ah, ar9300_cca_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (-50) << 1) & 0x1ff);
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REG_WRITE(ah, ar9300_cca_regs[i], val);
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}
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}
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}
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/*
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/*
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* Initialize the ANI register values with default (ini) values.
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* Initialize the ANI register values with default (ini) values.
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* This routine is called during a (full) hardware reset after
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* This routine is called during a (full) hardware reset after
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@ -1216,6 +1116,14 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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{
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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const u32 ar9300_cca_regs[6] = {
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AR_PHY_CCA_0,
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AR_PHY_CCA_1,
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AR_PHY_CCA_2,
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AR_PHY_EXT_CCA,
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AR_PHY_EXT_CCA_1,
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AR_PHY_EXT_CCA_2,
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};
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priv_ops->rf_set_freq = ar9003_hw_set_channel;
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priv_ops->rf_set_freq = ar9003_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
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priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
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@ -1232,10 +1140,10 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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priv_ops->set_diversity = ar9003_hw_set_diversity;
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priv_ops->set_diversity = ar9003_hw_set_diversity;
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priv_ops->ani_control = ar9003_hw_ani_control;
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priv_ops->ani_control = ar9003_hw_ani_control;
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priv_ops->do_getnf = ar9003_hw_do_getnf;
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priv_ops->do_getnf = ar9003_hw_do_getnf;
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priv_ops->loadnf = ar9003_hw_loadnf;
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priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
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priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
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ar9003_hw_set_nf_limits(ah);
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ar9003_hw_set_nf_limits(ah);
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memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
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}
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}
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void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
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void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
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@ -167,6 +167,100 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah)
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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}
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}
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void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath9k_nfcal_hist *h;
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unsigned i, j;
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int32_t val;
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u8 chainmask;
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struct ath_common *common = ath9k_hw_common(ah);
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if (AR_SREV_9300_20_OR_LATER(ah))
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chainmask = 0x3F;
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else if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
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chainmask = 0x9;
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else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
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if ((ah->rxchainmask & 0x2) || (ah->rxchainmask & 0x4))
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chainmask = 0x1B;
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else
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chainmask = 0x09;
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} else {
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if (ah->rxchainmask & 0x4)
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chainmask = 0x3F;
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else if (ah->rxchainmask & 0x2)
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chainmask = 0x1B;
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else
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chainmask = 0x09;
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}
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h = ah->nfCalHist;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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val = REG_READ(ah, ah->nf_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
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REG_WRITE(ah, ah->nf_regs[i], val);
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}
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}
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/*
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* Load software filtered NF value into baseband internal minCCApwr
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* variable.
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*/
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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/*
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* Wait for load to complete, should be fast, a few 10s of us.
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* The max delay was changed from an original 250us to 10000us
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* since 250us often results in NF load timeout and causes deaf
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* condition during stress testing 12/12/2009
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*/
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for (j = 0; j < 1000; j++) {
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if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_NF) == 0)
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break;
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udelay(10);
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}
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/*
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* We timed out waiting for the noisefloor to load, probably due to an
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* in-progress rx. Simply return here and allow the load plenty of time
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* to complete before the next calibration interval. We need to avoid
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* trying to load -50 (which happens below) while the previous load is
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* still in progress as this can cause rx deafness. Instead by returning
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* here, the baseband nf cal will just be capped by our present
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* noisefloor until the next calibration timer.
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*/
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|
if (j == 1000) {
|
||||||
|
ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
|
||||||
|
"to load: AR_PHY_AGC_CONTROL=0x%x\n",
|
||||||
|
REG_READ(ah, AR_PHY_AGC_CONTROL));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Restore maxCCAPower register parameter again so that we're not capped
|
||||||
|
* by the median we just loaded. This will be initial (and max) value
|
||||||
|
* of next noise floor calibration the baseband does.
|
||||||
|
*/
|
||||||
|
ENABLE_REGWRITE_BUFFER(ah);
|
||||||
|
for (i = 0; i < NUM_NF_READINGS; i++) {
|
||||||
|
if (chainmask & (1 << i)) {
|
||||||
|
val = REG_READ(ah, ah->nf_regs[i]);
|
||||||
|
val &= 0xFFFFFE00;
|
||||||
|
val |= (((u32) (-50) << 1) & 0x1ff);
|
||||||
|
REG_WRITE(ah, ah->nf_regs[i], val);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
REGWRITE_BUFFER_FLUSH(ah);
|
||||||
|
DISABLE_REGWRITE_BUFFER(ah);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
|
static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
|
||||||
{
|
{
|
||||||
struct ath_common *common = ath9k_hw_common(ah);
|
struct ath_common *common = ath9k_hw_common(ah);
|
||||||
|
|
|
@ -109,6 +109,7 @@ struct ath9k_pacal_info{
|
||||||
|
|
||||||
bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
|
bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
|
||||||
void ath9k_hw_start_nfcal(struct ath_hw *ah);
|
void ath9k_hw_start_nfcal(struct ath_hw *ah);
|
||||||
|
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
|
||||||
int16_t ath9k_hw_getnf(struct ath_hw *ah,
|
int16_t ath9k_hw_getnf(struct ath_hw *ah,
|
||||||
struct ath9k_channel *chan);
|
struct ath9k_channel *chan);
|
||||||
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
|
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
|
||||||
|
|
|
@ -264,12 +264,6 @@ static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
|
||||||
ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
|
ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ath9k_hw_loadnf(struct ath_hw *ah,
|
|
||||||
struct ath9k_channel *chan)
|
|
||||||
{
|
|
||||||
ath9k_hw_private_ops(ah)->loadnf(ah, chan);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
|
static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
|
||||||
struct ath9k_channel *chan)
|
struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
|
|
|
@ -510,7 +510,6 @@ struct ath_gen_timer_table {
|
||||||
* AR_RTC_PLL_CONTROL for a given channel
|
* AR_RTC_PLL_CONTROL for a given channel
|
||||||
* @setup_calibration: set up calibration
|
* @setup_calibration: set up calibration
|
||||||
* @iscal_supported: used to query if a type of calibration is supported
|
* @iscal_supported: used to query if a type of calibration is supported
|
||||||
* @loadnf: load noise floor read from each chain on the CCA registers
|
|
||||||
*
|
*
|
||||||
* @ani_reset: reset ANI parameters to default values
|
* @ani_reset: reset ANI parameters to default values
|
||||||
* @ani_lower_immunity: lower the noise immunity level. The level controls
|
* @ani_lower_immunity: lower the noise immunity level. The level controls
|
||||||
|
@ -564,7 +563,6 @@ struct ath_hw_private_ops {
|
||||||
bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
|
bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
|
||||||
int param);
|
int param);
|
||||||
void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
|
void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
|
||||||
void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
||||||
|
|
||||||
/* ANI */
|
/* ANI */
|
||||||
void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
|
void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
|
||||||
|
@ -658,6 +656,7 @@ struct ath_hw {
|
||||||
bool need_an_top2_fixup;
|
bool need_an_top2_fixup;
|
||||||
u16 tx_trig_level;
|
u16 tx_trig_level;
|
||||||
|
|
||||||
|
u32 nf_regs[6];
|
||||||
struct ath_nf_limits nf_2g;
|
struct ath_nf_limits nf_2g;
|
||||||
struct ath_nf_limits nf_5g;
|
struct ath_nf_limits nf_5g;
|
||||||
u16 rfsilent;
|
u16 rfsilent;
|
||||||
|
|
Loading…
Reference in New Issue