clk: qcom: Add Krait clock controller driver
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Stephen Boyd
Stephen Boyd
parent
40e5ddf4f8
commit
bb5c4a8505
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@ -292,3 +292,11 @@ config KPSS_XCC
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Support for the Krait ACC and GCC clock controllers. Say Y
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if you want to support CPU frequency scaling on devices such
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as MSM8960, APQ8064, etc.
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config KRAITCC
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tristate "Krait Clock Controller"
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depends on COMMON_CLK_QCOM && ARM
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select KRAIT_CLOCKS
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help
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Support for the Krait CPU clocks on Qualcomm devices.
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Say Y if you want to support CPU frequency scaling.
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@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
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obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
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obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
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obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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obj-$(CONFIG_KRAITCC) += krait-cc.o
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@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
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struct krait_mux_clk *mux = to_krait_mux_clk(hw);
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u32 sel;
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sel = clk_mux_reindex(index, mux->parent_map, 0);
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sel = clk_mux_index_to_val(mux->parent_map, 0, index);
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mux->en_mask = sel;
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/* Don't touch mux if CPU is off as it won't work */
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if (__clk_is_enabled(hw->clk))
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@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
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sel &= mux->mask;
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mux->en_mask = sel;
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return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
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return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
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}
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const struct clk_ops krait_mux_clk_ops = {
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@ -0,0 +1,341 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-krait.h"
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static unsigned int sec_mux_map[] = {
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2,
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0,
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};
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static unsigned int pri_mux_map[] = {
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1,
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2,
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0,
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};
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static int
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krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
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{
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struct krait_div2_clk *div;
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struct clk_init_data init = {
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.num_parents = 1,
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.ops = &krait_div2_clk_ops,
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.flags = CLK_SET_RATE_PARENT,
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};
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const char *p_names[1];
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struct clk *clk;
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div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
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if (!div)
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return -ENOMEM;
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div->width = 2;
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div->shift = 6;
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div->lpl = id >= 0;
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div->offset = offset;
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div->hw.init = &init;
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init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
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if (!init.name)
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return -ENOMEM;
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init.parent_names = p_names;
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p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
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if (!p_names[0]) {
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kfree(init.name);
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return -ENOMEM;
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}
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clk = devm_clk_register(dev, &div->hw);
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kfree(p_names[0]);
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kfree(init.name);
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return PTR_ERR_OR_ZERO(clk);
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}
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static int
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krait_add_sec_mux(struct device *dev, int id, const char *s,
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unsigned int offset, bool unique_aux)
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{
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struct krait_mux_clk *mux;
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static const char *sec_mux_list[] = {
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"acpu_aux",
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"qsb",
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};
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struct clk_init_data init = {
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.parent_names = sec_mux_list,
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.num_parents = ARRAY_SIZE(sec_mux_list),
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.ops = &krait_mux_clk_ops,
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.flags = CLK_SET_RATE_PARENT,
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};
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struct clk *clk;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return -ENOMEM;
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mux->offset = offset;
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mux->lpl = id >= 0;
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mux->mask = 0x3;
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mux->shift = 2;
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mux->parent_map = sec_mux_map;
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mux->hw.init = &init;
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init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
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if (!init.name)
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return -ENOMEM;
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if (unique_aux) {
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sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
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if (!sec_mux_list[0]) {
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clk = ERR_PTR(-ENOMEM);
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goto err_aux;
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}
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}
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clk = devm_clk_register(dev, &mux->hw);
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if (unique_aux)
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kfree(sec_mux_list[0]);
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err_aux:
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kfree(init.name);
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return PTR_ERR_OR_ZERO(clk);
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}
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static struct clk *
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krait_add_pri_mux(struct device *dev, int id, const char *s,
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unsigned int offset)
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{
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struct krait_mux_clk *mux;
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const char *p_names[3];
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struct clk_init_data init = {
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.parent_names = p_names,
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.num_parents = ARRAY_SIZE(p_names),
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.ops = &krait_mux_clk_ops,
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.flags = CLK_SET_RATE_PARENT,
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};
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struct clk *clk;
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->mask = 0x3;
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mux->shift = 0;
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mux->offset = offset;
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mux->lpl = id >= 0;
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mux->parent_map = pri_mux_map;
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mux->hw.init = &init;
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init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
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if (!init.name)
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return ERR_PTR(-ENOMEM);
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p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
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if (!p_names[0]) {
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clk = ERR_PTR(-ENOMEM);
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goto err_p0;
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}
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p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
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if (!p_names[1]) {
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clk = ERR_PTR(-ENOMEM);
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goto err_p1;
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}
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p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
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if (!p_names[2]) {
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clk = ERR_PTR(-ENOMEM);
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goto err_p2;
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}
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clk = devm_clk_register(dev, &mux->hw);
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kfree(p_names[2]);
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err_p2:
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kfree(p_names[1]);
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err_p1:
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kfree(p_names[0]);
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err_p0:
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kfree(init.name);
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return clk;
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}
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/* id < 0 for L2, otherwise id == physical CPU number */
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static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
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{
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int ret;
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unsigned int offset;
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void *p = NULL;
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const char *s;
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struct clk *clk;
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if (id >= 0) {
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offset = 0x4501 + (0x1000 * id);
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s = p = kasprintf(GFP_KERNEL, "%d", id);
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if (!s)
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return ERR_PTR(-ENOMEM);
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} else {
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offset = 0x500;
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s = "_l2";
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}
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ret = krait_add_div(dev, id, s, offset);
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if (ret) {
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clk = ERR_PTR(ret);
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goto err;
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}
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ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
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if (ret) {
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clk = ERR_PTR(ret);
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goto err;
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}
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clk = krait_add_pri_mux(dev, id, s, offset);
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err:
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kfree(p);
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return clk;
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}
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static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
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{
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unsigned int idx = clkspec->args[0];
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struct clk **clks = data;
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if (idx >= 5) {
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pr_err("%s: invalid clock index %d\n", __func__, idx);
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return ERR_PTR(-EINVAL);
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}
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return clks[idx] ? : ERR_PTR(-ENODEV);
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}
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static const struct of_device_id krait_cc_match_table[] = {
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{ .compatible = "qcom,krait-cc-v1", (void *)1UL },
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{ .compatible = "qcom,krait-cc-v2" },
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{}
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};
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MODULE_DEVICE_TABLE(of, krait_cc_match_table);
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static int krait_cc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *id;
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unsigned long cur_rate, aux_rate;
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int cpu;
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struct clk *clk;
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struct clk **clks;
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struct clk *l2_pri_mux_clk;
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id = of_match_device(krait_cc_match_table, dev);
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if (!id)
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return -ENODEV;
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/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
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clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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if (!id->data) {
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clk = clk_register_fixed_factor(dev, "acpu_aux",
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"gpll0_vote", 0, 1, 2);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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}
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/* Krait configurations have at most 4 CPUs and one L2 */
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clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
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if (!clks)
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return -ENOMEM;
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for_each_possible_cpu(cpu) {
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clk = krait_add_clks(dev, cpu, id->data);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clks[cpu] = clk;
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}
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l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
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if (IS_ERR(l2_pri_mux_clk))
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return PTR_ERR(l2_pri_mux_clk);
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clks[4] = l2_pri_mux_clk;
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/*
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* We don't want the CPU or L2 clocks to be turned off at late init
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* if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
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* refcount of these clocks. Any cpufreq/hotplug manager can assume
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* that the clocks have already been prepared and enabled by the time
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* they take over.
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*/
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for_each_online_cpu(cpu) {
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clk_prepare_enable(l2_pri_mux_clk);
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WARN(clk_prepare_enable(clks[cpu]),
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"Unable to turn on CPU%d clock", cpu);
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}
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/*
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* Force reinit of HFPLLs and muxes to overwrite any potential
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* incorrect configuration of HFPLLs and muxes by the bootloader.
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* While at it, also make sure the cores are running at known rates
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* and print the current rate.
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*
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* The clocks are set to aux clock rate first to make sure the
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* secondary mux is not sourcing off of QSB. The rate is then set to
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* two different rates to force a HFPLL reinit under all
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* circumstances.
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*/
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cur_rate = clk_get_rate(l2_pri_mux_clk);
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aux_rate = 384000000;
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if (cur_rate == 1) {
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pr_info("L2 @ QSB rate. Forcing new rate.\n");
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cur_rate = aux_rate;
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}
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clk_set_rate(l2_pri_mux_clk, aux_rate);
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clk_set_rate(l2_pri_mux_clk, 2);
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clk_set_rate(l2_pri_mux_clk, cur_rate);
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pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
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for_each_possible_cpu(cpu) {
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clk = clks[cpu];
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cur_rate = clk_get_rate(clk);
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if (cur_rate == 1) {
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pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
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cur_rate = aux_rate;
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}
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clk_set_rate(clk, aux_rate);
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clk_set_rate(clk, 2);
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clk_set_rate(clk, cur_rate);
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pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
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}
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of_clk_add_provider(dev->of_node, krait_of_get, clks);
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return 0;
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}
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static struct platform_driver krait_cc_driver = {
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.probe = krait_cc_probe,
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.driver = {
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.name = "krait-cc",
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.of_match_table = krait_cc_match_table,
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},
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};
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module_platform_driver(krait_cc_driver);
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MODULE_DESCRIPTION("Krait CPU Clock Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:krait-cc");
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