A bit of attention for the rk3066, fixed tsadc reset node
as well as enabling the dma for uart and mmc controllers. And one new soc, the rk1108 combining a single-core Cortex-A7 with a separate DSP core. -----BEGIN PGP SIGNATURE----- iQEtBAABCAAXBQJYNj8LEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYE3oggA j0b99/r3uGOavo9nun2yJTqq/bKhjAAupNhrEJtjKP9gdbR/1HOkjzRX/1g9ID36 b5cMpOePpRN9xCg0IyK4/+0jgXJ1r41Fp1yEI51Z57jlo0WMzP10/E8hGwNQgW7Q QSAPrTZbwLcrDjq7cOHrF8WvuMnA+6ye77IcDFJ0ZjtU7PYwfO63VTIJ/37Ph3FE wlDb0YH57nrn13qUlK8UDJJysl1v2H8NP48/5qEfgF/swbyt6VKkaL2Q+Ua2aDys AaH2oTRUPBSPqqXj78OKrWfHB8U5WWfn7PvDYxyjYcnOnasvE7kEBlmw4P955QDM XzEEXkiEcQFMLoEiWim5Xw== =2VYn -----END PGP SIGNATURE----- Merge tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "Rockchip dts32 changes for 4.10" from Heiko Stübner: A bit of attention for the rk3066, fixed tsadc reset node as well as enabling the dma for uart and mmc controllers. And one new soc, the rk1108 combining a single-core Cortex-A7 with a separate DSP core. * tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108 ARM: dts: rockchip: add rockchip RK1108 Evaluation board ARM: dts: rockchip: add basic support for RK1108 SOC clk: rockchip: add dt-binding header for rk1108 dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description ARM: dts: rockchip: enable dma for uart and mmc on rk3066a ARM: dts: rockchip: fix TSADC reset node for rk3066a
This commit is contained in:
Arnd Bergmann
commit
bb2d850778
|
|
@ -13,6 +13,7 @@ Required Properties:
|
|||
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
|
||||
before RK3288
|
||||
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
|
||||
- "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
|
||||
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
|
||||
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
|
||||
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
|
||||
|
|
|
|||
|
|
@ -656,6 +656,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
|
|||
arm-realview-pba8.dtb \
|
||||
arm-realview-pbx-a9.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk1108-evb.dtb \
|
||||
rk3036-evb.dtb \
|
||||
rk3036-kylin.dtb \
|
||||
rk3066a-bqcurie2.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk1108.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK1108 Evaluation board";
|
||||
compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,452 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/rk1108-cru.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "rockchip,rk1108";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@f00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf00>;
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@102a0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x102a0000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
clocks = <&cru ACLK_DMAC>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
bus_intmem@10080000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x10080000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x10080000 0x2000>;
|
||||
};
|
||||
|
||||
uart2: serial@10210000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10210000 0x100>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10220000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10220000 0x100>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10230000 {
|
||||
compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10230000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
grf: syscon@10300000 {
|
||||
compatible = "rockchip,rk1108-grf", "syscon";
|
||||
reg = <0x10300000 0x1000>;
|
||||
};
|
||||
|
||||
pmugrf: syscon@20060000 {
|
||||
compatible = "rockchip,rk1108-pmugrf", "syscon";
|
||||
reg = <0x20060000 0x1000>;
|
||||
};
|
||||
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rk1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
emmc: dwmmc@30110000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x30110000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio: dwmmc@30120000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x30120000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc: dwmmc@30130000 {
|
||||
compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
clock-freq-min-max = <400000 100000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x30130000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@32010000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x32011000 0x1000>,
|
||||
<0x32012000 0x1000>,
|
||||
<0x32014000 0x2000>,
|
||||
<0x32016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk1108-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmugrf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@20030000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20030000 0x100>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@10310000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10310000 0x100>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@10320000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10320000 0x100>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@10330000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10330000 0x100>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
pcfg_input_high: pcfg-input-high {
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2m1 {
|
||||
i2c2m1_xfer: i2c2m1-xfer {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2c2m1_gpio: i2c2m1-gpio {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2m05v {
|
||||
i2c2m05v_xfer: i2c2m05v-xfer {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2c2m05v_gpio: i2c2m05v-gpio {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmmc-cd {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts_gpio: uart0-rts-gpio {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m0 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m1 {
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_5v {
|
||||
uart2_5v_cts: uart2_5v-cts {
|
||||
rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_5v_rts: uart2_5v-rts {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -205,7 +205,7 @@
|
|||
clock-names = "saradc", "apb_pclk";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#io-channel-cells = <1>;
|
||||
resets = <&cru SRST_SARADC>;
|
||||
resets = <&cru SRST_TSADC>;
|
||||
reset-names = "saradc-apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -637,16 +637,25 @@
|
|||
|
||||
&mmc0 {
|
||||
clock-frequency = <50000000>;
|
||||
dmas = <&dmac2 1>;
|
||||
dma-names = "rx-tx";
|
||||
max-frequency = <50000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
dmas = <&dmac2 3>;
|
||||
dma-names = "rx-tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
dmas = <&dmac2 4>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_out>;
|
||||
|
|
@ -678,21 +687,29 @@
|
|||
};
|
||||
|
||||
&uart0 {
|
||||
dmas = <&dmac1_s 0>, <&dmac1_s 1>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
dmas = <&dmac1_s 2>, <&dmac1_s 3>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
dmas = <&dmac2 6>, <&dmac2 7>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
dmas = <&dmac2 8>, <&dmac2 9>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_xfer>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
|
||||
* Author: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
|
||||
|
||||
/* pll id */
|
||||
#define PLL_APLL 0
|
||||
#define PLL_DPLL 1
|
||||
#define PLL_GPLL 2
|
||||
#define ARMCLK 3
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_UART0 72
|
||||
#define SCLK_UART1 73
|
||||
#define SCLK_UART2 74
|
||||
#define SCLK_I2S0 75
|
||||
#define SCLK_I2S1 76
|
||||
#define SCLK_I2S2 77
|
||||
#define SCLK_TIMER0 78
|
||||
#define SCLK_TIMER1 79
|
||||
#define SCLK_SFC 80
|
||||
#define SCLK_SDMMC_DRV 81
|
||||
#define SCLK_SDIO_DRV 82
|
||||
#define SCLK_EMMC_DRV 83
|
||||
#define SCLK_SDMMC_SAMPLE 84
|
||||
#define SCLK_SDIO_SAMPLE 85
|
||||
#define SCLK_EMMC_SAMPLE 86
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 192
|
||||
#define ACLK_PRE 193
|
||||
#define ACLK_CORE 194
|
||||
#define ACLK_ENMCORE 195
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO1 256
|
||||
#define PCLK_GPIO2 257
|
||||
#define PCLK_GPIO3 258
|
||||
#define PCLK_GRF 259
|
||||
#define PCLK_I2C1 260
|
||||
#define PCLK_I2C2 261
|
||||
#define PCLK_I2C3 262
|
||||
#define PCLK_SPI 263
|
||||
#define PCLK_SFC 264
|
||||
#define PCLK_UART0 265
|
||||
#define PCLK_UART1 266
|
||||
#define PCLK_UART2 267
|
||||
#define PCLK_TSADC 268
|
||||
#define PCLK_PWM 269
|
||||
#define PCLK_TIMER 270
|
||||
#define PCLK_PERI 271
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 320
|
||||
#define HCLK_I2S1_8CH 321
|
||||
#define HCLK_I2S2_2CH 322
|
||||
#define HCLK_NANDC 323
|
||||
#define HCLK_SDMMC 324
|
||||
#define HCLK_SDIO 325
|
||||
#define HCLK_EMMC 326
|
||||
#define HCLK_PERI 327
|
||||
#define HCLK_SFC 328
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SFC + 1)
|
||||
|
||||
/* reset id */
|
||||
#define SRST_CORE_PO_AD 0
|
||||
#define SRST_CORE_AD 1
|
||||
#define SRST_L2_AD 2
|
||||
#define SRST_CPU_NIU_AD 3
|
||||
#define SRST_CORE_PO 4
|
||||
#define SRST_CORE 5
|
||||
#define SRST_L2 6
|
||||
#define SRST_CORE_DBG 8
|
||||
#define PRST_DBG 9
|
||||
#define RST_DAP 10
|
||||
#define PRST_DBG_NIU 11
|
||||
#define ARST_STRC_SYS_AD 15
|
||||
|
||||
#define SRST_DDRPHY_CLKDIV 16
|
||||
#define SRST_DDRPHY 17
|
||||
#define PRST_DDRPHY 18
|
||||
#define PRST_HDMIPHY 19
|
||||
#define PRST_VDACPHY 20
|
||||
#define PRST_VADCPHY 21
|
||||
#define PRST_MIPI_CSI_PHY 22
|
||||
#define PRST_MIPI_DSI_PHY 23
|
||||
#define PRST_ACODEC 24
|
||||
#define ARST_BUS_NIU 25
|
||||
#define PRST_TOP_NIU 26
|
||||
#define ARST_INTMEM 27
|
||||
#define HRST_ROM 28
|
||||
#define ARST_DMAC 29
|
||||
#define SRST_MSCH_NIU 30
|
||||
#define PRST_MSCH_NIU 31
|
||||
|
||||
#define PRST_DDRUPCTL 32
|
||||
#define NRST_DDRUPCTL 33
|
||||
#define PRST_DDRMON 34
|
||||
#define HRST_I2S0_8CH 35
|
||||
#define MRST_I2S0_8CH 36
|
||||
#define HRST_I2S1_2CH 37
|
||||
#define MRST_IS21_2CH 38
|
||||
#define HRST_I2S2_2CH 39
|
||||
#define MRST_I2S2_2CH 40
|
||||
#define HRST_CRYPTO 41
|
||||
#define SRST_CRYPTO 42
|
||||
#define PRST_SPI 43
|
||||
#define SRST_SPI 44
|
||||
#define PRST_UART0 45
|
||||
#define PRST_UART1 46
|
||||
#define PRST_UART2 47
|
||||
|
||||
#define SRST_UART0 48
|
||||
#define SRST_UART1 49
|
||||
#define SRST_UART2 50
|
||||
#define PRST_I2C1 51
|
||||
#define PRST_I2C2 52
|
||||
#define PRST_I2C3 53
|
||||
#define SRST_I2C1 54
|
||||
#define SRST_I2C2 55
|
||||
#define SRST_I2C3 56
|
||||
#define PRST_PWM1 58
|
||||
#define SRST_PWM1 60
|
||||
#define PRST_WDT 61
|
||||
#define PRST_GPIO1 62
|
||||
#define PRST_GPIO2 63
|
||||
|
||||
#define PRST_GPIO3 64
|
||||
#define PRST_GRF 65
|
||||
#define PRST_EFUSE 66
|
||||
#define PRST_EFUSE512 67
|
||||
#define PRST_TIMER0 68
|
||||
#define SRST_TIMER0 69
|
||||
#define SRST_TIMER1 70
|
||||
#define PRST_TSADC 71
|
||||
#define SRST_TSADC 72
|
||||
#define PRST_SARADC 73
|
||||
#define SRST_SARADC 74
|
||||
#define HRST_SYSBUS 75
|
||||
#define PRST_USBGRF 76
|
||||
|
||||
#define ARST_PERIPH_NIU 80
|
||||
#define HRST_PERIPH_NIU 81
|
||||
#define PRST_PERIPH_NIU 82
|
||||
#define HRST_PERIPH 83
|
||||
#define HRST_SDMMC 84
|
||||
#define HRST_SDIO 85
|
||||
#define HRST_EMMC 86
|
||||
#define HRST_NANDC 87
|
||||
#define NRST_NANDC 88
|
||||
#define HRST_SFC 89
|
||||
#define SRST_SFC 90
|
||||
#define ARST_GMAC 91
|
||||
#define HRST_OTG 92
|
||||
#define SRST_OTG 93
|
||||
#define SRST_OTG_ADP 94
|
||||
#define HRST_HOST0 95
|
||||
|
||||
#define HRST_HOST0_AUX 96
|
||||
#define HRST_HOST0_ARB 97
|
||||
#define SRST_HOST0_EHCIPHY 98
|
||||
#define SRST_HOST0_UTMI 99
|
||||
#define SRST_USBPOR 100
|
||||
#define SRST_UTMI0 101
|
||||
#define SRST_UTMI1 102
|
||||
|
||||
#define ARST_VIO0_NIU 102
|
||||
#define ARST_VIO1_NIU 103
|
||||
#define HRST_VIO_NIU 104
|
||||
#define PRST_VIO_NIU 105
|
||||
#define ARST_VOP 106
|
||||
#define HRST_VOP 107
|
||||
#define DRST_VOP 108
|
||||
#define ARST_IEP 109
|
||||
#define HRST_IEP 110
|
||||
#define ARST_RGA 111
|
||||
#define HRST_RGA 112
|
||||
#define SRST_RGA 113
|
||||
#define PRST_CVBS 114
|
||||
#define PRST_HDMI 115
|
||||
#define SRST_HDMI 116
|
||||
#define PRST_MIPI_DSI 117
|
||||
|
||||
#define ARST_ISP_NIU 118
|
||||
#define HRST_ISP_NIU 119
|
||||
#define HRST_ISP 120
|
||||
#define SRST_ISP 121
|
||||
#define ARST_VIP0 122
|
||||
#define HRST_VIP0 123
|
||||
#define PRST_VIP0 124
|
||||
#define ARST_VIP1 125
|
||||
#define HRST_VIP1 126
|
||||
#define PRST_VIP1 127
|
||||
#define ARST_VIP2 128
|
||||
#define HRST_VIP2 129
|
||||
#define PRST_VIP2 120
|
||||
#define ARST_VIP3 121
|
||||
#define HRST_VIP3 122
|
||||
#define PRST_VIP4 123
|
||||
|
||||
#define PRST_CIF1TO4 124
|
||||
#define SRST_CVBS_CLK 125
|
||||
#define HRST_CVBS 126
|
||||
|
||||
#define ARST_VPU_NIU 140
|
||||
#define HRST_VPU_NIU 141
|
||||
#define ARST_VPU 142
|
||||
#define HRST_VPU 143
|
||||
#define ARST_RKVDEC_NIU 144
|
||||
#define HRST_RKVDEC_NIU 145
|
||||
#define ARST_RKVDEC 146
|
||||
#define HRST_RKVDEC 147
|
||||
#define SRST_RKVDEC_CABAC 148
|
||||
#define SRST_RKVDEC_CORE 149
|
||||
#define ARST_RKVENC_NIU 150
|
||||
#define HRST_RKVENC_NIU 151
|
||||
#define ARST_RKVENC 152
|
||||
#define HRST_RKVENC 153
|
||||
#define SRST_RKVENC_CORE 154
|
||||
|
||||
#define SRST_DSP_CORE 156
|
||||
#define SRST_DSP_SYS 157
|
||||
#define SRST_DSP_GLOBAL 158
|
||||
#define SRST_DSP_OECM 159
|
||||
#define PRST_DSP_IOP_NIU 160
|
||||
#define ARST_DSP_EPP_NIU 161
|
||||
#define ARST_DSP_EDP_NIU 162
|
||||
#define PRST_DSP_DBG_NIU 163
|
||||
#define PRST_DSP_CFG_NIU 164
|
||||
#define PRST_DSP_GRF 165
|
||||
#define PRST_DSP_MAILBOX 166
|
||||
#define PRST_DSP_INTC 167
|
||||
#define PRST_DSP_PFM_MON 169
|
||||
#define SRST_DSP_PFM_MON 170
|
||||
#define ARST_DSP_EDAP_NIU 171
|
||||
|
||||
#define SRST_PMU 172
|
||||
#define SRST_PMU_I2C0 173
|
||||
#define PRST_PMU_I2C0 174
|
||||
#define PRST_PMU_GPIO0 175
|
||||
#define PRST_PMU_INTMEM 176
|
||||
#define PRST_PMU_PWM0 177
|
||||
#define SRST_PMU_PWM0 178
|
||||
#define PRST_PMU_GRF 179
|
||||
#define SRST_PMU_NIU 180
|
||||
#define SRST_PMU_PVTM 181
|
||||
#define ARST_DSP_EDP_PERF 184
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#define ARST_DSP_EPP_PERF 185
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||||
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||||
#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */
|
||||
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Reference in New Issue