powerpc/book3e-64: Add support to initial_tlb_book3e for non-HES TLB
We now search through TLBnCFG looking for the first array that has IPROT support (we assume that there is only one). If that TLB has hardware entry select (HES) support we use the existing code and with the proper TLB select (the HES code still needs to clean up bolted entries from firmware). The non-HES code is pretty similiar to the 32-bit FSL Book-E code but does make some new assumtions (like that we have tlbilx) and simplifies things down a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Benjamin Herrenschmidt
parent
4b98d9e713
commit
bb1af71ecb
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@ -108,6 +108,8 @@
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#define SPRN_PID2 0x27A /* Process ID Register 2 */
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
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#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */
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#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */
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#define SPRN_EPR 0x2BE /* External Proxy Register */
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#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
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#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
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@ -616,18 +616,214 @@ bad_stack_book3e:
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* Setup the initial TLB for a core. This current implementation
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* assume that whatever we are running off will not conflict with
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* the new mapping at PAGE_OFFSET.
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* We also make various assumptions about the processor we run on,
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* this might have to be made more flexible based on the content
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* of MMUCFG and friends.
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*/
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_GLOBAL(initial_tlb_book3e)
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/* Look for the first TLB with IPROT set */
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mfspr r4,SPRN_TLB0CFG
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andi. r3,r4,TLBnCFG_IPROT
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lis r3,MAS0_TLBSEL(0)@h
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bne found_iprot
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mfspr r4,SPRN_TLB1CFG
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andi. r3,r4,TLBnCFG_IPROT
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lis r3,MAS0_TLBSEL(1)@h
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bne found_iprot
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mfspr r4,SPRN_TLB2CFG
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andi. r3,r4,TLBnCFG_IPROT
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lis r3,MAS0_TLBSEL(2)@h
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bne found_iprot
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lis r3,MAS0_TLBSEL(3)@h
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mfspr r4,SPRN_TLB3CFG
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/* fall through */
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found_iprot:
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andi. r5,r4,TLBnCFG_HES
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bne have_hes
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mflr r8 /* save LR */
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/* 1. Find the index of the entry we're executing in
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*
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* r3 = MAS0_TLBSEL (for the iprot array)
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* r4 = SPRN_TLBnCFG
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*/
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bl invstr /* Find our address */
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invstr: mflr r6 /* Make it accessible */
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mfmsr r7
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rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
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mfspr r7,SPRN_PID
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slwi r7,r7,16
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or r7,r7,r5
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mtspr SPRN_MAS6,r7
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tlbsx 0,r6 /* search MSR[IS], SPID=PID */
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mfspr r3,SPRN_MAS0
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rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
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mfspr r7,SPRN_MAS1 /* Insure IPROT set */
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oris r7,r7,MAS1_IPROT@h
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mtspr SPRN_MAS1,r7
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tlbwe
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/* 2. Invalidate all entries except the entry we're executing in
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*
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* r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
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* r4 = SPRN_TLBnCFG
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* r5 = ESEL of entry we are running in
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*/
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andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
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li r6,0 /* Set Entry counter to 0 */
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1: mr r7,r3 /* Set MAS0(TLBSEL) */
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rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
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mtspr SPRN_MAS0,r7
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tlbre
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mfspr r7,SPRN_MAS1
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rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
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cmpw r5,r6
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beq skpinv /* Dont update the current execution TLB */
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mtspr SPRN_MAS1,r7
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tlbwe
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isync
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skpinv: addi r6,r6,1 /* Increment */
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cmpw r6,r4 /* Are we done? */
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bne 1b /* If not, repeat */
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/* Invalidate all TLBs */
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PPC_TLBILX_ALL(0,0)
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sync
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isync
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/* 3. Setup a temp mapping and jump to it
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*
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* r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
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* r5 = ESEL of entry we are running in
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*/
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andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
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addi r7,r7,0x1
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mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
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mtspr SPRN_MAS0,r4
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tlbre
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rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
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mtspr SPRN_MAS0,r4
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mfspr r7,SPRN_MAS1
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xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
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mtspr SPRN_MAS1,r6
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tlbwe
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mfmsr r6
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xori r6,r6,MSR_IS
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mtspr SPRN_SRR1,r6
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bl 1f /* Find our address */
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1: mflr r6
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addi r6,r6,(2f - 1b)
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mtspr SPRN_SRR0,r6
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rfi
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2:
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/* 4. Clear out PIDs & Search info
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*
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* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
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* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
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* r5 = MAS3
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*/
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li r6,0
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mtspr SPRN_MAS6,r6
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mtspr SPRN_PID,r6
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/* 5. Invalidate mapping we started in
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*
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* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
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* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
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* r5 = MAS3
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*/
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mtspr SPRN_MAS0,r3
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tlbre
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mfspr r6,SPRN_MAS1
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rlwinm r6,r6,0,2,0 /* clear IPROT */
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mtspr SPRN_MAS1,r6
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tlbwe
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/* Invalidate TLB1 */
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PPC_TLBILX_ALL(0,0)
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sync
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isync
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/* The mapping only needs to be cache-coherent on SMP */
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#ifdef CONFIG_SMP
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#define M_IF_SMP MAS2_M
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#else
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#define M_IF_SMP 0
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#endif
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/* 6. Setup KERNELBASE mapping in TLB[0]
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*
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* r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
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* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
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* r5 = MAS3
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*/
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rlwinm r3,r3,0,16,3 /* clear ESEL */
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mtspr SPRN_MAS0,r3
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lis r6,(MAS1_VALID|MAS1_IPROT)@h
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ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
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mtspr SPRN_MAS1,r6
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LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
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mtspr SPRN_MAS2,r6
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rlwinm r5,r5,0,0,25
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ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
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mtspr SPRN_MAS3,r5
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li r5,-1
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rlwinm r5,r5,0,0,25
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tlbwe
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/* 7. Jump to KERNELBASE mapping
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*
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* r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
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*/
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/* Now we branch the new virtual address mapped by this entry */
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LOAD_REG_IMMEDIATE(r6,2f)
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lis r7,MSR_KERNEL@h
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ori r7,r7,MSR_KERNEL@l
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mtspr SPRN_SRR0,r6
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mtspr SPRN_SRR1,r7
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rfi /* start execution out of TLB1[0] entry */
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2:
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/* 8. Clear out the temp mapping
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*
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* r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
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*/
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mtspr SPRN_MAS0,r4
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tlbre
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mfspr r5,SPRN_MAS1
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rlwinm r5,r5,0,2,0 /* clear IPROT */
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mtspr SPRN_MAS1,r5
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tlbwe
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/* Invalidate TLB1 */
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PPC_TLBILX_ALL(0,0)
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sync
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isync
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/* We translate LR and return */
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tovirt(r8,r8)
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mtlr r8
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blr
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have_hes:
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/* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
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* kernel linear mapping. We also set MAS8 once for all here though
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* that will have to be made dependent on whether we are running under
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* a hypervisor I suppose.
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*/
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li r3,MAS0_HES | MAS0_WQ_ALLWAYS
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ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
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mtspr SPRN_MAS0,r3
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lis r3,(MAS1_VALID | MAS1_IPROT)@h
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ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
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