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powerpc/mm/radix: Fix CONFIG_PPC_MMU_STD_64 typo 

It's CONFIG_PPC_STD_MMU_64 not ...
     CONFIG_PPC_MMU_STD_64.

Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code")
Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Valentin Rothberg 2016-05-03 08:59:27 +02:00 committed by Michael Ellerman
parent 69dfbaeb65
commit bb03efe2b7
1 changed files with 5 additions and 5 deletions
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10
arch/powerpc/kernel/mce_power.c
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@ -80,7 +80,7 @@ void __flush_tlb_power9(unsigned int action)
/* flush SLBs and reload */ /* flush SLBs and reload */
#ifdef CONFIG_PPC_MMU_STD_64 #ifdef CONFIG_PPC_STD_MMU_64
static void flush_and_reload_slb(void) static void flush_and_reload_slb(void)
{ {
struct slb_shadow *slb; struct slb_shadow *slb;
@ -125,7 +125,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
* reset the error bits whenever we handle them so that at the end * reset the error bits whenever we handle them so that at the end
* we can check whether we handled all of them or not. * we can check whether we handled all of them or not.
* */ * */
#ifdef CONFIG_PPC_MMU_STD_64 #ifdef CONFIG_PPC_STD_MMU_64
if (dsisr & slb_error_bits) { if (dsisr & slb_error_bits) {
flush_and_reload_slb(); flush_and_reload_slb();
/* reset error bits */ /* reset error bits */
@ -157,7 +157,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
switch (P7_SRR1_MC_IFETCH(srr1)) { switch (P7_SRR1_MC_IFETCH(srr1)) {
case 0: case 0:
break; break;
#ifdef CONFIG_PPC_MMU_STD_64 #ifdef CONFIG_PPC_STD_MMU_64
case P7_SRR1_MC_IFETCH_SLB_PARITY: case P7_SRR1_MC_IFETCH_SLB_PARITY:
case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
/* flush and reload SLBs for SLB errors. */ /* flush and reload SLBs for SLB errors. */
@ -184,7 +184,7 @@ static long mce_handle_ierror_p7(uint64_t srr1)
handled = mce_handle_common_ierror(srr1); handled = mce_handle_common_ierror(srr1);
#ifdef CONFIG_PPC_MMU_STD_64 #ifdef CONFIG_PPC_STD_MMU_64
if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
flush_and_reload_slb(); flush_and_reload_slb();
handled = 1; handled = 1;
@ -332,7 +332,7 @@ static long mce_handle_ierror_p8(uint64_t srr1)
handled = mce_handle_common_ierror(srr1); handled = mce_handle_common_ierror(srr1);
#ifdef CONFIG_PPC_MMU_STD_64 #ifdef CONFIG_PPC_STD_MMU_64
if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
flush_and_reload_slb(); flush_and_reload_slb();
handled = 1; handled = 1;