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ARM: EXYNOS4: Add clkdev support 

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[kgene.kim@samsung.com: removed changes of mach-exynos4/time.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Thomas Abraham 2011-06-14 19:12:27 +09:00 committed by Kukjin Kim
parent b2a9dd466c
commit badc4f2d60
2 changed files with 58 additions and 120 deletions
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1
arch/arm/Kconfig
View File

@ -772,6 +772,7 @@ config ARCH_EXYNOS4
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS

177
arch/arm/mach-exynos4/clock.c
View File

@ -27,24 +27,20 @@
static struct clk clk_sclk_hdmi27m = { static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m", .name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_hdmiphy = { static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy", .name = "sclk_hdmiphy",
.id = -1,
}; };
static struct clk clk_sclk_usbphy0 = { static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0", .name = "sclk_usbphy0",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_usbphy1 = { static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1", .name = "sclk_usbphy1",
.id = -1,
}; };
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.sources = &clk_src_apll, .sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_sclk_apll = { static struct clksrc_clk clk_sclk_apll = {
.clk = { .clk = {
.name = "sclk_apll", .name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.sources = &clk_src_epll, .sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
static struct clksrc_clk clk_moutcore = { static struct clksrc_clk clk_moutcore = {
.clk = { .clk = {
.name = "moutcore", .name = "moutcore",
.id = -1,
}, },
.sources = &clkset_moutcore, .sources = &clkset_moutcore,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
static struct clksrc_clk clk_coreclk = { static struct clksrc_clk clk_coreclk = {
.clk = { .clk = {
.name = "core_clk", .name = "core_clk",
.id = -1,
.parent = &clk_moutcore.clk, .parent = &clk_moutcore.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_armclk = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
}; };
@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_aclk_corem0 = { static struct clksrc_clk clk_aclk_corem0 = {
.clk = { .clk = {
.name = "aclk_corem0", .name = "aclk_corem0",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
static struct clksrc_clk clk_aclk_cores = { static struct clksrc_clk clk_aclk_cores = {
.clk = { .clk = {
.name = "aclk_cores", .name = "aclk_cores",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
static struct clksrc_clk clk_aclk_corem1 = { static struct clksrc_clk clk_aclk_corem1 = {
.clk = { .clk = {
.name = "aclk_corem1", .name = "aclk_corem1",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
static struct clksrc_clk clk_periphclk = { static struct clksrc_clk clk_periphclk = {
.clk = { .clk = {
.name = "periphclk", .name = "periphclk",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
static struct clksrc_clk clk_mout_corebus = { static struct clksrc_clk clk_mout_corebus = {
.clk = { .clk = {
.name = "mout_corebus", .name = "mout_corebus",
.id = -1,
}, },
.sources = &clkset_mout_corebus, .sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
static struct clksrc_clk clk_sclk_dmc = { static struct clksrc_clk clk_sclk_dmc = {
.clk = { .clk = {
.name = "sclk_dmc", .name = "sclk_dmc",
.id = -1,
.parent = &clk_mout_corebus.clk, .parent = &clk_mout_corebus.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clksrc_clk clk_aclk_cored = { static struct clksrc_clk clk_aclk_cored = {
.clk = { .clk = {
.name = "aclk_cored", .name = "aclk_cored",
.id = -1,
.parent = &clk_sclk_dmc.clk, .parent = &clk_sclk_dmc.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
static struct clksrc_clk clk_aclk_corep = { static struct clksrc_clk clk_aclk_corep = {
.clk = { .clk = {
.name = "aclk_corep", .name = "aclk_corep",
.id = -1,
.parent = &clk_aclk_cored.clk, .parent = &clk_aclk_cored.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
static struct clksrc_clk clk_aclk_acp = { static struct clksrc_clk clk_aclk_acp = {
.clk = { .clk = {
.name = "aclk_acp", .name = "aclk_acp",
.id = -1,
.parent = &clk_mout_corebus.clk, .parent = &clk_mout_corebus.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
static struct clksrc_clk clk_pclk_acp = { static struct clksrc_clk clk_pclk_acp = {
.clk = { .clk = {
.name = "pclk_acp", .name = "pclk_acp",
.id = -1,
.parent = &clk_aclk_acp.clk, .parent = &clk_aclk_acp.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
static struct clksrc_clk clk_aclk_200 = { static struct clksrc_clk clk_aclk_200 = {
.clk = { .clk = {
.name = "aclk_200", .name = "aclk_200",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
static struct clksrc_clk clk_aclk_100 = { static struct clksrc_clk clk_aclk_100 = {
.clk = { .clk = {
.name = "aclk_100", .name = "aclk_100",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
static struct clksrc_clk clk_aclk_160 = { static struct clksrc_clk clk_aclk_160 = {
.clk = { .clk = {
.name = "aclk_160", .name = "aclk_160",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
static struct clksrc_clk clk_aclk_133 = { static struct clksrc_clk clk_aclk_133 = {
.clk = { .clk = {
.name = "aclk_133", .name = "aclk_133",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = { static struct clksrc_clk clk_vpllsrc = {
.clk = { .clk = {
.name = "vpll_src", .name = "vpll_src",
.id = -1,
.enable = exynos4_clksrc_mask_top_ctrl, .enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = {
.clk = { .clk = {
.name = "sclk_vpll", .name = "sclk_vpll",
.id = -1,
}, },
.sources = &clkset_sclk_vpll, .sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24), .ctrlbit = (1<<24),
}, { }, {
.name = "csis", .name = "csis",
.id = 0, .devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "csis", .name = "csis",
.id = 1, .devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 2, .devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 3, .devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "fimd", .name = "fimd",
.id = 0, .devname = "s5pv310-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl, .enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "fimd", .name = "fimd",
.id = 1, .devname = "s5pv310-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl, .enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "sataphy", .name = "sataphy",
.id = -1,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "hsmmc", .name = "dwmmc",
.id = 4,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "sata", .name = "sata",
.id = -1,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 0, .devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 1, .devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "keypad", .name = "keypad",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
}, { }, {
.name = "usbhost", .name = "usbhost",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl , .enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "spi", .name = "spi",
.id = 2, .devname = "s3c64xx-spi.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
}, { }, {
.name = "fimg2d", .name = "fimg2d",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 2, .devname = "s3c2440-i2c.2",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 3, .devname = "s3c2440-i2c.3",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 4, .devname = "s3c2440-i2c.4",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 5, .devname = "s3c2440-i2c.5",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 6, .devname = "s3c2440-i2c.6",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 7, .devname = "s3c2440-i2c.7",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "SYSMMU_MDMA", .name = "SYSMMU_MDMA",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "SYSMMU_FIMC0", .name = "SYSMMU_FIMC0",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "SYSMMU_FIMC1", .name = "SYSMMU_FIMC1",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "SYSMMU_FIMC2", .name = "SYSMMU_FIMC2",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "SYSMMU_FIMC3", .name = "SYSMMU_FIMC3",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "SYSMMU_JPEG", .name = "SYSMMU_JPEG",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, { }, {
.name = "SYSMMU_FIMD0", .name = "SYSMMU_FIMD0",
.id = -1,
.enable = exynos4_clk_ip_lcd0_ctrl, .enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_FIMD1", .name = "SYSMMU_FIMD1",
.id = -1,
.enable = exynos4_clk_ip_lcd1_ctrl, .enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_PCIe", .name = "SYSMMU_PCIe",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "SYSMMU_G2D", .name = "SYSMMU_G2D",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "SYSMMU_ROTATOR", .name = "SYSMMU_ROTATOR",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_TV", .name = "SYSMMU_TV",
.id = -1,
.enable = exynos4_clk_ip_tv_ctrl, .enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_MFC_L", .name = "SYSMMU_MFC_L",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl, .enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "SYSMMU_MFC_R", .name = "SYSMMU_MFC_R",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl, .enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
} }
@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "uart", .name = "uart",
.id = 0, .devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "uart", .name = "uart",
.id = 4, .devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "uart", .name = "uart",
.id = 5, .devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
} }
@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
static struct clksrc_clk clk_mout_g2d0 = { static struct clksrc_clk clk_mout_g2d0 = {
.clk = { .clk = {
.name = "mout_g2d0", .name = "mout_g2d0",
.id = -1,
}, },
.sources = &clkset_mout_g2d0, .sources = &clkset_mout_g2d0,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
static struct clksrc_clk clk_mout_g2d1 = { static struct clksrc_clk clk_mout_g2d1 = {
.clk = { .clk = {
.name = "mout_g2d1", .name = "mout_g2d1",
.id = -1,
}, },
.sources = &clkset_mout_g2d1, .sources = &clkset_mout_g2d1,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = {
static struct clksrc_clk clk_dout_mmc0 = { static struct clksrc_clk clk_dout_mmc0 = {
.clk = { .clk = {
.name = "dout_mmc0", .name = "dout_mmc0",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
static struct clksrc_clk clk_dout_mmc1 = { static struct clksrc_clk clk_dout_mmc1 = {
.clk = { .clk = {
.name = "dout_mmc1", .name = "dout_mmc1",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
static struct clksrc_clk clk_dout_mmc2 = { static struct clksrc_clk clk_dout_mmc2 = {
.clk = { .clk = {
.name = "dout_mmc2", .name = "dout_mmc2",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
static struct clksrc_clk clk_dout_mmc3 = { static struct clksrc_clk clk_dout_mmc3 = {
.clk = { .clk = {
.name = "dout_mmc3", .name = "dout_mmc3",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
static struct clksrc_clk clk_dout_mmc4 = { static struct clksrc_clk clk_dout_mmc4 = {
.clk = { .clk = {
.name = "dout_mmc4", .name = "dout_mmc4",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 0, .devname = "s5pv210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 1, .devname = "s5pv210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 2, .devname = "s5pv210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 3, .devname = "s5pv210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwm", .name = "sclk_pwm",
.id = -1,
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = 0, .devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = 1, .devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28), .ctrlbit = (1 << 28),
}, },
@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, },
@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 2, .devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 3, .devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = 0, .devname = "s5pv310-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl, .enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = 1, .devname = "s5pv310-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl, .enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_sata", .name = "sclk_sata",
.id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, },
@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 2, .devname = "s3c64xx-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimg2d", .name = "sclk_fimg2d",
.id = -1,
}, },
.sources = &clkset_mout_g2d, .sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_dout_mmc0.clk, .parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_dout_mmc1.clk, .parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_dout_mmc2.clk, .parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_dout_mmc3.clk, .parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_dwmmc",
.id = 4,
.parent = &clk_dout_mmc4.clk, .parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),