ARM: EXYNOS4: Add clkdev support
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [kgene.kim@samsung.com: removed changes of mach-exynos4/time.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
parent
b2a9dd466c
commit
badc4f2d60
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@ -772,6 +772,7 @@ config ARCH_EXYNOS4
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select ARCH_SPARSEMEM_ENABLE
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select GENERIC_GPIO
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select HAVE_CLK
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select CLKDEV_LOOKUP
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select ARCH_HAS_CPUFREQ
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select GENERIC_CLOCKEVENTS
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select HAVE_S3C_RTC if RTC_CLASS
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@ -27,24 +27,20 @@
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static struct clk clk_sclk_hdmi27m = {
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.name = "sclk_hdmi27m",
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.id = -1,
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.rate = 27000000,
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};
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static struct clk clk_sclk_hdmiphy = {
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.name = "sclk_hdmiphy",
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.id = -1,
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};
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static struct clk clk_sclk_usbphy0 = {
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.name = "sclk_usbphy0",
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.id = -1,
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.rate = 27000000,
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};
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static struct clk clk_sclk_usbphy1 = {
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.name = "sclk_usbphy1",
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.id = -1,
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};
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static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
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@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
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@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
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static struct clksrc_clk clk_sclk_apll = {
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.clk = {
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.name = "sclk_apll",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
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@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
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@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
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@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
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static struct clksrc_clk clk_moutcore = {
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.clk = {
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.name = "moutcore",
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.id = -1,
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},
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.sources = &clkset_moutcore,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
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@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
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static struct clksrc_clk clk_coreclk = {
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.clk = {
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.name = "core_clk",
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.id = -1,
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.parent = &clk_moutcore.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
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@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
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static struct clksrc_clk clk_armclk = {
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.clk = {
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.name = "armclk",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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};
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@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
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static struct clksrc_clk clk_aclk_corem0 = {
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.clk = {
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.name = "aclk_corem0",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
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static struct clksrc_clk clk_aclk_cores = {
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.clk = {
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.name = "aclk_cores",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
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static struct clksrc_clk clk_aclk_corem1 = {
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.clk = {
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.name = "aclk_corem1",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
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@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
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static struct clksrc_clk clk_periphclk = {
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.clk = {
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.name = "periphclk",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
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static struct clksrc_clk clk_mout_corebus = {
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.clk = {
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.name = "mout_corebus",
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.id = -1,
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},
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.sources = &clkset_mout_corebus,
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.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
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@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
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static struct clksrc_clk clk_sclk_dmc = {
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.clk = {
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.name = "sclk_dmc",
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
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@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
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static struct clksrc_clk clk_aclk_cored = {
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.clk = {
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.name = "aclk_cored",
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.id = -1,
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.parent = &clk_sclk_dmc.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
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@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
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static struct clksrc_clk clk_aclk_corep = {
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.clk = {
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.name = "aclk_corep",
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.id = -1,
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.parent = &clk_aclk_cored.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
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@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
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static struct clksrc_clk clk_aclk_acp = {
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.clk = {
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.name = "aclk_acp",
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
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@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
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static struct clksrc_clk clk_pclk_acp = {
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.clk = {
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.name = "pclk_acp",
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.id = -1,
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.parent = &clk_aclk_acp.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
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@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
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static struct clksrc_clk clk_aclk_200 = {
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.clk = {
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.name = "aclk_200",
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.id = -1,
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
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@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
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static struct clksrc_clk clk_aclk_100 = {
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.clk = {
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.name = "aclk_100",
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.id = -1,
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
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@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
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static struct clksrc_clk clk_aclk_160 = {
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.clk = {
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.name = "aclk_160",
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.id = -1,
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
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@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
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static struct clksrc_clk clk_aclk_133 = {
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.clk = {
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.name = "aclk_133",
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.id = -1,
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},
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.sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
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@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
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static struct clksrc_clk clk_vpllsrc = {
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.clk = {
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.name = "vpll_src",
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.id = -1,
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.enable = exynos4_clksrc_mask_top_ctrl,
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.ctrlbit = (1 << 0),
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},
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@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
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static struct clksrc_clk clk_sclk_vpll = {
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.clk = {
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.name = "sclk_vpll",
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.id = -1,
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},
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.sources = &clkset_sclk_vpll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
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@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
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static struct clk init_clocks_off[] = {
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{
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.name = "timers",
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.id = -1,
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.parent = &clk_aclk_100.clk,
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1<<24),
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}, {
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.name = "csis",
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.id = 0,
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.devname = "s5p-mipi-csis.0",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "csis",
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.id = 1,
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.devname = "s5p-mipi-csis.1",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 5),
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}, {
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.name = "fimc",
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.id = 0,
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.devname = "exynos4-fimc.0",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "fimc",
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.id = 1,
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.devname = "exynos4-fimc.1",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "fimc",
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.id = 2,
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.devname = "exynos4-fimc.2",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "fimc",
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.id = 3,
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.devname = "exynos4-fimc.3",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "fimd",
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.id = 0,
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.devname = "s5pv310-fb.0",
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.enable = exynos4_clk_ip_lcd0_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "fimd",
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.id = 1,
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.devname = "s5pv310-fb.1",
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "sataphy",
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.id = -1,
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "hsmmc",
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.id = 0,
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.devname = "s3c-sdhci.0",
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 5),
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}, {
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.name = "hsmmc",
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.id = 1,
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.devname = "s3c-sdhci.1",
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 6),
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}, {
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.name = "hsmmc",
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.id = 2,
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.devname = "s3c-sdhci.2",
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = "hsmmc",
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.id = 3,
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.devname = "s3c-sdhci.3",
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "hsmmc",
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.id = 4,
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.name = "dwmmc",
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 9),
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}, {
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.name = "sata",
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.id = -1,
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.parent = &clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 10),
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}, {
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.name = "pdma",
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.id = 0,
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.devname = "s3c-pl330.0",
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "pdma",
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.id = 1,
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.devname = "s3c-pl330.1",
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "adc",
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.id = -1,
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 15),
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}, {
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.name = "keypad",
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.id = -1,
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.enable = exynos4_clk_ip_perir_ctrl,
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.ctrlbit = (1 << 16),
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}, {
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.name = "rtc",
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.id = -1,
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.enable = exynos4_clk_ip_perir_ctrl,
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.ctrlbit = (1 << 15),
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_aclk_100.clk,
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.enable = exynos4_clk_ip_perir_ctrl,
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.ctrlbit = (1 << 14),
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}, {
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.name = "usbhost",
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.id = -1,
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.enable = exynos4_clk_ip_fsys_ctrl ,
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.ctrlbit = (1 << 12),
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}, {
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.name = "otg",
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.id = -1,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 13),
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}, {
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.name = "spi",
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.id = 0,
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.devname = "s3c64xx-spi.0",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 16),
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}, {
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.name = "spi",
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.id = 1,
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.devname = "s3c64xx-spi.1",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 17),
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}, {
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.name = "spi",
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.id = 2,
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.devname = "s3c64xx-spi.2",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 18),
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}, {
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.name = "iis",
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.id = 0,
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.devname = "samsung-i2s.0",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 19),
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}, {
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.name = "iis",
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.id = 1,
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.devname = "samsung-i2s.1",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 20),
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}, {
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.name = "iis",
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.id = 2,
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.devname = "samsung-i2s.2",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 21),
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}, {
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@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = {
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.ctrlbit = (1 << 27),
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}, {
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.name = "fimg2d",
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.id = -1,
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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}, {
|
||||
.name = "i2c",
|
||||
.id = 0,
|
||||
.devname = "s3c2440-i2c.0",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 1,
|
||||
.devname = "s3c2440-i2c.1",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 2,
|
||||
.devname = "s3c2440-i2c.2",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 3,
|
||||
.devname = "s3c2440-i2c.3",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 4,
|
||||
.devname = "s3c2440-i2c.4",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 5,
|
||||
.devname = "s3c2440-i2c.5",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 6,
|
||||
.devname = "s3c2440-i2c.6",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 7,
|
||||
.devname = "s3c2440-i2c.7",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "SYSMMU_MDMA",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC0",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC1",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC2",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC3",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "SYSMMU_JPEG",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMD0",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMD1",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_PCIe",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 18),
|
||||
}, {
|
||||
.name = "SYSMMU_G2D",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "SYSMMU_ROTATOR",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_TV",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_MFC_L",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_mfc_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "SYSMMU_MFC_R",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_mfc_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}
|
||||
|
@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = {
|
|||
static struct clk init_clocks[] = {
|
||||
{
|
||||
.name = "uart",
|
||||
.id = 0,
|
||||
.devname = "s5pv210-uart.0",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 1,
|
||||
.devname = "s5pv210-uart.1",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 2,
|
||||
.devname = "s5pv210-uart.2",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 3,
|
||||
.devname = "s5pv210-uart.3",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 4,
|
||||
.devname = "s5pv210-uart.4",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 5,
|
||||
.devname = "s5pv210-uart.5",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}
|
||||
|
@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
|
|||
static struct clksrc_clk clk_mout_g2d0 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d0",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_mout_g2d0,
|
||||
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
||||
|
@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
|
|||
static struct clksrc_clk clk_mout_g2d1 = {
|
||||
.clk = {
|
||||
.name = "mout_g2d1",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_mout_g2d1,
|
||||
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
|
||||
|
@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = {
|
|||
static struct clksrc_clk clk_dout_mmc0 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc0",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
|
||||
|
@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
|
|||
static struct clksrc_clk clk_dout_mmc1 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc1",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
|
||||
|
@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
|
|||
static struct clksrc_clk clk_dout_mmc2 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc2",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
|
||||
|
@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
|
|||
static struct clksrc_clk clk_dout_mmc3 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc3",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
|
||||
|
@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
|
|||
static struct clksrc_clk clk_dout_mmc4 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc4",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
|
||||
|
@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
{
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 0,
|
||||
.devname = "s5pv210-uart.0",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
|
@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 1,
|
||||
.devname = "s5pv210-uart.1",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
|
@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 2,
|
||||
.devname = "s5pv210-uart.2",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
|
@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 3,
|
||||
.devname = "s5pv210-uart.3",
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
|
@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_pwm",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
|
@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_csis",
|
||||
.id = 0,
|
||||
.devname = "s5p-mipi-csis.0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
|
@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_csis",
|
||||
.id = 1,
|
||||
.devname = "s5p-mipi-csis.1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 28),
|
||||
},
|
||||
|
@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.id = 0,
|
||||
.devname = "exynos4-fimc.0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
|
@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.id = 1,
|
||||
.devname = "exynos4-fimc.1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
|
@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 0,
|
||||
.devname = "exynos4-fimc.0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
|
@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 1,
|
||||
.devname = "exynos4-fimc.1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
|
@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 2,
|
||||
.devname = "exynos4-fimc.2",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
|
@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 3,
|
||||
.devname = "exynos4-fimc.3",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
|
@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.id = 0,
|
||||
.devname = "s5pv310-fb.0",
|
||||
.enable = exynos4_clksrc_mask_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
|
@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.id = 1,
|
||||
.devname = "s5pv310-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
|
@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
|
@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 0,
|
||||
.devname = "s3c64xx-spi.0",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
|
@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 1,
|
||||
.devname = "s3c64xx-spi.1",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
|
@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 2,
|
||||
.devname = "s3c64xx-spi.2",
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
|
@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimg2d",
|
||||
.id = -1,
|
||||
},
|
||||
.sources = &clkset_mout_g2d,
|
||||
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
||||
|
@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.id = 0,
|
||||
.devname = "s3c-sdhci.0",
|
||||
.parent = &clk_dout_mmc0.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.id = 1,
|
||||
.devname = "s3c-sdhci.1",
|
||||
.parent = &clk_dout_mmc1.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.id = 2,
|
||||
.devname = "s3c-sdhci.2",
|
||||
.parent = &clk_dout_mmc2.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.id = 3,
|
||||
.devname = "s3c-sdhci.3",
|
||||
.parent = &clk_dout_mmc3.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.id = 4,
|
||||
.name = "sclk_dwmmc",
|
||||
.parent = &clk_dout_mmc4.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
|
|
Loading…
Reference in New Issue