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[media] V4L: Add driver for S3C24XX/S3C64XX SoC series camera interface 

This patch adds V4L2 driver for Samsung S3C24XX/S3C64XX SoC series
camera interface. The driver exposes a subdev device node for CAMIF
pixel resolution and crop control and two video capture nodes - for
the "codec" and "preview" data paths. It has been tested on Mini2440
(s3c2440) and Mini6410 (s3c6410) board with gstreamer and mplayer.

Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Andrey Gusakov <dron0gus@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sylwester Nawrocki 2012-08-22 20:09:18 -03:00 committed by Mauro Carvalho Chehab
parent d033a308d8
commit babde1c243
9 changed files with 3665 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/media/platform/Kconfig
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@ -109,6 +109,18 @@ config VIDEO_OMAP3_DEBUG
---help---
Enable debug messages on OMAP 3 camera controller driver.
config VIDEO_S3C_CAMIF
tristate "Samsung S3C24XX/S3C64XX SoC Camera Interface driver"
depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
depends on (PLAT_S3C64XX || PLAT_S3C24XX) && PM_RUNTIME
select VIDEOBUF2_DMA_CONTIG
---help---
This is a v4l2 driver for s3c24xx and s3c64xx SoC series camera
host interface (CAMIF).
To compile this driver as a module, choose M here: the module
will be called s3c-camif.
source "drivers/media/platform/soc_camera/Kconfig"
source "drivers/media/platform/s5p-fimc/Kconfig"
source "drivers/media/platform/s5p-tv/Kconfig"

1
drivers/media/platform/Makefile
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@ -27,6 +27,7 @@ obj-$(CONFIG_VIDEO_CODA) += coda.o
obj-$(CONFIG_VIDEO_MEM2MEM_DEINTERLACE) += m2m-deinterlace.o
obj-$(CONFIG_VIDEO_S3C_CAMIF) += s3c-camif/
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg/
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/

5
drivers/media/platform/s3c-camif/Makefile Normal file
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@ -0,0 +1,5 @@
# Makefile for s3c244x/s3c64xx CAMIF driver
s3c-camif-objs := camif-core.o camif-capture.o camif-regs.o
obj-$(CONFIG_VIDEO_S3C_CAMIF) += s3c-camif.o

1672
drivers/media/platform/s3c-camif/camif-capture.c Normal file
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File diff suppressed because it is too large Load Diff

662
drivers/media/platform/s3c-camif/camif-core.c Normal file
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@ -0,0 +1,662 @@
/*
* s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver
*
* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
* Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published
* by the Free Software Foundation, either version 2 of the License,
* or (at your option) any later version.
*/
#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/media-device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
#include "camif-core.h"
static char *camif_clocks[CLK_MAX_NUM] = {
/* HCLK CAMIF clock */
[CLK_GATE] = "camif",
/* CAMIF / external camera sensor master clock */
[CLK_CAM] = "camera",
};
static const struct camif_fmt camif_formats[] = {
{
.name = "YUV 4:2:2 planar, Y/Cb/Cr",
.fourcc = V4L2_PIX_FMT_YUV422P,
.depth = 16,
.ybpp = 1,
.color = IMG_FMT_YCBCR422P,
.colplanes = 3,
.flags = FMT_FL_S3C24XX_CODEC |
FMT_FL_S3C64XX,
}, {
.name = "YUV 4:2:0 planar, Y/Cb/Cr",
.fourcc = V4L2_PIX_FMT_YUV420,
.depth = 12,
.ybpp = 1,
.color = IMG_FMT_YCBCR420,
.colplanes = 3,
.flags = FMT_FL_S3C24XX_CODEC |
FMT_FL_S3C64XX,
}, {
.name = "YVU 4:2:0 planar, Y/Cr/Cb",
.fourcc = V4L2_PIX_FMT_YVU420,
.depth = 12,
.ybpp = 1,
.color = IMG_FMT_YCRCB420,
.colplanes = 3,
.flags = FMT_FL_S3C24XX_CODEC |
FMT_FL_S3C64XX,
}, {
.name = "RGB565, 16 bpp",
.fourcc = V4L2_PIX_FMT_RGB565X,
.depth = 16,
.ybpp = 2,
.color = IMG_FMT_RGB565,
.colplanes = 1,
.flags = FMT_FL_S3C24XX_PREVIEW |
FMT_FL_S3C64XX,
}, {
.name = "XRGB8888, 32 bpp",
.fourcc = V4L2_PIX_FMT_RGB32,
.depth = 32,
.ybpp = 4,
.color = IMG_FMT_XRGB8888,
.colplanes = 1,
.flags = FMT_FL_S3C24XX_PREVIEW |
FMT_FL_S3C64XX,
}, {
.name = "BGR666",
.fourcc = V4L2_PIX_FMT_BGR666,
.depth = 32,
.ybpp = 4,
.color = IMG_FMT_RGB666,
.colplanes = 1,
.flags = FMT_FL_S3C64XX,
}
};
/**
* s3c_camif_find_format() - lookup camif color format by fourcc or an index
* @pixelformat: fourcc to match, ignored if null
* @index: index to the camif_formats array, ignored if negative
*/
const struct camif_fmt *s3c_camif_find_format(struct camif_vp *vp,
const u32 *pixelformat,
int index)
{
const struct camif_fmt *fmt, *def_fmt = NULL;
unsigned int i;
int id = 0;
if (index >= (int)ARRAY_SIZE(camif_formats))
return NULL;
for (i = 0; i < ARRAY_SIZE(camif_formats); ++i) {
fmt = &camif_formats[i];
if (vp && !(vp->fmt_flags & fmt->flags))
continue;
if (pixelformat && fmt->fourcc == *pixelformat)
return fmt;
if (index == id)
def_fmt = fmt;
id++;
}
return def_fmt;
}
static int camif_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
{
unsigned int sh = 6;
if (src >= 64 * tar)
return -EINVAL;
while (sh--) {
unsigned int tmp = 1 << sh;
if (src >= tar * tmp) {
*shift = sh, *ratio = tmp;
return 0;
}
}
*shift = 0, *ratio = 1;
return 0;
}
int s3c_camif_get_scaler_config(struct camif_vp *vp,
struct camif_scaler *scaler)
{
struct v4l2_rect *camif_crop = &vp->camif->camif_crop;
int source_x = camif_crop->width;
int source_y = camif_crop->height;
int target_x = vp->out_frame.rect.width;
int target_y = vp->out_frame.rect.height;
int ret;
if (vp->rotation == 90 || vp->rotation == 270)
swap(target_x, target_y);
ret = camif_get_scaler_factor(source_x, target_x, &scaler->pre_h_ratio,
&scaler->h_shift);
if (ret < 0)
return ret;
ret = camif_get_scaler_factor(source_y, target_y, &scaler->pre_v_ratio,
&scaler->v_shift);
if (ret < 0)
return ret;
scaler->pre_dst_width = source_x / scaler->pre_h_ratio;
scaler->pre_dst_height = source_y / scaler->pre_v_ratio;
scaler->main_h_ratio = (source_x << 8) / (target_x << scaler->h_shift);
scaler->main_v_ratio = (source_y << 8) / (target_y << scaler->v_shift);
scaler->scaleup_h = (target_x >= source_x);
scaler->scaleup_v = (target_y >= source_y);
scaler->copy = 0;
pr_debug("H: ratio: %u, shift: %u. V: ratio: %u, shift: %u.\n",
scaler->pre_h_ratio, scaler->h_shift,
scaler->pre_v_ratio, scaler->v_shift);
pr_debug("Source: %dx%d, Target: %dx%d, scaleup_h/v: %d/%d\n",
source_x, source_y, target_x, target_y,
scaler->scaleup_h, scaler->scaleup_v);
return 0;
}
static int camif_register_sensor(struct camif_dev *camif)
{
struct s3c_camif_sensor_info *sensor = &camif->pdata.sensor;
struct v4l2_device *v4l2_dev = &camif->v4l2_dev;
struct i2c_adapter *adapter;
struct v4l2_subdev_format format;
struct v4l2_subdev *sd;
int ret;
camif->sensor.sd = NULL;
if (sensor->i2c_board_info.addr == 0)
return -EINVAL;
adapter = i2c_get_adapter(sensor->i2c_bus_num);
if (adapter == NULL) {
v4l2_warn(v4l2_dev, "failed to get I2C adapter %d\n",
sensor->i2c_bus_num);
return -EPROBE_DEFER;
}
sd = v4l2_i2c_new_subdev_board(v4l2_dev, adapter,
&sensor->i2c_board_info, NULL);
if (sd == NULL) {
i2c_put_adapter(adapter);
v4l2_warn(v4l2_dev, "failed to acquire subdev %s\n",
sensor->i2c_board_info.type);
return -EPROBE_DEFER;
}
camif->sensor.sd = sd;
v4l2_info(v4l2_dev, "registered sensor subdevice %s\n", sd->name);
/* Get initial pixel format and set it at the camif sink pad */
format.pad = 0;
format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &format);
if (ret < 0)
return 0;
format.pad = CAMIF_SD_PAD_SINK;
v4l2_subdev_call(&camif->subdev, pad, set_fmt, NULL, &format);
v4l2_info(sd, "Initial format from sensor: %dx%d, %#x\n",
format.format.width, format.format.height,
format.format.code);
return 0;
}
static void camif_unregister_sensor(struct camif_dev *camif)
{
struct v4l2_subdev *sd = camif->sensor.sd;
struct i2c_client *client = sd ? v4l2_get_subdevdata(sd) : NULL;
struct i2c_adapter *adapter;
if (client == NULL)
return;
adapter = client->adapter;
v4l2_device_unregister_subdev(sd);
camif->sensor.sd = NULL;
i2c_unregister_device(client);
if (adapter)
i2c_put_adapter(adapter);
}
static int camif_create_media_links(struct camif_dev *camif)
{
int i, ret;
ret = media_entity_create_link(&camif->sensor.sd->entity, 0,
&camif->subdev.entity, CAMIF_SD_PAD_SINK,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
if (ret)
return ret;
for (i = 1; i < CAMIF_SD_PADS_NUM && !ret; i++) {
ret = media_entity_create_link(&camif->subdev.entity, i,
&camif->vp[i - 1].vdev.entity, 0,
MEDIA_LNK_FL_IMMUTABLE |
MEDIA_LNK_FL_ENABLED);
}
return ret;
}
static int camif_register_video_nodes(struct camif_dev *camif)
{
int ret = s3c_camif_register_video_node(camif, VP_CODEC);
if (ret < 0)
return ret;
return s3c_camif_register_video_node(camif, VP_PREVIEW);
}
static void camif_unregister_video_nodes(struct camif_dev *camif)
{
s3c_camif_unregister_video_node(camif, VP_CODEC);
s3c_camif_unregister_video_node(camif, VP_PREVIEW);
}
static void camif_unregister_media_entities(struct camif_dev *camif)
{
camif_unregister_video_nodes(camif);
camif_unregister_sensor(camif);
s3c_camif_unregister_subdev(camif);
}
/*
* Media device
*/
static int camif_media_dev_register(struct camif_dev *camif)
{
struct media_device *md = &camif->media_dev;
struct v4l2_device *v4l2_dev = &camif->v4l2_dev;
unsigned int ip_rev = camif->variant->ip_revision;
int ret;
memset(md, 0, sizeof(*md));
snprintf(md->model, sizeof(md->model), "SAMSUNG S3C%s CAMIF",
ip_rev == S3C6410_CAMIF_IP_REV ? "6410" : "244X");
strlcpy(md->bus_info, "platform", sizeof(md->bus_info));
md->hw_revision = ip_rev;
md->driver_version = KERNEL_VERSION(1, 0, 0);
md->dev = camif->dev;
strlcpy(v4l2_dev->name, "s3c-camif", sizeof(v4l2_dev->name));
v4l2_dev->mdev = md;
ret = v4l2_device_register(camif->dev, v4l2_dev);
if (ret < 0)
return ret;
ret = media_device_register(md);
if (ret < 0)
v4l2_device_unregister(v4l2_dev);
return ret;
}
static void camif_clk_put(struct camif_dev *camif)
{
int i;
for (i = 0; i < CLK_MAX_NUM; i++) {
if (IS_ERR_OR_NULL(camif->clock[i]))
continue;
clk_unprepare(camif->clock[i]);
clk_put(camif->clock[i]);
}
}
static int camif_clk_get(struct camif_dev *camif)
{
int ret, i;
for (i = 0; i < CLK_MAX_NUM; i++) {
camif->clock[i] = clk_get(camif->dev, camif_clocks[i]);
if (IS_ERR(camif->clock[i])) {
ret = PTR_ERR(camif->clock[i]);
goto err;
}
ret = clk_prepare(camif->clock[i]);
if (ret < 0) {
clk_put(camif->clock[i]);
camif->clock[i] = NULL;
goto err;
}
}
return 0;
err:
camif_clk_put(camif);
dev_err(camif->dev, "failed to get clock: %s\n",
camif_clocks[i]);
return ret;
}
/*
* The CAMIF device has two relatively independent data processing paths
* that can source data from memory or the common camera input frontend.
* Register interrupts for each data processing path (camif_vp).
*/
static int camif_request_irqs(struct platform_device *pdev,
struct camif_dev *camif)
{
int irq, ret, i;
for (i = 0; i < CAMIF_VP_NUM; i++) {
struct camif_vp *vp = &camif->vp[i];
init_waitqueue_head(&vp->irq_queue);
irq = platform_get_irq(pdev, i);
if (irq <= 0) {
dev_err(&pdev->dev, "failed to get IRQ %d\n", i);
return -ENXIO;
}
ret = devm_request_irq(&pdev->dev, irq, s3c_camif_irq_handler,
0, dev_name(&pdev->dev), vp);
if (ret < 0) {
dev_err(&pdev->dev, "failed to install IRQ: %d\n", ret);
break;
}
}
return ret;
}
static int s3c_camif_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct s3c_camif_plat_data *pdata = dev->platform_data;
struct s3c_camif_drvdata *drvdata;
struct camif_dev *camif;
struct resource *mres;
int ret = 0;
camif = devm_kzalloc(dev, sizeof(*camif), GFP_KERNEL);
if (!camif)
return -ENOMEM;
spin_lock_init(&camif->slock);
mutex_init(&camif->lock);
camif->dev = dev;
if (!pdata || !pdata->gpio_get || !pdata->gpio_put) {
dev_err(dev, "wrong platform data\n");
return -EINVAL;
}
camif->pdata = *pdata;
drvdata = (void *)platform_get_device_id(pdev)->driver_data;
camif->variant = drvdata->variant;
mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
camif->io_base = devm_request_and_ioremap(dev, mres);
if (!camif->io_base) {
dev_err(dev, "failed to obtain I/O memory\n");
return -ENOENT;
}
ret = camif_request_irqs(pdev, camif);
if (ret < 0)
return ret;
ret = pdata->gpio_get();
if (ret < 0)
return ret;
ret = s3c_camif_create_subdev(camif);
if (ret < 0)
goto err_sd;
ret = camif_clk_get(camif);
if (ret < 0)
goto err_clk;
platform_set_drvdata(pdev, camif);
clk_set_rate(camif->clock[CLK_CAM],
camif->pdata.sensor.clock_frequency);
dev_info(dev, "sensor clock frequency: %lu\n",
clk_get_rate(camif->clock[CLK_CAM]));
/*
* Set initial pixel format, resolution and crop rectangle.
* Must be done before a sensor subdev is registered as some
* settings are overrode with values from sensor subdev.
*/
s3c_camif_set_defaults(camif);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0)
goto err_pm;
/* Initialize contiguous memory allocator */
camif->alloc_ctx = vb2_dma_contig_init_ctx(dev);
if (IS_ERR(camif->alloc_ctx)) {
ret = PTR_ERR(camif->alloc_ctx);
goto err_alloc;
}
ret = camif_media_dev_register(camif);
if (ret < 0)
goto err_mdev;
ret = camif_register_sensor(camif);
if (ret < 0)
goto err_sens;
ret = v4l2_device_register_subdev(&camif->v4l2_dev, &camif->subdev);
if (ret < 0)
goto err_sens;
mutex_lock(&camif->media_dev.graph_mutex);
ret = v4l2_device_register_subdev_nodes(&camif->v4l2_dev);
if (ret < 0)
goto err_unlock;
ret = camif_register_video_nodes(camif);
if (ret < 0)
goto err_unlock;
ret = camif_create_media_links(camif);
if (ret < 0)
goto err_unlock;
mutex_unlock(&camif->media_dev.graph_mutex);
pm_runtime_put(dev);
return 0;
err_unlock:
mutex_unlock(&camif->media_dev.graph_mutex);
err_sens:
v4l2_device_unregister(&camif->v4l2_dev);
media_device_unregister(&camif->media_dev);
camif_unregister_media_entities(camif);
err_mdev:
vb2_dma_contig_cleanup_ctx(camif->alloc_ctx);
err_alloc:
pm_runtime_put(dev);
pm_runtime_disable(dev);
err_pm:
camif_clk_put(camif);
err_clk:
s3c_camif_unregister_subdev(camif);
err_sd:
pdata->gpio_put();
return ret;
}
static int __devexit s3c_camif_remove(struct platform_device *pdev)
{
struct camif_dev *camif = platform_get_drvdata(pdev);
struct s3c_camif_plat_data *pdata = &camif->pdata;
media_device_unregister(&camif->media_dev);
camif_unregister_media_entities(camif);
v4l2_device_unregister(&camif->v4l2_dev);
pm_runtime_disable(&pdev->dev);
camif_clk_put(camif);
pdata->gpio_put();
return 0;
}
static int s3c_camif_runtime_resume(struct device *dev)
{
struct camif_dev *camif = dev_get_drvdata(dev);
clk_enable(camif->clock[CLK_GATE]);
/* null op on s3c244x */
clk_enable(camif->clock[CLK_CAM]);
return 0;
}
static int s3c_camif_runtime_suspend(struct device *dev)
{
struct camif_dev *camif = dev_get_drvdata(dev);
/* null op on s3c244x */
clk_disable(camif->clock[CLK_CAM]);
clk_disable(camif->clock[CLK_GATE]);
return 0;
}
static const struct s3c_camif_variant s3c244x_camif_variant = {
.vp_pix_limits = {
[VP_CODEC] = {
.max_out_width = 4096,
.max_sc_out_width = 2048,
.out_width_align = 16,
.min_out_width = 16,
.max_height = 4096,
},
[VP_PREVIEW] = {
.max_out_width = 640,
.max_sc_out_width = 640,
.out_width_align = 16,
.min_out_width = 16,
.max_height = 480,
}
},
.pix_limits = {
.win_hor_offset_align = 8,
},
.ip_revision = S3C244X_CAMIF_IP_REV,
};
static struct s3c_camif_drvdata s3c244x_camif_drvdata = {
.variant = &s3c244x_camif_variant,
.bus_clk_freq = 24000000UL,
};
static const struct s3c_camif_variant s3c6410_camif_variant = {
.vp_pix_limits = {
[VP_CODEC] = {
.max_out_width = 4096,
.max_sc_out_width = 2048,
.out_width_align = 16,
.min_out_width = 16,
.max_height = 4096,
},
[VP_PREVIEW] = {
.max_out_width = 4096,
.max_sc_out_width = 720,
.out_width_align = 16,
.min_out_width = 16,
.max_height = 4096,
}
},
.pix_limits = {
.win_hor_offset_align = 8,
},
.ip_revision = S3C6410_CAMIF_IP_REV,
.has_img_effect = 1,
.vp_offset = 0x20,
};
static struct s3c_camif_drvdata s3c6410_camif_drvdata = {
.variant = &s3c6410_camif_variant,
.bus_clk_freq = 133000000UL,
};
static struct platform_device_id s3c_camif_driver_ids[] = {
{
.name = "s3c2440-camif",
.driver_data = (unsigned long)&s3c244x_camif_drvdata,
}, {
.name = "s3c6410-camif",
.driver_data = (unsigned long)&s3c6410_camif_drvdata,
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(platform, s3c_camif_driver_ids);
static const struct dev_pm_ops s3c_camif_pm_ops = {
.runtime_suspend = s3c_camif_runtime_suspend,
.runtime_resume = s3c_camif_runtime_resume,
};
static struct platform_driver s3c_camif_driver = {
.probe = s3c_camif_probe,
.remove = __devexit_p(s3c_camif_remove),
.id_table = s3c_camif_driver_ids,
.driver = {
.name = S3C_CAMIF_DRIVER_NAME,
.owner = THIS_MODULE,
.pm = &s3c_camif_pm_ops,
}
};
module_platform_driver(s3c_camif_driver);
MODULE_AUTHOR("Sylwester Nawrocki <sylvester.nawrocki@gmail.com>");
MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
MODULE_DESCRIPTION("S3C24XX/S3C64XX SoC camera interface driver");
MODULE_LICENSE("GPL");

393
drivers/media/platform/s3c-camif/camif-core.h Normal file
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@ -0,0 +1,393 @@
/*
* s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver
*
* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
* Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef CAMIF_CORE_H_
#define CAMIF_CORE_H_
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mediabus.h>
#include <media/videobuf2-core.h>
#include <media/s3c_camif.h>
#define S3C_CAMIF_DRIVER_NAME "s3c-camif"
#define CAMIF_REQ_BUFS_MIN 3
#define CAMIF_MAX_OUT_BUFS 4
#define CAMIF_MAX_PIX_WIDTH 4096
#define CAMIF_MAX_PIX_HEIGHT 4096
#define SCALER_MAX_RATIO 64
#define CAMIF_DEF_WIDTH 640
#define CAMIF_DEF_HEIGHT 480
#define CAMIF_STOP_TIMEOUT 1500 /* ms */
#define S3C244X_CAMIF_IP_REV 0x20 /* 2.0 */
#define S3C2450_CAMIF_IP_REV 0x30 /* 3.0 - not implemented, not tested */
#define S3C6400_CAMIF_IP_REV 0x31 /* 3.1 - not implemented, not tested */
#define S3C6410_CAMIF_IP_REV 0x32 /* 3.2 */
/* struct camif_vp::state */
#define ST_VP_PENDING (1 << 0)
#define ST_VP_RUNNING (1 << 1)
#define ST_VP_STREAMING (1 << 2)
#define ST_VP_SENSOR_STREAMING (1 << 3)
#define ST_VP_ABORTING (1 << 4)
#define ST_VP_OFF (1 << 5)
#define ST_VP_LASTIRQ (1 << 6)
#define ST_VP_CONFIG (1 << 8)
#define CAMIF_SD_PAD_SINK 0
#define CAMIF_SD_PAD_SOURCE_C 1
#define CAMIF_SD_PAD_SOURCE_P 2
#define CAMIF_SD_PADS_NUM 3
enum img_fmt {
IMG_FMT_RGB565 = 0x0010,
IMG_FMT_RGB666,
IMG_FMT_XRGB8888,
IMG_FMT_YCBCR420 = 0x0020,
IMG_FMT_YCRCB420,
IMG_FMT_YCBCR422P,
IMG_FMT_YCBYCR422 = 0x0040,
IMG_FMT_YCRYCB422,
IMG_FMT_CBYCRY422,
IMG_FMT_CRYCBY422,
};
#define img_fmt_is_rgb(x) ((x) & 0x10)
#define img_fmt_is_ycbcr(x) ((x) & 0x60)
/* Possible values for struct camif_fmt::flags */
#define FMT_FL_S3C24XX_CODEC (1 << 0)
#define FMT_FL_S3C24XX_PREVIEW (1 << 1)
#define FMT_FL_S3C64XX (1 << 2)
/**
* struct camif_fmt - pixel format description
* @fourcc: fourcc code for this format, 0 if not applicable
* @color: a corresponding enum img_fmt
* @colplanes: number of physically contiguous data planes
* @flags: indicate for which SoCs revisions this format is valid
* @depth: bits per pixel (total)
* @ybpp: number of luminance bytes per pixel
*/
struct camif_fmt {
char *name;
u32 fourcc;
u32 color;
u16 colplanes;
u16 flags;
u8 depth;
u8 ybpp;
};
/**
* struct camif_dma_offset - pixel offset information for DMA
* @initial: offset (in pixels) to first pixel
* @line: offset (in pixels) from end of line to start of next line
*/
struct camif_dma_offset {
int initial;
int line;
};
/**
* struct camif_frame - source/target frame properties
* @f_width: full pixel width
* @f_height: full pixel height
* @rect: crop/composition rectangle
* @dma_offset: DMA offset configuration
*/
struct camif_frame {
u16 f_width;
u16 f_height;
struct v4l2_rect rect;
struct camif_dma_offset dma_offset;
};
/* CAMIF clocks enumeration */
enum {
CLK_GATE,
CLK_CAM,
CLK_MAX_NUM,
};
struct vp_pix_limits {
u16 max_out_width;
u16 max_sc_out_width;
u16 out_width_align;
u16 max_height;
u8 min_out_width;
u16 out_hor_offset_align;
};
struct camif_pix_limits {
u16 win_hor_offset_align;
};
/**
* struct s3c_camif_variant - CAMIF variant structure
* @vp_pix_limits: pixel limits for the codec and preview paths
* @camif_pix_limits: pixel limits for the camera input interface
* @ip_revision: the CAMIF IP revision: 0x20 for s3c244x, 0x32 for s3c6410
*/
struct s3c_camif_variant {
struct vp_pix_limits vp_pix_limits[2];
struct camif_pix_limits pix_limits;
u8 ip_revision;
u8 has_img_effect;
unsigned int vp_offset;
};
struct s3c_camif_drvdata {
const struct s3c_camif_variant *variant;
unsigned long bus_clk_freq;
};
struct camif_scaler {
u8 scaleup_h;
u8 scaleup_v;
u8 copy;
u8 enable;
u32 h_shift;
u32 v_shift;
u32 pre_h_ratio;
u32 pre_v_ratio;
u32 pre_dst_width;
u32 pre_dst_height;
u32 main_h_ratio;
u32 main_v_ratio;
};
struct camif_dev;
/**
* struct camif_vp - CAMIF data processing path structure (codec/preview)
* @irq_queue: interrupt handling waitqueue
* @irq: interrupt number for this data path
* @camif: pointer to the camif structure
* @pad: media pad for the video node
* @vdev video device
* @ctrl_handler: video node controls handler
* @owner: file handle that own the streaming
* @pending_buf_q: pending (empty) buffers queue head
* @active_buf_q: active (being written) buffers queue head
* @active_buffers: counter of buffer set up at the DMA engine
* @buf_index: identifier of a last empty buffer set up in H/W
* @frame_sequence: image frame sequence counter
* @reqbufs_count: the number of buffers requested
* @scaler: the scaler structure
* @out_fmt: pixel format at this video path output
* @payload: the output data frame payload size
* @out_frame: the output pixel resolution
* @state: the video path's state
* @fmt_flags: flags determining supported pixel formats
* @id: CAMIF id, 0 - codec, 1 - preview
* @rotation: current image rotation value
* @hflip: apply horizontal flip if set
* @vflip: apply vertical flip if set
*/
struct camif_vp {
wait_queue_head_t irq_queue;
int irq;
struct camif_dev *camif;
struct media_pad pad;
struct video_device vdev;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_fh *owner;
struct vb2_queue vb_queue;
struct list_head pending_buf_q;
struct list_head active_buf_q;
unsigned int active_buffers;
unsigned int buf_index;
unsigned int frame_sequence;
unsigned int reqbufs_count;
struct camif_scaler scaler;
const struct camif_fmt *out_fmt;
unsigned int payload;
struct camif_frame out_frame;
unsigned int state;
u16 fmt_flags;
u8 id;
u8 rotation;
u8 hflip;
u8 vflip;
unsigned int offset;
};
/* Video processing path enumeration */
#define VP_CODEC 0
#define VP_PREVIEW 1
#define CAMIF_VP_NUM 2
/**
* struct camif_dev - the CAMIF driver private data structure
* @media_dev: top-level media device structure
* @v4l2_dev: root v4l2_device
* @subdev: camera interface ("catchcam") subdev
* @mbus_fmt: camera input media bus format
* @camif_crop: camera input interface crop rectangle
* @pads: the camif subdev's media pads
* @stream_count: the camera interface streaming reference counter
* @sensor: image sensor data structure
* @m_pipeline: video entity pipeline description
* @ctrl_handler: v4l2 control handler (owned by @subdev)
* @test_pattern: test pattern controls
* @vp: video path (DMA) description (codec/preview)
* @alloc_ctx: memory buffer allocator context
* @variant: variant information for this device
* @dev: pointer to the CAMIF device struct
* @pdata: a copy of the driver's platform data
* @clock: clocks required for the CAMIF operation
* @lock: mutex protecting this data structure
* @slock: spinlock protecting CAMIF registers
* @io_base: start address of the mmaped CAMIF registers
*/
struct camif_dev {
struct media_device media_dev;
struct v4l2_device v4l2_dev;
struct v4l2_subdev subdev;
struct v4l2_mbus_framefmt mbus_fmt;
struct v4l2_rect camif_crop;
struct media_pad pads[CAMIF_SD_PADS_NUM];
int stream_count;
struct cam_sensor {
struct v4l2_subdev *sd;
short power_count;
short stream_count;
} sensor;
struct media_pipeline *m_pipeline;
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_ctrl *ctrl_test_pattern;
struct {
struct v4l2_ctrl *ctrl_colorfx;
struct v4l2_ctrl *ctrl_colorfx_cbcr;
};
u8 test_pattern;
u8 colorfx;
u8 colorfx_cb;
u8 colorfx_cr;
struct camif_vp vp[CAMIF_VP_NUM];
struct vb2_alloc_ctx *alloc_ctx;
const struct s3c_camif_variant *variant;
struct device *dev;
struct s3c_camif_plat_data pdata;
struct clk *clock[CLK_MAX_NUM];
struct mutex lock;
spinlock_t slock;
void __iomem *io_base;
};
/**
* struct camif_addr - Y/Cb/Cr DMA start address structure
* @y: luminance plane dma address
* @cb: Cb plane dma address
* @cr: Cr plane dma address
*/
struct camif_addr {
dma_addr_t y;
dma_addr_t cb;
dma_addr_t cr;
};
/**
* struct camif_buffer - the camif video buffer structure
* @vb: vb2 buffer
* @list: list head for the buffers queue
* @paddr: DMA start addresses
* @index: an identifier of this buffer at the DMA engine
*/
struct camif_buffer {
struct vb2_buffer vb;
struct list_head list;
struct camif_addr paddr;
unsigned int index;
};
const struct camif_fmt *s3c_camif_find_format(struct camif_vp *vp,
const u32 *pixelformat, int index);
int s3c_camif_register_video_node(struct camif_dev *camif, int idx);
void s3c_camif_unregister_video_node(struct camif_dev *camif, int idx);
irqreturn_t s3c_camif_irq_handler(int irq, void *priv);
int s3c_camif_create_subdev(struct camif_dev *camif);
void s3c_camif_unregister_subdev(struct camif_dev *camif);
int s3c_camif_set_defaults(struct camif_dev *camif);
int s3c_camif_get_scaler_config(struct camif_vp *vp,
struct camif_scaler *scaler);
static inline void camif_active_queue_add(struct camif_vp *vp,
struct camif_buffer *buf)
{
list_add_tail(&buf->list, &vp->active_buf_q);
vp->active_buffers++;
}
static inline struct camif_buffer *camif_active_queue_pop(
struct camif_vp *vp)
{
struct camif_buffer *buf = list_first_entry(&vp->active_buf_q,
struct camif_buffer, list);
list_del(&buf->list);
vp->active_buffers--;
return buf;
}
static inline struct camif_buffer *camif_active_queue_peek(
struct camif_vp *vp, int index)
{
struct camif_buffer *tmp, *buf;
if (WARN_ON(list_empty(&vp->active_buf_q)))
return NULL;
list_for_each_entry_safe(buf, tmp, &vp->active_buf_q, list) {
if (buf->index == index) {
list_del(&buf->list);
vp->active_buffers--;
return buf;
}
}
return NULL;
}
static inline void camif_pending_queue_add(struct camif_vp *vp,
struct camif_buffer *buf)
{
list_add_tail(&buf->list, &vp->pending_buf_q);
}
static inline struct camif_buffer *camif_pending_queue_pop(
struct camif_vp *vp)
{
struct camif_buffer *buf = list_first_entry(&vp->pending_buf_q,
struct camif_buffer, list);
list_del(&buf->list);
return buf;
}
#endif /* CAMIF_CORE_H_ */

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drivers/media/platform/s3c-camif/camif-regs.c Normal file
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/*
* Samsung s3c24xx/s3c64xx SoC CAMIF driver
*
* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
* Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
#include <linux/delay.h>
#include "camif-regs.h"
#define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
#define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
void camif_hw_reset(struct camif_dev *camif)
{
u32 cfg;
cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT);
cfg |= CISRCFMT_ITU601_8BIT;
camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg);
/* S/W reset */
cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
cfg |= CIGCTRL_SWRST;
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV)
cfg |= CIGCTRL_IRQ_LEVEL;
camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg);
udelay(10);
cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
cfg &= ~CIGCTRL_SWRST;
camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg);
udelay(10);
}
void camif_hw_clear_pending_irq(struct camif_vp *vp)
{
u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_CIGCTRL);
cfg |= CIGCTRL_IRQ_CLR(vp->id);
camif_write(vp->camif, S3C_CAMIF_REG_CIGCTRL, cfg);
}
/*
* Sets video test pattern (off, color bar, horizontal or vertical gradient).
* External sensor pixel clock must be active for the test pattern to work.
*/
void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern)
{
u32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
cfg &= ~CIGCTRL_TESTPATTERN_MASK;
cfg |= (pattern << 27);
camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg);
}
void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect,
unsigned int cr, unsigned int cb)
{
static const struct v4l2_control colorfx[] = {
{ V4L2_COLORFX_NONE, CIIMGEFF_FIN_BYPASS },
{ V4L2_COLORFX_BW, CIIMGEFF_FIN_ARBITRARY },
{ V4L2_COLORFX_SEPIA, CIIMGEFF_FIN_ARBITRARY },
{ V4L2_COLORFX_NEGATIVE, CIIMGEFF_FIN_NEGATIVE },
{ V4L2_COLORFX_ART_FREEZE, CIIMGEFF_FIN_ARTFREEZE },
{ V4L2_COLORFX_EMBOSS, CIIMGEFF_FIN_EMBOSSING },
{ V4L2_COLORFX_SILHOUETTE, CIIMGEFF_FIN_SILHOUETTE },
{ V4L2_COLORFX_SET_CBCR, CIIMGEFF_FIN_ARBITRARY },
};
unsigned int i, cfg;
for (i = 0; i < ARRAY_SIZE(colorfx); i++)
if (colorfx[i].id == effect)
break;
if (i == ARRAY_SIZE(colorfx))
return;
cfg = camif_read(camif, S3C_CAMIF_REG_CIIMGEFF(camif->vp->offset));
/* Set effect */
cfg &= ~CIIMGEFF_FIN_MASK;
cfg |= colorfx[i].value;
/* Set both paths */
if (camif->variant->ip_revision >= S3C6400_CAMIF_IP_REV) {
if (effect == V4L2_COLORFX_NONE)
cfg &= ~CIIMGEFF_IE_ENABLE_MASK;
else
cfg |= CIIMGEFF_IE_ENABLE_MASK;
}
cfg &= ~CIIMGEFF_PAT_CBCR_MASK;
cfg |= cr | (cb << 13);
camif_write(camif, S3C_CAMIF_REG_CIIMGEFF(camif->vp->offset), cfg);
}
static const u32 src_pixfmt_map[8][2] = {
{ V4L2_MBUS_FMT_YUYV8_2X8, CISRCFMT_ORDER422_YCBYCR },
{ V4L2_MBUS_FMT_YVYU8_2X8, CISRCFMT_ORDER422_YCRYCB },
{ V4L2_MBUS_FMT_UYVY8_2X8, CISRCFMT_ORDER422_CBYCRY },
{ V4L2_MBUS_FMT_VYUY8_2X8, CISRCFMT_ORDER422_CRYCBY },
};
/* Set camera input pixel format and resolution */
void camif_hw_set_source_format(struct camif_dev *camif)
{
struct v4l2_mbus_framefmt *mf = &camif->mbus_fmt;
unsigned int i = ARRAY_SIZE(src_pixfmt_map);
u32 cfg;
while (i-- >= 0) {
if (src_pixfmt_map[i][0] == mf->code)
break;
}
if (i == 0 && src_pixfmt_map[i][0] != mf->code) {
dev_err(camif->dev,
"Unsupported pixel code, falling back to %#08x\n",
src_pixfmt_map[i][0]);
}
cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT);
cfg &= ~(CISRCFMT_ORDER422_MASK | CISRCFMT_SIZE_CAM_MASK);
cfg |= (mf->width << 16) | mf->height;
cfg |= src_pixfmt_map[i][1];
camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg);
}
/* Set the camera host input window offsets (cropping) */
void camif_hw_set_camera_crop(struct camif_dev *camif)
{
struct v4l2_mbus_framefmt *mf = &camif->mbus_fmt;
struct v4l2_rect *crop = &camif->camif_crop;
u32 hoff2, voff2;
u32 cfg;
/* Note: s3c244x requirement: left = f_width - rect.width / 2 */
cfg = camif_read(camif, S3C_CAMIF_REG_CIWDOFST);
cfg &= ~(CIWDOFST_OFST_MASK | CIWDOFST_WINOFSEN);
cfg |= (crop->left << 16) | crop->top;
if (crop->left != 0 || crop->top != 0)
cfg |= CIWDOFST_WINOFSEN;
camif_write(camif, S3C_CAMIF_REG_CIWDOFST, cfg);
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV) {
hoff2 = mf->width - crop->width - crop->left;
voff2 = mf->height - crop->height - crop->top;
cfg = (hoff2 << 16) | voff2;
camif_write(camif, S3C_CAMIF_REG_CIWDOFST2, cfg);
}
}
void camif_hw_clear_fifo_overflow(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
u32 cfg;
cfg = camif_read(camif, S3C_CAMIF_REG_CIWDOFST);
if (vp->id == 0)
cfg |= (CIWDOFST_CLROVCOFIY | CIWDOFST_CLROVCOFICB |
CIWDOFST_CLROVCOFICR);
else
cfg |= (/* CIWDOFST_CLROVPRFIY | */ CIWDOFST_CLROVPRFICB |
CIWDOFST_CLROVPRFICR);
camif_write(camif, S3C_CAMIF_REG_CIWDOFST, cfg);
}
/* Set video bus signals polarity */
void camif_hw_set_camera_bus(struct camif_dev *camif)
{
unsigned int flags = camif->pdata.sensor.flags;
u32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
cfg &= ~(CIGCTRL_INVPOLPCLK | CIGCTRL_INVPOLVSYNC |
CIGCTRL_INVPOLHREF | CIGCTRL_INVPOLFIELD);
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CIGCTRL_INVPOLPCLK;
if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
cfg |= CIGCTRL_INVPOLVSYNC;
/*
* HREF is normally high during frame active data
* transmission and low during horizontal synchronization
* period. Thus HREF active high means HSYNC active low.
*/
if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
cfg |= CIGCTRL_INVPOLHREF; /* HREF active low */
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV) {
if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
cfg |= CIGCTRL_INVPOLFIELD;
cfg |= CIGCTRL_FIELDMODE;
}
pr_debug("Setting CIGCTRL to: %#x\n", cfg);
camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg);
}
void camif_hw_set_output_addr(struct camif_vp *vp,
struct camif_addr *paddr, int i)
{
struct camif_dev *camif = vp->camif;
camif_write(camif, S3C_CAMIF_REG_CIYSA(vp->id, i), paddr->y);
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV
|| vp->id == VP_CODEC) {
camif_write(camif, S3C_CAMIF_REG_CICBSA(vp->id, i),
paddr->cb);
camif_write(camif, S3C_CAMIF_REG_CICRSA(vp->id, i),
paddr->cr);
}
pr_debug("dst_buf[%d]: %#X, cb: %#X, cr: %#X\n",
i, paddr->y, paddr->cb, paddr->cr);
}
static void camif_hw_set_out_dma_size(struct camif_vp *vp)
{
struct camif_frame *frame = &vp->out_frame;
u32 cfg;
cfg = camif_read(vp->camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset));
cfg &= ~CITRGFMT_TARGETSIZE_MASK;
cfg |= (frame->f_width << 16) | frame->f_height;
camif_write(vp->camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset), cfg);
}
static void camif_get_dma_burst(u32 width, u32 ybpp, u32 *mburst, u32 *rburst)
{
unsigned int nwords = width * ybpp / 4;
unsigned int div, rem;
if (WARN_ON(width < 8 || (width * ybpp) & 7))
return;
for (div = 16; div >= 2; div /= 2) {
if (nwords < div)
continue;
rem = nwords & (div - 1);
if (rem == 0) {
*mburst = div;
*rburst = div;
break;
}
if (rem == div / 2 || rem == div / 4) {
*mburst = div;
*rburst = rem;
break;
}
}
}
void camif_hw_set_output_dma(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
struct camif_frame *frame = &vp->out_frame;
const struct camif_fmt *fmt = vp->out_fmt;
unsigned int ymburst = 0, yrburst = 0;
u32 cfg;
camif_hw_set_out_dma_size(vp);
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV) {
struct camif_dma_offset *offset = &frame->dma_offset;
/* Set the input dma offsets. */
cfg = S3C_CISS_OFFS_INITIAL(offset->initial);
cfg |= S3C_CISS_OFFS_LINE(offset->line);
camif_write(camif, S3C_CAMIF_REG_CISSY(vp->id), cfg);
camif_write(camif, S3C_CAMIF_REG_CISSCB(vp->id), cfg);
camif_write(camif, S3C_CAMIF_REG_CISSCR(vp->id), cfg);
}
/* Configure DMA burst values */
camif_get_dma_burst(frame->rect.width, fmt->ybpp, &ymburst, &yrburst);
cfg = camif_read(camif, S3C_CAMIF_REG_CICTRL(vp->id, vp->offset));
cfg &= ~CICTRL_BURST_MASK;
cfg |= CICTRL_YBURST1(ymburst) | CICTRL_YBURST2(yrburst);
cfg |= CICTRL_CBURST1(ymburst / 2) | CICTRL_CBURST2(yrburst / 2);
camif_write(camif, S3C_CAMIF_REG_CICTRL(vp->id, vp->offset), cfg);
pr_debug("ymburst: %u, yrburst: %u\n", ymburst, yrburst);
}
void camif_hw_set_input_path(struct camif_vp *vp)
{
u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_MSCTRL(vp->id));
cfg &= ~MSCTRL_SEL_DMA_CAM;
camif_write(vp->camif, S3C_CAMIF_REG_MSCTRL(vp->id), cfg);
}
void camif_hw_set_target_format(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
struct camif_frame *frame = &vp->out_frame;
u32 cfg;
pr_debug("fw: %d, fh: %d color: %d\n", frame->f_width,
frame->f_height, vp->out_fmt->color);
cfg = camif_read(camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset));
cfg &= ~CITRGFMT_TARGETSIZE_MASK;
if (camif->variant->ip_revision == S3C244X_CAMIF_IP_REV) {
/* We currently support only YCbCr 4:2:2 at the camera input */
cfg |= CITRGFMT_IN422;
cfg &= ~CITRGFMT_OUT422;
if (vp->out_fmt->color == IMG_FMT_YCBCR422P)
cfg |= CITRGFMT_OUT422;
} else {
cfg &= ~CITRGFMT_OUTFORMAT_MASK;
switch (vp->out_fmt->color) {
case IMG_FMT_RGB565...IMG_FMT_XRGB8888:
cfg |= CITRGFMT_OUTFORMAT_RGB;
break;
case IMG_FMT_YCBCR420...IMG_FMT_YCRCB420:
cfg |= CITRGFMT_OUTFORMAT_YCBCR420;
break;
case IMG_FMT_YCBCR422P:
cfg |= CITRGFMT_OUTFORMAT_YCBCR422;
break;
case IMG_FMT_YCBYCR422...IMG_FMT_CRYCBY422:
cfg |= CITRGFMT_OUTFORMAT_YCBCR422I;
break;
}
}
/* Rotation is only supported by s3c64xx */
if (vp->rotation == 90 || vp->rotation == 270)
cfg |= (frame->f_height << 16) | frame->f_width;
else
cfg |= (frame->f_width << 16) | frame->f_height;
camif_write(camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset), cfg);
/* Target area, output pixel width * height */
cfg = camif_read(camif, S3C_CAMIF_REG_CITAREA(vp->id, vp->offset));
cfg &= ~CITAREA_MASK;
cfg |= (frame->f_width * frame->f_height);
camif_write(camif, S3C_CAMIF_REG_CITAREA(vp->id, vp->offset), cfg);
}
void camif_hw_set_flip(struct camif_vp *vp)
{
u32 cfg = camif_read(vp->camif,
S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset));
cfg &= ~CITRGFMT_FLIP_MASK;
if (vp->hflip)
cfg |= CITRGFMT_FLIP_Y_MIRROR;
if (vp->vflip)
cfg |= CITRGFMT_FLIP_X_MIRROR;
camif_write(vp->camif, S3C_CAMIF_REG_CITRGFMT(vp->id, vp->offset), cfg);
}
static void camif_hw_set_prescaler(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
struct camif_scaler *sc = &vp->scaler;
u32 cfg, shfactor, addr;
addr = S3C_CAMIF_REG_CISCPRERATIO(vp->id, vp->offset);
shfactor = 10 - (sc->h_shift + sc->v_shift);
cfg = shfactor << 28;
cfg |= (sc->pre_h_ratio << 16) | sc->pre_v_ratio;
camif_write(camif, addr, cfg);
cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
camif_write(camif, S3C_CAMIF_REG_CISCPREDST(vp->id, vp->offset), cfg);
}
void camif_s3c244x_hw_set_scaler(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
struct camif_scaler *scaler = &vp->scaler;
unsigned int color = vp->out_fmt->color;
u32 cfg;
camif_hw_set_prescaler(vp);
cfg = camif_read(camif, S3C_CAMIF_REG_CISCCTRL(vp->id, vp->offset));
cfg &= ~(CISCCTRL_SCALEUP_MASK | CISCCTRL_SCALERBYPASS |
CISCCTRL_MAIN_RATIO_MASK | CIPRSCCTRL_RGB_FORMAT_24BIT);
if (scaler->enable) {
if (scaler->scaleup_h) {
if (vp->id == VP_CODEC)
cfg |= CISCCTRL_SCALEUP_H;
else
cfg |= CIPRSCCTRL_SCALEUP_H;
}
if (scaler->scaleup_v) {
if (vp->id == VP_CODEC)
cfg |= CISCCTRL_SCALEUP_V;
else
cfg |= CIPRSCCTRL_SCALEUP_V;
}
} else {
if (vp->id == VP_CODEC)
cfg |= CISCCTRL_SCALERBYPASS;
}
cfg |= ((scaler->main_h_ratio & 0x1ff) << 16);
cfg |= scaler->main_v_ratio & 0x1ff;
if (vp->id == VP_PREVIEW) {
if (color == IMG_FMT_XRGB8888)
cfg |= CIPRSCCTRL_RGB_FORMAT_24BIT;
cfg |= CIPRSCCTRL_SAMPLE;
}
camif_write(camif, S3C_CAMIF_REG_CISCCTRL(vp->id, vp->offset), cfg);
pr_debug("main: h_ratio: %#x, v_ratio: %#x",
scaler->main_h_ratio, scaler->main_v_ratio);
}
void camif_s3c64xx_hw_set_scaler(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
struct camif_scaler *scaler = &vp->scaler;
unsigned int color = vp->out_fmt->color;
u32 cfg;
camif_hw_set_prescaler(vp);
cfg = camif_read(camif, S3C_CAMIF_REG_CISCCTRL(vp->id, vp->offset));
cfg &= ~(CISCCTRL_CSCR2Y_WIDE | CISCCTRL_CSCY2R_WIDE
| CISCCTRL_SCALEUP_H | CISCCTRL_SCALEUP_V
| CISCCTRL_SCALERBYPASS | CISCCTRL_ONE2ONE
| CISCCTRL_INRGB_FMT_MASK | CISCCTRL_OUTRGB_FMT_MASK
| CISCCTRL_INTERLACE | CISCCTRL_EXTRGB_EXTENSION
| CISCCTRL_MAIN_RATIO_MASK);
cfg |= (CISCCTRL_CSCR2Y_WIDE | CISCCTRL_CSCY2R_WIDE);
if (!scaler->enable) {
cfg |= CISCCTRL_SCALERBYPASS;
} else {
if (scaler->scaleup_h)
cfg |= CISCCTRL_SCALEUP_H;
if (scaler->scaleup_v)
cfg |= CISCCTRL_SCALEUP_V;
if (scaler->copy)
cfg |= CISCCTRL_ONE2ONE;
}
switch (color) {
case IMG_FMT_RGB666:
cfg |= CISCCTRL_OUTRGB_FMT_RGB666;
break;
case IMG_FMT_XRGB8888:
cfg |= CISCCTRL_OUTRGB_FMT_RGB888;
break;
}
cfg |= (scaler->main_h_ratio & 0x1ff) << 16;
cfg |= scaler->main_v_ratio & 0x1ff;
camif_write(camif, S3C_CAMIF_REG_CISCCTRL(vp->id, vp->offset), cfg);
pr_debug("main: h_ratio: %#x, v_ratio: %#x",
scaler->main_h_ratio, scaler->main_v_ratio);
}
void camif_hw_set_scaler(struct camif_vp *vp)
{
unsigned int ip_rev = vp->camif->variant->ip_revision;
if (ip_rev == S3C244X_CAMIF_IP_REV)
camif_s3c244x_hw_set_scaler(vp);
else
camif_s3c64xx_hw_set_scaler(vp);
}
void camif_hw_enable_scaler(struct camif_vp *vp, bool on)
{
u32 addr = S3C_CAMIF_REG_CISCCTRL(vp->id, vp->offset);
u32 cfg;
cfg = camif_read(vp->camif, addr);
if (on)
cfg |= CISCCTRL_SCALERSTART;
else
cfg &= ~CISCCTRL_SCALERSTART;
camif_write(vp->camif, addr, cfg);
}
void camif_hw_set_lastirq(struct camif_vp *vp, int enable)
{
u32 addr = S3C_CAMIF_REG_CICTRL(vp->id, vp->offset);
u32 cfg;
cfg = camif_read(vp->camif, addr);
if (enable)
cfg |= CICTRL_LASTIRQ_ENABLE;
else
cfg &= ~CICTRL_LASTIRQ_ENABLE;
camif_write(vp->camif, addr, cfg);
}
void camif_hw_enable_capture(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
u32 cfg;
cfg = camif_read(camif, S3C_CAMIF_REG_CIIMGCPT(vp->offset));
camif->stream_count++;
if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV)
cfg |= CIIMGCPT_CPT_FREN_ENABLE(vp->id);
if (vp->scaler.enable)
cfg |= CIIMGCPT_IMGCPTEN_SC(vp->id);
if (camif->stream_count == 1)
cfg |= CIIMGCPT_IMGCPTEN;
camif_write(camif, S3C_CAMIF_REG_CIIMGCPT(vp->offset), cfg);
pr_debug("CIIMGCPT: %#x, camif->stream_count: %d\n",
cfg, camif->stream_count);
}
void camif_hw_disable_capture(struct camif_vp *vp)
{
struct camif_dev *camif = vp->camif;
u32 cfg;
cfg = camif_read(camif, S3C_CAMIF_REG_CIIMGCPT(vp->offset));
cfg &= ~CIIMGCPT_IMGCPTEN_SC(vp->id);
if (WARN_ON(--(camif->stream_count) < 0))
camif->stream_count = 0;
if (camif->stream_count == 0)
cfg &= ~CIIMGCPT_IMGCPTEN;
pr_debug("CIIMGCPT: %#x, camif->stream_count: %d\n",
cfg, camif->stream_count);
camif_write(camif, S3C_CAMIF_REG_CIIMGCPT(vp->offset), cfg);
}
void camif_hw_dump_regs(struct camif_dev *camif, const char *label)
{
struct {
u32 offset;
const char * const name;
} registers[] = {
{ S3C_CAMIF_REG_CISRCFMT, "CISRCFMT" },
{ S3C_CAMIF_REG_CIWDOFST, "CIWDOFST" },
{ S3C_CAMIF_REG_CIGCTRL, "CIGCTRL" },
{ S3C_CAMIF_REG_CIWDOFST2, "CIWDOFST2" },
{ S3C_CAMIF_REG_CIYSA(0, 0), "CICOYSA0" },
{ S3C_CAMIF_REG_CICBSA(0, 0), "CICOCBSA0" },
{ S3C_CAMIF_REG_CICRSA(0, 0), "CICOCRSA0" },
{ S3C_CAMIF_REG_CIYSA(0, 1), "CICOYSA1" },
{ S3C_CAMIF_REG_CICBSA(0, 1), "CICOCBSA1" },
{ S3C_CAMIF_REG_CICRSA(0, 1), "CICOCRSA1" },
{ S3C_CAMIF_REG_CIYSA(0, 2), "CICOYSA2" },
{ S3C_CAMIF_REG_CICBSA(0, 2), "CICOCBSA2" },
{ S3C_CAMIF_REG_CICRSA(0, 2), "CICOCRSA2" },
{ S3C_CAMIF_REG_CIYSA(0, 3), "CICOYSA3" },
{ S3C_CAMIF_REG_CICBSA(0, 3), "CICOCBSA3" },
{ S3C_CAMIF_REG_CICRSA(0, 3), "CICOCRSA3" },
{ S3C_CAMIF_REG_CIYSA(1, 0), "CIPRYSA0" },
{ S3C_CAMIF_REG_CIYSA(1, 1), "CIPRYSA1" },
{ S3C_CAMIF_REG_CIYSA(1, 2), "CIPRYSA2" },
{ S3C_CAMIF_REG_CIYSA(1, 3), "CIPRYSA3" },
{ S3C_CAMIF_REG_CITRGFMT(0, 0), "CICOTRGFMT" },
{ S3C_CAMIF_REG_CITRGFMT(1, 0), "CIPRTRGFMT" },
{ S3C_CAMIF_REG_CICTRL(0, 0), "CICOCTRL" },
{ S3C_CAMIF_REG_CICTRL(1, 0), "CIPRCTRL" },
{ S3C_CAMIF_REG_CISCPREDST(0, 0), "CICOSCPREDST" },
{ S3C_CAMIF_REG_CISCPREDST(1, 0), "CIPRSCPREDST" },
{ S3C_CAMIF_REG_CISCPRERATIO(0, 0), "CICOSCPRERATIO" },
{ S3C_CAMIF_REG_CISCPRERATIO(1, 0), "CIPRSCPRERATIO" },
{ S3C_CAMIF_REG_CISCCTRL(0, 0), "CICOSCCTRL" },
{ S3C_CAMIF_REG_CISCCTRL(1, 0), "CIPRSCCTRL" },
{ S3C_CAMIF_REG_CITAREA(0, 0), "CICOTAREA" },
{ S3C_CAMIF_REG_CITAREA(1, 0), "CIPRTAREA" },
{ S3C_CAMIF_REG_CISTATUS(0, 0), "CICOSTATUS" },
{ S3C_CAMIF_REG_CISTATUS(1, 0), "CIPRSTATUS" },
{ S3C_CAMIF_REG_CIIMGCPT(0), "CIIMGCPT" },
};
u32 i;
pr_info("--- %s ---\n", label);
for (i = 0; i < ARRAY_SIZE(registers); i++) {
u32 cfg = readl(camif->io_base + registers[i].offset);
printk(KERN_INFO "%s:\t0x%08x\n", registers[i].name, cfg);
}
}

269
drivers/media/platform/s3c-camif/camif-regs.h Normal file
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/*
* Register definition file for s3c24xx/s3c64xx SoC CAMIF driver
*
* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
* Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef CAMIF_REGS_H_
#define CAMIF_REGS_H_
#include "camif-core.h"
#include <media/s3c_camif.h>
/*
* The id argument indicates the processing path:
* id = 0 - codec (FIMC C), 1 - preview (FIMC P).
*/
/* Camera input format */
#define S3C_CAMIF_REG_CISRCFMT 0x00
#define CISRCFMT_ITU601_8BIT (1 << 31)
#define CISRCFMT_ITU656_8BIT (0 << 31)
#define CISRCFMT_ORDER422_YCBYCR (0 << 14)
#define CISRCFMT_ORDER422_YCRYCB (1 << 14)
#define CISRCFMT_ORDER422_CBYCRY (2 << 14)
#define CISRCFMT_ORDER422_CRYCBY (3 << 14)
#define CISRCFMT_ORDER422_MASK (3 << 14)
#define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff)
/* Window offset */
#define S3C_CAMIF_REG_CIWDOFST 0x04
#define CIWDOFST_WINOFSEN (1 << 31)
#define CIWDOFST_CLROVCOFIY (1 << 30)
#define CIWDOFST_CLROVRLB_PR (1 << 28)
/* #define CIWDOFST_CLROVPRFIY (1 << 27) */
#define CIWDOFST_CLROVCOFICB (1 << 15)
#define CIWDOFST_CLROVCOFICR (1 << 14)
#define CIWDOFST_CLROVPRFICB (1 << 13)
#define CIWDOFST_CLROVPRFICR (1 << 12)
#define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
/* Window offset 2 */
#define S3C_CAMIF_REG_CIWDOFST2 0x14
#define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff)
/* Global control */
#define S3C_CAMIF_REG_CIGCTRL 0x08
#define CIGCTRL_SWRST (1 << 31)
#define CIGCTRL_CAMRST (1 << 30)
#define CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
#define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
#define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
#define CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
#define CIGCTRL_TESTPATTERN_MASK (3 << 27)
#define CIGCTRL_INVPOLPCLK (1 << 26)
#define CIGCTRL_INVPOLVSYNC (1 << 25)
#define CIGCTRL_INVPOLHREF (1 << 24)
#define CIGCTRL_IRQ_OVFEN (1 << 22)
#define CIGCTRL_HREF_MASK (1 << 21)
#define CIGCTRL_IRQ_LEVEL (1 << 20)
/* IRQ_CLR_C, IRQ_CLR_P */
#define CIGCTRL_IRQ_CLR(id) (1 << (19 - (id)))
#define CIGCTRL_FIELDMODE (1 << 2)
#define CIGCTRL_INVPOLFIELD (1 << 1)
#define CIGCTRL_CAM_INTERLACE (1 << 0)
/* Y DMA output frame start address. n = 0..3. */
#define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4)
/* Cb plane output DMA start address. n = 0..3. Only codec path. */
#define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4)
/* Cr plane output DMA start address. n = 0..3. Only codec path. */
#define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4)
/* CICOTRGFMT, CIPRTRGFMT - Target format */
#define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs)))
#define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */
#define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */
#define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */
#define CITRGFMT_TARGETHSIZE(x) ((x) << 16)
#define CITRGFMT_FLIP_NORMAL (0 << 14)
#define CITRGFMT_FLIP_X_MIRROR (1 << 14)
#define CITRGFMT_FLIP_Y_MIRROR (2 << 14)
#define CITRGFMT_FLIP_180 (3 << 14)
#define CITRGFMT_FLIP_MASK (3 << 14)
/* Preview path only */
#define CITRGFMT_ROT90_PR (1 << 13)
#define CITRGFMT_TARGETVSIZE(x) ((x) << 0)
#define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff)
/* CICOCTRL, CIPRCTRL. Output DMA control. */
#define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs)))
#define CICTRL_BURST_MASK (0xfffff << 4)
/* xBURSTn - 5-bits width */
#define CICTRL_YBURST1(x) ((x) << 19)
#define CICTRL_YBURST2(x) ((x) << 14)
#define CICTRL_RGBBURST1(x) ((x) << 19)
#define CICTRL_RGBBURST2(x) ((x) << 14)
#define CICTRL_CBURST1(x) ((x) << 9)
#define CICTRL_CBURST2(x) ((x) << 4)
#define CICTRL_LASTIRQ_ENABLE (1 << 2)
#define CICTRL_ORDER422_MASK (3 << 0)
/* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
#define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs)))
/* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
#define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs)))
/* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
#define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs)))
#define CISCCTRL_SCALERBYPASS (1 << 31)
/* s3c244x preview path only, s3c64xx both */
#define CIPRSCCTRL_SAMPLE (1 << 31)
/* 0 - 16-bit RGB, 1 - 24-bit RGB */
#define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */
#define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */
#define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */
/* s3c64xx */
#define CISCCTRL_SCALEUP_H (1 << 30)
#define CISCCTRL_SCALEUP_V (1 << 29)
#define CISCCTRL_SCALEUP_MASK (0x3 << 29)
#define CISCCTRL_CSCR2Y_WIDE (1 << 28)
#define CISCCTRL_CSCY2R_WIDE (1 << 27)
#define CISCCTRL_LCDPATHEN_FIFO (1 << 26)
#define CISCCTRL_INTERLACE (1 << 25)
#define CISCCTRL_SCALERSTART (1 << 15)
#define CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
#define CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
#define CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
#define CISCCTRL_INRGB_FMT_MASK (3 << 13)
#define CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
#define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
#define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
#define CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
#define CISCCTRL_EXTRGB_EXTENSION (1 << 10)
#define CISCCTRL_ONE2ONE (1 << 9)
#define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff)
/* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
#define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs)))
#define CITAREA_MASK 0xfffffff
/* Codec (id = 0) or preview (id = 1) path status. */
#define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs)))
#define CISTATUS_OVFIY_STATUS (1 << 31)
#define CISTATUS_OVFICB_STATUS (1 << 30)
#define CISTATUS_OVFICR_STATUS (1 << 29)
#define CISTATUS_OVF_MASK (0x7 << 29)
#define CIPRSTATUS_OVF_MASK (0x3 << 30)
#define CISTATUS_VSYNC_STATUS (1 << 28)
#define CISTATUS_FRAMECNT_MASK (3 << 26)
#define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3)
#define CISTATUS_WINOFSTEN_STATUS (1 << 25)
#define CISTATUS_IMGCPTEN_STATUS (1 << 22)
#define CISTATUS_IMGCPTENSC_STATUS (1 << 21)
#define CISTATUS_VSYNC_A_STATUS (1 << 20)
#define CISTATUS_FRAMEEND_STATUS (1 << 19) /* 17 on s3c64xx */
/* Image capture enable */
#define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs))
#define CIIMGCPT_IMGCPTEN (1 << 31)
#define CIIMGCPT_IMGCPTEN_SC(id) (1 << (30 - (id)))
/* Frame control: 1 - one-shot, 0 - free run */
#define CIIMGCPT_CPT_FREN_ENABLE(id) (1 << (25 - (id)))
#define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18)
#define CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
/* Capture sequence */
#define S3C_CAMIF_REG_CICPTSEQ 0xc4
/* Image effects */
#define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs))
#define CIIMGEFF_IE_ENABLE(id) (1 << (30 + (id)))
#define CIIMGEFF_IE_ENABLE_MASK (3 << 30)
/* Image effect: 1 - after scaler, 0 - before scaler */
#define CIIMGEFF_IE_AFTER_SC (1 << 29)
#define CIIMGEFF_FIN_MASK (7 << 26)
#define CIIMGEFF_FIN_BYPASS (0 << 26)
#define CIIMGEFF_FIN_ARBITRARY (1 << 26)
#define CIIMGEFF_FIN_NEGATIVE (2 << 26)
#define CIIMGEFF_FIN_ARTFREEZE (3 << 26)
#define CIIMGEFF_FIN_EMBOSSING (4 << 26)
#define CIIMGEFF_FIN_SILHOUETTE (5 << 26)
#define CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
#define CIIMGEFF_PAT_CB(x) ((x) << 13)
#define CIIMGEFF_PAT_CR(x) (x)
/* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */
#define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCR0SA(id) (0xdc + ((id) * 0x2c))
/* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */
#define S3C_CAMIF_REG_MSY0END(id) (0xe0 + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCB0END(id) (0xe4 + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCR0END(id) (0xe8 + ((id) * 0x2c))
/* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */
#define S3C_CAMIF_REG_MSYOFF(id) (0x118 + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCBOFF(id) (0x11c + ((id) * 0x2c))
#define S3C_CAMIF_REG_MSCROFF(id) (0x120 + ((id) * 0x2c))
/* Real input DMA data size. n = 0 - codec, 1 - preview. */
#define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c)
#define AUTOLOAD_ENABLE (1 << 31)
#define ADDR_CH_DIS (1 << 30)
#define MSHEIGHT(x) (((x) & 0x3ff) << 16)
#define MSWIDTH(x) ((x) & 0x3ff)
/* Input DMA control. n = 0 - codec, 1 - preview */
#define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c)
#define MSCTRL_ORDER422_M_YCBYCR (0 << 4)
#define MSCTRL_ORDER422_M_YCRYCB (1 << 4)
#define MSCTRL_ORDER422_M_CBYCRY (2 << 4)
#define MSCTRL_ORDER422_M_CRYCBY (3 << 4)
/* 0 - camera, 1 - DMA */
#define MSCTRL_SEL_DMA_CAM (1 << 3)
#define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1)
#define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1)
#define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1)
#define MSCTRL_INFORMAT_M_RGB (3 << 1)
#define MSCTRL_ENVID_M (1 << 0)
/* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
#define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c)
#define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c)
#define S3C_CAMIF_REG_CISSCR(id) (0x134 + (id) * 0x0c)
#define S3C_CISS_OFFS_INITIAL(x) ((x) << 16)
#define S3C_CISS_OFFS_LINE(x) ((x) << 0)
/* ------------------------------------------------------------------ */
void camif_hw_reset(struct camif_dev *camif);
void camif_hw_clear_pending_irq(struct camif_vp *vp);
void camif_hw_clear_fifo_overflow(struct camif_vp *vp);
void camif_hw_set_lastirq(struct camif_vp *vp, int enable);
void camif_hw_set_input_path(struct camif_vp *vp);
void camif_hw_enable_scaler(struct camif_vp *vp, bool on);
void camif_hw_enable_capture(struct camif_vp *vp);
void camif_hw_disable_capture(struct camif_vp *vp);
void camif_hw_set_camera_bus(struct camif_dev *camif);
void camif_hw_set_source_format(struct camif_dev *camif);
void camif_hw_set_camera_crop(struct camif_dev *camif);
void camif_hw_set_scaler(struct camif_vp *vp);
void camif_hw_set_flip(struct camif_vp *vp);
void camif_hw_set_output_dma(struct camif_vp *vp);
void camif_hw_set_target_format(struct camif_vp *vp);
void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern);
void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect,
unsigned int cr, unsigned int cb);
void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr,
int index);
void camif_hw_dump_regs(struct camif_dev *camif, const char *label);
static inline u32 camif_hw_get_status(struct camif_vp *vp)
{
return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
vp->offset));
}
#endif /* CAMIF_REGS_H_ */

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include/media/s3c_camif.h Normal file
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/*
* s3c24xx/s3c64xx SoC series Camera Interface (CAMIF) driver
*
* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MEDIA_S3C_CAMIF_
#define MEDIA_S3C_CAMIF_
#include <linux/i2c.h>
#include <media/v4l2-mediabus.h>
/**
* struct s3c_camif_sensor_info - an image sensor description
* @i2c_board_info: pointer to an I2C sensor subdevice board info
* @clock_frequency: frequency of the clock the host provides to a sensor
* @mbus_type: media bus type
* @i2c_bus_num: i2c control bus id the sensor is attached to
* @flags: the parallel bus flags defining signals polarity (V4L2_MBUS_*)
* @use_field: 1 if parallel bus FIELD signal is used (only s3c64xx)
*/
struct s3c_camif_sensor_info {
struct i2c_board_info i2c_board_info;
unsigned long clock_frequency;
enum v4l2_mbus_type mbus_type;
u16 i2c_bus_num;
u16 flags;
u8 use_field;
};
struct s3c_camif_plat_data {
struct s3c_camif_sensor_info sensor;
int (*gpio_get)(void);
int (*gpio_put)(void);
};
/* Platform default helper functions */
int s3c_camif_gpio_get(void);
int s3c_camif_gpio_put(void);
#endif /* MEDIA_S3C_CAMIF_ */