arm-soc: soc-specific updates
This is a larger set of new functionality for the existing SoC families,
including:
* vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850
* prima2 gains support for the "marco" SoC family, its SMP based cousin
* tegra gains support for the new Tegra4 (Tegra114) family
* socfpga now supports a newer version of the hardware including SMP
* i.mx31 and bcm2835 are now using DT probing for their clocks
* lots of updates for sh-mobile
* OMAP updates for clocks, power management and USB
* i.mx6q and tegra now support cpuidle
* kirkwood now supports PCIe hot plugging
* tegra clock support is updated
* tegra USB PHY probing gets implemented diffently
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
This commit is contained in:
Linus Torvalds
commit
bab588fcfb
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@ -3,9 +3,11 @@ Altera SOCFPGA System Manager
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible : "altr,sys-mgr"
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- compatible : "altr,sys-mgr"
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||||||
- reg : Should contain 1 register ranges(address and length)
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- reg : Should contain 1 register ranges(address and length)
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||||||
|
- cpu1-start-addr : CPU1 start address in hex.
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||||||
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||||||
Example:
|
Example:
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||||||
sysmgr@ffd08000 {
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sysmgr@ffd08000 {
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||||||
compatible = "altr,sys-mgr";
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compatible = "altr,sys-mgr";
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reg = <0xffd08000 0x1000>;
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reg = <0xffd08000 0x1000>;
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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@ -1,3 +1,9 @@
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||||||
prima2 "cb" evaluation board
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CSR SiRFprimaII and SiRFmarco device tree bindings.
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||||||
|
========================================
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||||||
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||||||
Required root node properties:
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Required root node properties:
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||||||
- compatible = "sirf,prima2-cb", "sirf,prima2";
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- compatible:
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||||||
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- "sirf,prima2-cb" : prima2 "cb" evaluation board
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- "sirf,marco-cb" : marco "cb" evaluation board
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- "sirf,prima2" : prima2 device based board
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- "sirf,marco" : marco device based board
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||||||
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@ -12,3 +12,11 @@ compatible = "wm,wm8505";
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||||||
Boards with the Wondermedia WM8650 SoC shall have the following properties:
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Boards with the Wondermedia WM8650 SoC shall have the following properties:
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||||||
Required root node property:
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Required root node property:
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||||||
compatible = "wm,wm8650";
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compatible = "wm,wm8650";
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||||||
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||||||
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Boards with the Wondermedia WM8750 SoC shall have the following properties:
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||||||
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Required root node property:
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||||||
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compatible = "wm,wm8750";
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||||||
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Boards with the Wondermedia WM8850 SoC shall have the following properties:
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||||||
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Required root node property:
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||||||
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compatible = "wm,wm8850";
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||||||
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@ -0,0 +1,91 @@
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* Clock bindings for Freescale i.MX31
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||||||
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Required properties:
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||||||
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- compatible: Should be "fsl,imx31-ccm"
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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||||||
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX31
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clocks and IDs.
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||||||
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Clock ID
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||||||
|
-----------------------
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||||||
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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upll 5
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mcu_main 6
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hsp 7
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ahb 8
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nfc 9
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ipg 10
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per_div 11
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per 12
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csi_sel 13
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fir_sel 14
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csi_div 15
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usb_div_pre 16
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usb_div_post 17
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fir_div_pre 18
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fir_div_post 19
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sdhc1_gate 20
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sdhc2_gate 21
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gpt_gate 22
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epit1_gate 23
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epit2_gate 24
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iim_gate 25
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ata_gate 26
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sdma_gate 27
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cspi3_gate 28
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||||||
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rng_gate 29
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uart1_gate 30
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uart2_gate 31
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ssi1_gate 32
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i2c1_gate 33
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i2c2_gate 34
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i2c3_gate 35
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||||||
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hantro_gate 36
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||||||
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mstick1_gate 37
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||||||
|
mstick2_gate 38
|
||||||
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csi_gate 39
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||||||
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rtc_gate 40
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||||||
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wdog_gate 41
|
||||||
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pwm_gate 42
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||||||
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sim_gate 43
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||||||
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ect_gate 44
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||||||
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usb_gate 45
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||||||
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kpp_gate 46
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||||||
|
ipu_gate 47
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||||||
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uart3_gate 48
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||||||
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uart4_gate 49
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||||||
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uart5_gate 50
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||||||
|
owire_gate 51
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||||||
|
ssi2_gate 52
|
||||||
|
cspi1_gate 53
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||||||
|
cspi2_gate 54
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||||||
|
gacc_gate 55
|
||||||
|
emi_gate 56
|
||||||
|
rtic_gate 57
|
||||||
|
firi_gate 58
|
||||||
|
|
||||||
|
Examples:
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||||||
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||||||
|
clks: ccm@53f80000{
|
||||||
|
compatible = "fsl,imx31-ccm";
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||||||
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reg = <0x53f80000 0x4000>;
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||||||
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interrupts = <0 31 0x04 0 53 0x04>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
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|
||||||
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uart1: serial@43f90000 {
|
||||||
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
|
reg = <0x43f90000 0x4000>;
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||||||
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interrupts = <45>;
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||||||
|
clocks = <&clks 10>, <&clks 30>;
|
||||||
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clock-names = "ipg", "per";
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||||||
|
status = "disabled";
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||||||
|
};
|
||||||
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|
@ -0,0 +1,205 @@
|
||||||
|
NVIDIA Tegra20 Clock And Reset Controller
|
||||||
|
|
||||||
|
This binding uses the common clock binding:
|
||||||
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
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|
||||||
|
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||||
|
for muxing and gating Tegra's clocks, and setting their rates.
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible : Should be "nvidia,tegra20-car"
|
||||||
|
- reg : Should contain CAR registers location and length
|
||||||
|
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||||
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||||
|
- #clock-cells : Should be 1.
|
||||||
|
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||||
|
|
||||||
|
The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||||
|
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||||
|
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||||
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this case, those clocks are assigned IDs above 95 in order to highlight
|
||||||
|
this issue. Implementations that interpret these clock IDs as bit values
|
||||||
|
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||||
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explicitly handle these special cases.
|
||||||
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|
||||||
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The balance of the clocks controlled by the CAR are assigned IDs of 96 and
|
||||||
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above.
|
||||||
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||||||
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0 cpu
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||||||
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1 unassigned
|
||||||
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2 unassigned
|
||||||
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3 ac97
|
||||||
|
4 rtc
|
||||||
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5 tmr
|
||||||
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6 uart1
|
||||||
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7 unassigned (register bit affects uart2 and vfir)
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||||||
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8 gpio
|
||||||
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9 sdmmc2
|
||||||
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10 unassigned (register bit affects spdif_in and spdif_out)
|
||||||
|
11 i2s1
|
||||||
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12 i2c1
|
||||||
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13 ndflash
|
||||||
|
14 sdmmc1
|
||||||
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15 sdmmc4
|
||||||
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16 twc
|
||||||
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17 pwm
|
||||||
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18 i2s2
|
||||||
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19 epp
|
||||||
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20 unassigned (register bit affects vi and vi_sensor)
|
||||||
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21 2d
|
||||||
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22 usbd
|
||||||
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23 isp
|
||||||
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24 3d
|
||||||
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25 ide
|
||||||
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26 disp2
|
||||||
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27 disp1
|
||||||
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28 host1x
|
||||||
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29 vcp
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||||||
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30 unassigned
|
||||||
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31 cache2
|
||||||
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|
||||||
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32 mem
|
||||||
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33 ahbdma
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||||||
|
34 apbdma
|
||||||
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35 unassigned
|
||||||
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36 kbc
|
||||||
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37 stat_mon
|
||||||
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38 pmc
|
||||||
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39 fuse
|
||||||
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40 kfuse
|
||||||
|
41 sbc1
|
||||||
|
42 snor
|
||||||
|
43 spi1
|
||||||
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44 sbc2
|
||||||
|
45 xio
|
||||||
|
46 sbc3
|
||||||
|
47 dvc
|
||||||
|
48 dsi
|
||||||
|
49 unassigned (register bit affects tvo and cve)
|
||||||
|
50 mipi
|
||||||
|
51 hdmi
|
||||||
|
52 csi
|
||||||
|
53 tvdac
|
||||||
|
54 i2c2
|
||||||
|
55 uart3
|
||||||
|
56 unassigned
|
||||||
|
57 emc
|
||||||
|
58 usb2
|
||||||
|
59 usb3
|
||||||
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60 mpe
|
||||||
|
61 vde
|
||||||
|
62 bsea
|
||||||
|
63 bsev
|
||||||
|
|
||||||
|
64 speedo
|
||||||
|
65 uart4
|
||||||
|
66 uart5
|
||||||
|
67 i2c3
|
||||||
|
68 sbc4
|
||||||
|
69 sdmmc3
|
||||||
|
70 pcie
|
||||||
|
71 owr
|
||||||
|
72 afi
|
||||||
|
73 csite
|
||||||
|
74 unassigned
|
||||||
|
75 avpucq
|
||||||
|
76 la
|
||||||
|
77 unassigned
|
||||||
|
78 unassigned
|
||||||
|
79 unassigned
|
||||||
|
80 unassigned
|
||||||
|
81 unassigned
|
||||||
|
82 unassigned
|
||||||
|
83 unassigned
|
||||||
|
84 irama
|
||||||
|
85 iramb
|
||||||
|
86 iramc
|
||||||
|
87 iramd
|
||||||
|
88 cram2
|
||||||
|
89 audio_2x a/k/a audio_2x_sync_clk
|
||||||
|
90 clk_d
|
||||||
|
91 unassigned
|
||||||
|
92 sus
|
||||||
|
93 cdev1
|
||||||
|
94 cdev2
|
||||||
|
95 unassigned
|
||||||
|
|
||||||
|
96 uart2
|
||||||
|
97 vfir
|
||||||
|
98 spdif_in
|
||||||
|
99 spdif_out
|
||||||
|
100 vi
|
||||||
|
101 vi_sensor
|
||||||
|
102 tvo
|
||||||
|
103 cve
|
||||||
|
104 osc
|
||||||
|
105 clk_32k a/k/a clk_s
|
||||||
|
106 clk_m
|
||||||
|
107 sclk
|
||||||
|
108 cclk
|
||||||
|
109 hclk
|
||||||
|
110 pclk
|
||||||
|
111 blink
|
||||||
|
112 pll_a
|
||||||
|
113 pll_a_out0
|
||||||
|
114 pll_c
|
||||||
|
115 pll_c_out1
|
||||||
|
116 pll_d
|
||||||
|
117 pll_d_out0
|
||||||
|
118 pll_e
|
||||||
|
119 pll_m
|
||||||
|
120 pll_m_out1
|
||||||
|
121 pll_p
|
||||||
|
122 pll_p_out1
|
||||||
|
123 pll_p_out2
|
||||||
|
124 pll_p_out3
|
||||||
|
125 pll_p_out4
|
||||||
|
126 pll_s
|
||||||
|
127 pll_u
|
||||||
|
128 pll_x
|
||||||
|
129 cop a/k/a avp
|
||||||
|
130 audio a/k/a audio_sync_clk
|
||||||
|
131 pll_ref
|
||||||
|
132 twd
|
||||||
|
|
||||||
|
Example SoC include file:
|
||||||
|
|
||||||
|
/ {
|
||||||
|
tegra_car: clock {
|
||||||
|
compatible = "nvidia,tegra20-car";
|
||||||
|
reg = <0x60006000 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@c5004000 {
|
||||||
|
clocks = <&tegra_car 58>; /* usb2 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
Example board file:
|
||||||
|
|
||||||
|
/ {
|
||||||
|
clocks {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
osc: clock@0 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
reg = <0>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <12000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_32k: clock@1 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
reg = <1>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <32768>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&tegra_car {
|
||||||
|
clocks = <&clk_32k> <&osc>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,262 @@
|
||||||
|
NVIDIA Tegra30 Clock And Reset Controller
|
||||||
|
|
||||||
|
This binding uses the common clock binding:
|
||||||
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
|
|
||||||
|
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||||
|
for muxing and gating Tegra's clocks, and setting their rates.
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible : Should be "nvidia,tegra30-car"
|
||||||
|
- reg : Should contain CAR registers location and length
|
||||||
|
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||||
|
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||||
|
- #clock-cells : Should be 1.
|
||||||
|
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||||
|
|
||||||
|
The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||||
|
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||||
|
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||||
|
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||||
|
this issue. Implementations that interpret these clock IDs as bit values
|
||||||
|
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||||
|
explicitly handle these special cases.
|
||||||
|
|
||||||
|
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||||
|
above.
|
||||||
|
|
||||||
|
0 cpu
|
||||||
|
1 unassigned
|
||||||
|
2 unassigned
|
||||||
|
3 unassigned
|
||||||
|
4 rtc
|
||||||
|
5 timer
|
||||||
|
6 uarta
|
||||||
|
7 unassigned (register bit affects uartb and vfir)
|
||||||
|
8 gpio
|
||||||
|
9 sdmmc2
|
||||||
|
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||||
|
11 i2s1
|
||||||
|
12 i2c1
|
||||||
|
13 ndflash
|
||||||
|
14 sdmmc1
|
||||||
|
15 sdmmc4
|
||||||
|
16 unassigned
|
||||||
|
17 pwm
|
||||||
|
18 i2s2
|
||||||
|
19 epp
|
||||||
|
20 unassigned (register bit affects vi and vi_sensor)
|
||||||
|
21 2d
|
||||||
|
22 usbd
|
||||||
|
23 isp
|
||||||
|
24 3d
|
||||||
|
25 unassigned
|
||||||
|
26 disp2
|
||||||
|
27 disp1
|
||||||
|
28 host1x
|
||||||
|
29 vcp
|
||||||
|
30 i2s0
|
||||||
|
31 cop_cache
|
||||||
|
|
||||||
|
32 mc
|
||||||
|
33 ahbdma
|
||||||
|
34 apbdma
|
||||||
|
35 unassigned
|
||||||
|
36 kbc
|
||||||
|
37 statmon
|
||||||
|
38 pmc
|
||||||
|
39 unassigned (register bit affects fuse and fuse_burn)
|
||||||
|
40 kfuse
|
||||||
|
41 sbc1
|
||||||
|
42 nor
|
||||||
|
43 unassigned
|
||||||
|
44 sbc2
|
||||||
|
45 unassigned
|
||||||
|
46 sbc3
|
||||||
|
47 i2c5
|
||||||
|
48 dsia
|
||||||
|
49 unassigned (register bit affects cve and tvo)
|
||||||
|
50 mipi
|
||||||
|
51 hdmi
|
||||||
|
52 csi
|
||||||
|
53 tvdac
|
||||||
|
54 i2c2
|
||||||
|
55 uartc
|
||||||
|
56 unassigned
|
||||||
|
57 emc
|
||||||
|
58 usb2
|
||||||
|
59 usb3
|
||||||
|
60 mpe
|
||||||
|
61 vde
|
||||||
|
62 bsea
|
||||||
|
63 bsev
|
||||||
|
|
||||||
|
64 speedo
|
||||||
|
65 uartd
|
||||||
|
66 uarte
|
||||||
|
67 i2c3
|
||||||
|
68 sbc4
|
||||||
|
69 sdmmc3
|
||||||
|
70 pcie
|
||||||
|
71 owr
|
||||||
|
72 afi
|
||||||
|
73 csite
|
||||||
|
74 pciex
|
||||||
|
75 avpucq
|
||||||
|
76 la
|
||||||
|
77 unassigned
|
||||||
|
78 unassigned
|
||||||
|
79 dtv
|
||||||
|
80 ndspeed
|
||||||
|
81 i2cslow
|
||||||
|
82 dsib
|
||||||
|
83 unassigned
|
||||||
|
84 irama
|
||||||
|
85 iramb
|
||||||
|
86 iramc
|
||||||
|
87 iramd
|
||||||
|
88 cram2
|
||||||
|
89 unassigned
|
||||||
|
90 audio_2x a/k/a audio_2x_sync_clk
|
||||||
|
91 unassigned
|
||||||
|
92 csus
|
||||||
|
93 cdev2
|
||||||
|
94 cdev1
|
||||||
|
95 unassigned
|
||||||
|
|
||||||
|
96 cpu_g
|
||||||
|
97 cpu_lp
|
||||||
|
98 3d2
|
||||||
|
99 mselect
|
||||||
|
100 tsensor
|
||||||
|
101 i2s3
|
||||||
|
102 i2s4
|
||||||
|
103 i2c4
|
||||||
|
104 sbc5
|
||||||
|
105 sbc6
|
||||||
|
106 d_audio
|
||||||
|
107 apbif
|
||||||
|
108 dam0
|
||||||
|
109 dam1
|
||||||
|
110 dam2
|
||||||
|
111 hda2codec_2x
|
||||||
|
112 atomics
|
||||||
|
113 audio0_2x
|
||||||
|
114 audio1_2x
|
||||||
|
115 audio2_2x
|
||||||
|
116 audio3_2x
|
||||||
|
117 audio4_2x
|
||||||
|
118 audio5_2x
|
||||||
|
119 actmon
|
||||||
|
120 extern1
|
||||||
|
121 extern2
|
||||||
|
122 extern3
|
||||||
|
123 sata_oob
|
||||||
|
124 sata
|
||||||
|
125 hda
|
||||||
|
127 se
|
||||||
|
128 hda2hdmi
|
||||||
|
129 sata_cold
|
||||||
|
|
||||||
|
160 uartb
|
||||||
|
161 vfir
|
||||||
|
162 spdif_in
|
||||||
|
163 spdif_out
|
||||||
|
164 vi
|
||||||
|
165 vi_sensor
|
||||||
|
166 fuse
|
||||||
|
167 fuse_burn
|
||||||
|
168 cve
|
||||||
|
169 tvo
|
||||||
|
|
||||||
|
170 clk_32k
|
||||||
|
171 clk_m
|
||||||
|
172 clk_m_div2
|
||||||
|
173 clk_m_div4
|
||||||
|
174 pll_ref
|
||||||
|
175 pll_c
|
||||||
|
176 pll_c_out1
|
||||||
|
177 pll_m
|
||||||
|
178 pll_m_out1
|
||||||
|
179 pll_p
|
||||||
|
180 pll_p_out1
|
||||||
|
181 pll_p_out2
|
||||||
|
182 pll_p_out3
|
||||||
|
183 pll_p_out4
|
||||||
|
184 pll_a
|
||||||
|
185 pll_a_out0
|
||||||
|
186 pll_d
|
||||||
|
187 pll_d_out0
|
||||||
|
188 pll_d2
|
||||||
|
189 pll_d2_out0
|
||||||
|
190 pll_u
|
||||||
|
191 pll_x
|
||||||
|
192 pll_x_out0
|
||||||
|
193 pll_e
|
||||||
|
194 spdif_in_sync
|
||||||
|
195 i2s0_sync
|
||||||
|
196 i2s1_sync
|
||||||
|
197 i2s2_sync
|
||||||
|
198 i2s3_sync
|
||||||
|
199 i2s4_sync
|
||||||
|
200 vimclk
|
||||||
|
201 audio0
|
||||||
|
202 audio1
|
||||||
|
203 audio2
|
||||||
|
204 audio3
|
||||||
|
205 audio4
|
||||||
|
206 audio5
|
||||||
|
207 clk_out_1 (extern1)
|
||||||
|
208 clk_out_2 (extern2)
|
||||||
|
209 clk_out_3 (extern3)
|
||||||
|
210 sclk
|
||||||
|
211 blink
|
||||||
|
212 cclk_g
|
||||||
|
213 cclk_lp
|
||||||
|
214 twd
|
||||||
|
215 cml0
|
||||||
|
216 cml1
|
||||||
|
217 hclk
|
||||||
|
218 pclk
|
||||||
|
|
||||||
|
Example SoC include file:
|
||||||
|
|
||||||
|
/ {
|
||||||
|
tegra_car: clock {
|
||||||
|
compatible = "nvidia,tegra30-car";
|
||||||
|
reg = <0x60006000 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb@c5004000 {
|
||||||
|
clocks = <&tegra_car 58>; /* usb2 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
Example board file:
|
||||||
|
|
||||||
|
/ {
|
||||||
|
clocks {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
osc: clock@0 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
reg = <0>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <12000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_32k: clock@1 {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
reg = <1>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <32768>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&tegra_car {
|
||||||
|
clocks = <&clk_32k> <&osc>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -11,6 +11,7 @@ Required properties :
|
||||||
- phy_type : Should be one of "ulpi" or "utmi".
|
- phy_type : Should be one of "ulpi" or "utmi".
|
||||||
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
|
- nvidia,vbus-gpio : If present, specifies a gpio that needs to be
|
||||||
activated for the bus to be powered.
|
activated for the bus to be powered.
|
||||||
|
- nvidia,phy : phandle of the PHY instance, the controller is connected to.
|
||||||
|
|
||||||
Required properties for phy_type == ulpi:
|
Required properties for phy_type == ulpi:
|
||||||
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
|
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
|
||||||
|
|
@ -27,3 +28,5 @@ Optional properties:
|
||||||
registers are accessed through the APB_MISC base address instead of
|
registers are accessed through the APB_MISC base address instead of
|
||||||
the USB controller. Since this is a legacy issue it probably does not
|
the USB controller. Since this is a legacy issue it probably does not
|
||||||
warrant a compatible string of its own.
|
warrant a compatible string of its own.
|
||||||
|
- nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
|
||||||
|
USB ports, which need reset twice due to hardware issues.
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
Tegra SOC USB PHY
|
||||||
|
|
||||||
|
The device node for Tegra SOC USB PHY:
|
||||||
|
|
||||||
|
Required properties :
|
||||||
|
- compatible : Should be "nvidia,tegra20-usb-phy".
|
||||||
|
- reg : Address and length of the register set for the USB PHY interface.
|
||||||
|
- phy_type : Should be one of "ulpi" or "utmi".
|
||||||
|
|
||||||
|
Required properties for phy_type == ulpi:
|
||||||
|
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- nvidia,has-legacy-mode : boolean indicates whether this controller can
|
||||||
|
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
|
||||||
|
registers are accessed through the APB_MISC base address instead of
|
||||||
|
the USB controller.
|
||||||
|
|
@ -393,6 +393,7 @@ config ARCH_GEMINI
|
||||||
config ARCH_SIRF
|
config ARCH_SIRF
|
||||||
bool "CSR SiRF"
|
bool "CSR SiRF"
|
||||||
select ARCH_REQUIRE_GPIOLIB
|
select ARCH_REQUIRE_GPIOLIB
|
||||||
|
select AUTO_ZRELADDR
|
||||||
select COMMON_CLK
|
select COMMON_CLK
|
||||||
select GENERIC_CLOCKEVENTS
|
select GENERIC_CLOCKEVENTS
|
||||||
select GENERIC_IRQ_CHIP
|
select GENERIC_IRQ_CHIP
|
||||||
|
|
@ -640,6 +641,7 @@ config ARCH_LPC32XX
|
||||||
config ARCH_TEGRA
|
config ARCH_TEGRA
|
||||||
bool "NVIDIA Tegra"
|
bool "NVIDIA Tegra"
|
||||||
select ARCH_HAS_CPUFREQ
|
select ARCH_HAS_CPUFREQ
|
||||||
|
select ARCH_REQUIRE_GPIOLIB
|
||||||
select CLKDEV_LOOKUP
|
select CLKDEV_LOOKUP
|
||||||
select CLKSRC_MMIO
|
select CLKSRC_MMIO
|
||||||
select CLKSRC_OF
|
select CLKSRC_OF
|
||||||
|
|
|
||||||
|
|
@ -205,12 +205,19 @@ choice
|
||||||
Say Y here if you want kernel low-level debugging support
|
Say Y here if you want kernel low-level debugging support
|
||||||
on i.MX28.
|
on i.MX28.
|
||||||
|
|
||||||
config DEBUG_IMX31_IMX35_UART
|
config DEBUG_IMX31_UART
|
||||||
bool "i.MX31 and i.MX35 Debug UART"
|
bool "i.MX31 Debug UART"
|
||||||
depends on SOC_IMX31 || SOC_IMX35
|
depends on SOC_IMX31
|
||||||
help
|
help
|
||||||
Say Y here if you want kernel low-level debugging support
|
Say Y here if you want kernel low-level debugging support
|
||||||
on i.MX31 or i.MX35.
|
on i.MX31.
|
||||||
|
|
||||||
|
config DEBUG_IMX35_UART
|
||||||
|
bool "i.MX35 Debug UART"
|
||||||
|
depends on SOC_IMX35
|
||||||
|
help
|
||||||
|
Say Y here if you want kernel low-level debugging support
|
||||||
|
on i.MX35.
|
||||||
|
|
||||||
config DEBUG_IMX51_UART
|
config DEBUG_IMX51_UART
|
||||||
bool "i.MX51 Debug UART"
|
bool "i.MX51 Debug UART"
|
||||||
|
|
@ -393,6 +400,20 @@ choice
|
||||||
Say Y here if you want kernel low-level debugging support
|
Say Y here if you want kernel low-level debugging support
|
||||||
on Tegra based platforms.
|
on Tegra based platforms.
|
||||||
|
|
||||||
|
config DEBUG_SIRFPRIMA2_UART1
|
||||||
|
bool "Kernel low-level debugging messages via SiRFprimaII UART1"
|
||||||
|
depends on ARCH_PRIMA2
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the uart1 port on SiRFprimaII devices.
|
||||||
|
|
||||||
|
config DEBUG_SIRFMARCO_UART1
|
||||||
|
bool "Kernel low-level debugging messages via SiRFmarco UART1"
|
||||||
|
depends on ARCH_MARCO
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the uart1 port on SiRFmarco devices.
|
||||||
|
|
||||||
config DEBUG_VEXPRESS_UART0_DETECT
|
config DEBUG_VEXPRESS_UART0_DETECT
|
||||||
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
|
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
|
||||||
depends on ARCH_VEXPRESS && CPU_CP15_MMU
|
depends on ARCH_VEXPRESS && CPU_CP15_MMU
|
||||||
|
|
@ -464,11 +485,16 @@ choice
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config DEBUG_IMX6Q_UART_PORT
|
config DEBUG_IMX_UART_PORT
|
||||||
int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART
|
int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
|
||||||
range 1 5
|
DEBUG_IMX25_UART || \
|
||||||
|
DEBUG_IMX21_IMX27_UART || \
|
||||||
|
DEBUG_IMX31_UART || \
|
||||||
|
DEBUG_IMX35_UART || \
|
||||||
|
DEBUG_IMX51_UART || \
|
||||||
|
DEBUG_IMX50_IMX53_UART || \
|
||||||
|
DEBUG_IMX6Q_UART
|
||||||
default 1
|
default 1
|
||||||
depends on SOC_IMX6Q
|
|
||||||
help
|
help
|
||||||
Choose UART port on which kernel low-level debug messages
|
Choose UART port on which kernel low-level debug messages
|
||||||
should be output.
|
should be output.
|
||||||
|
|
@ -557,7 +583,8 @@ config DEBUG_LL_INCLUDE
|
||||||
default "debug/imx.S" if DEBUG_IMX1_UART || \
|
default "debug/imx.S" if DEBUG_IMX1_UART || \
|
||||||
DEBUG_IMX25_UART || \
|
DEBUG_IMX25_UART || \
|
||||||
DEBUG_IMX21_IMX27_UART || \
|
DEBUG_IMX21_IMX27_UART || \
|
||||||
DEBUG_IMX31_IMX35_UART || \
|
DEBUG_IMX31_UART || \
|
||||||
|
DEBUG_IMX35_UART || \
|
||||||
DEBUG_IMX51_UART || \
|
DEBUG_IMX51_UART || \
|
||||||
DEBUG_IMX53_UART ||\
|
DEBUG_IMX53_UART ||\
|
||||||
DEBUG_IMX6Q_UART
|
DEBUG_IMX6Q_UART
|
||||||
|
|
|
||||||
|
|
@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
|
||||||
kirkwood-ts219-6281.dtb \
|
kirkwood-ts219-6281.dtb \
|
||||||
kirkwood-ts219-6282.dtb \
|
kirkwood-ts219-6282.dtb \
|
||||||
kirkwood-openblocks_a6.dtb
|
kirkwood-openblocks_a6.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
|
||||||
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
|
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
|
||||||
msm8960-cdp.dtb
|
msm8960-cdp.dtb
|
||||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
|
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
|
||||||
|
|
@ -124,6 +125,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
|
||||||
r8a7740-armadillo800eva.dtb \
|
r8a7740-armadillo800eva.dtb \
|
||||||
sh73a0-kzm9g.dtb \
|
sh73a0-kzm9g.dtb \
|
||||||
sh7372-mackerel.dtb
|
sh7372-mackerel.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
|
||||||
|
socfpga_vt.dtb
|
||||||
dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
|
dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
|
||||||
spear1340-evb.dtb
|
spear1340-evb.dtb
|
||||||
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
|
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
|
||||||
|
|
@ -143,7 +146,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
||||||
tegra20-ventana.dtb \
|
tegra20-ventana.dtb \
|
||||||
tegra20-whistler.dtb \
|
tegra20-whistler.dtb \
|
||||||
tegra30-cardhu-a02.dtb \
|
tegra30-cardhu-a02.dtb \
|
||||||
tegra30-cardhu-a04.dtb
|
tegra30-cardhu-a04.dtb \
|
||||||
|
tegra114-dalmore.dtb \
|
||||||
|
tegra114-pluto.dtb
|
||||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
||||||
vexpress-v2p-ca9.dtb \
|
vexpress-v2p-ca9.dtb \
|
||||||
vexpress-v2p-ca15-tc1.dtb \
|
vexpress-v2p-ca15-tc1.dtb \
|
||||||
|
|
@ -151,7 +156,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
||||||
xenvm-4.2.dtb
|
xenvm-4.2.dtb
|
||||||
dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
|
dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
|
||||||
wm8505-ref.dtb \
|
wm8505-ref.dtb \
|
||||||
wm8650-mid.dtb
|
wm8650-mid.dtb \
|
||||||
|
wm8850-w70v2.dtb
|
||||||
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
|
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
|
||||||
|
|
||||||
targets += dtbs
|
targets += dtbs
|
||||||
|
|
|
||||||
|
|
@ -15,11 +15,18 @@
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
cpu@0 {
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a9";
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
};
|
};
|
||||||
cpu@1 {
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
compatible = "arm,cortex-a9";
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -45,6 +45,8 @@
|
||||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
reg = <0x43f90000 0x4000>;
|
reg = <0x43f90000 0x4000>;
|
||||||
interrupts = <45>;
|
interrupts = <45>;
|
||||||
|
clocks = <&clks 10>, <&clks 30>;
|
||||||
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -52,12 +54,16 @@
|
||||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
reg = <0x43f94000 0x4000>;
|
reg = <0x43f94000 0x4000>;
|
||||||
interrupts = <32>;
|
interrupts = <32>;
|
||||||
|
clocks = <&clks 10>, <&clks 31>;
|
||||||
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
uart4: serial@43fb0000 {
|
uart4: serial@43fb0000 {
|
||||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
reg = <0x43fb0000 0x4000>;
|
reg = <0x43fb0000 0x4000>;
|
||||||
|
clocks = <&clks 10>, <&clks 49>;
|
||||||
|
clock-names = "ipg", "per";
|
||||||
interrupts = <46>;
|
interrupts = <46>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
@ -66,6 +72,8 @@
|
||||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
reg = <0x43fb4000 0x4000>;
|
reg = <0x43fb4000 0x4000>;
|
||||||
interrupts = <47>;
|
interrupts = <47>;
|
||||||
|
clocks = <&clks 10>, <&clks 50>;
|
||||||
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -81,8 +89,17 @@
|
||||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||||
reg = <0x5000c000 0x4000>;
|
reg = <0x5000c000 0x4000>;
|
||||||
interrupts = <18>;
|
interrupts = <18>;
|
||||||
|
clocks = <&clks 10>, <&clks 48>;
|
||||||
|
clock-names = "ipg", "per";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
clks: ccm@53f80000{
|
||||||
|
compatible = "fsl,imx31-ccm";
|
||||||
|
reg = <0x53f80000 0x4000>;
|
||||||
|
interrupts = <0 31 0x04 0 53 0x04>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,54 @@
|
||||||
|
/*
|
||||||
|
* DTS file for CSR SiRFmarco Evaluation Board
|
||||||
|
*
|
||||||
|
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "marco.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "CSR SiRFmarco Evaluation Board";
|
||||||
|
compatible = "sirf,marco-cb", "sirf,marco";
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x40000000 0x60000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
axi {
|
||||||
|
peri-iobg {
|
||||||
|
uart1: uart@cc060000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
uart2: uart@cc070000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
i2c0: i2c@cc0e0000 {
|
||||||
|
status = "okay";
|
||||||
|
fpga-cpld@4d {
|
||||||
|
compatible = "sirf,fpga-cpld";
|
||||||
|
reg = <0x4d>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
spi1: spi@cc170000 {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi1_pins_a>;
|
||||||
|
spi@0 {
|
||||||
|
compatible = "spidev";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <1000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pci-iobg {
|
||||||
|
sd0: sdhci@cd000000 {
|
||||||
|
bus-width = <8>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,756 @@
|
||||||
|
/*
|
||||||
|
* DTS file for CSR SiRFmarco SoC
|
||||||
|
*
|
||||||
|
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
/ {
|
||||||
|
compatible = "sirf,marco";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
axi {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x40000000 0x40000000 0xa0000000>;
|
||||||
|
|
||||||
|
l2-cache-controller@c0030000 {
|
||||||
|
compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
|
||||||
|
reg = <0xc0030000 0x1000>;
|
||||||
|
interrupts = <0 59 0>;
|
||||||
|
arm,tag-latency = <1 1 1>;
|
||||||
|
arm,data-latency = <1 1 1>;
|
||||||
|
arm,filter-ranges = <0x40000000 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@c0011000 {
|
||||||
|
compatible = "arm,cortex-a9-gic";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
reg = <0xc0011000 0x1000>,
|
||||||
|
<0xc0010100 0x0100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rstc-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc2000000 0xc2000000 0x1000000>;
|
||||||
|
|
||||||
|
reset-controller@c2000000 {
|
||||||
|
compatible = "sirf,marco-rstc";
|
||||||
|
reg = <0xc2000000 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sys-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc3000000 0xc3000000 0x1000000>;
|
||||||
|
|
||||||
|
clock-controller@c3000000 {
|
||||||
|
compatible = "sirf,marco-clkc";
|
||||||
|
reg = <0xc3000000 0x1000>;
|
||||||
|
interrupts = <0 3 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rsc-controller@c3010000 {
|
||||||
|
compatible = "sirf,marco-rsc";
|
||||||
|
reg = <0xc3010000 0x1000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mem-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc4000000 0xc4000000 0x1000000>;
|
||||||
|
|
||||||
|
memory-controller@c4000000 {
|
||||||
|
compatible = "sirf,marco-memc";
|
||||||
|
reg = <0xc4000000 0x10000>;
|
||||||
|
interrupts = <0 27 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
disp-iobg0 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc5000000 0xc5000000 0x1000000>;
|
||||||
|
|
||||||
|
display0@c5000000 {
|
||||||
|
compatible = "sirf,marco-lcd";
|
||||||
|
reg = <0xc5000000 0x10000>;
|
||||||
|
interrupts = <0 30 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vpp0@c5010000 {
|
||||||
|
compatible = "sirf,marco-vpp";
|
||||||
|
reg = <0xc5010000 0x10000>;
|
||||||
|
interrupts = <0 31 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
disp-iobg1 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc6000000 0xc6000000 0x1000000>;
|
||||||
|
|
||||||
|
display1@c6000000 {
|
||||||
|
compatible = "sirf,marco-lcd";
|
||||||
|
reg = <0xc6000000 0x10000>;
|
||||||
|
interrupts = <0 62 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vpp1@c6010000 {
|
||||||
|
compatible = "sirf,marco-vpp";
|
||||||
|
reg = <0xc6010000 0x10000>;
|
||||||
|
interrupts = <0 63 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
graphics-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc8000000 0xc8000000 0x1000000>;
|
||||||
|
|
||||||
|
graphics@c8000000 {
|
||||||
|
compatible = "powervr,sgx540";
|
||||||
|
reg = <0xc8000000 0x1000000>;
|
||||||
|
interrupts = <0 6 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
multimedia-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xc9000000 0xc9000000 0x1000000>;
|
||||||
|
|
||||||
|
multimedia@a0000000 {
|
||||||
|
compatible = "sirf,marco-video-codec";
|
||||||
|
reg = <0xc9000000 0x1000000>;
|
||||||
|
interrupts = <0 5 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
dsp-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xca000000 0xca000000 0x2000000>;
|
||||||
|
|
||||||
|
dspif@ca000000 {
|
||||||
|
compatible = "sirf,marco-dspif";
|
||||||
|
reg = <0xca000000 0x10000>;
|
||||||
|
interrupts = <0 9 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gps@ca010000 {
|
||||||
|
compatible = "sirf,marco-gps";
|
||||||
|
reg = <0xca010000 0x10000>;
|
||||||
|
interrupts = <0 7 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dsp@cb000000 {
|
||||||
|
compatible = "sirf,marco-dsp";
|
||||||
|
reg = <0xcb000000 0x1000000>;
|
||||||
|
interrupts = <0 8 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
peri-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xcc000000 0xcc000000 0x2000000>;
|
||||||
|
|
||||||
|
timer@cc020000 {
|
||||||
|
compatible = "sirf,marco-tick";
|
||||||
|
reg = <0xcc020000 0x1000>;
|
||||||
|
interrupts = <0 0 0>,
|
||||||
|
<0 1 0>,
|
||||||
|
<0 2 0>,
|
||||||
|
<0 49 0>,
|
||||||
|
<0 50 0>,
|
||||||
|
<0 51 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
nand@cc030000 {
|
||||||
|
compatible = "sirf,marco-nand";
|
||||||
|
reg = <0xcc030000 0x10000>;
|
||||||
|
interrupts = <0 41 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
audio@cc040000 {
|
||||||
|
compatible = "sirf,marco-audio";
|
||||||
|
reg = <0xcc040000 0x10000>;
|
||||||
|
interrupts = <0 35 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: uart@cc050000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-uart";
|
||||||
|
reg = <0xcc050000 0x1000>;
|
||||||
|
interrupts = <0 17 0>;
|
||||||
|
fifosize = <128>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: uart@cc060000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-uart";
|
||||||
|
reg = <0xcc060000 0x1000>;
|
||||||
|
interrupts = <0 18 0>;
|
||||||
|
fifosize = <32>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart2: uart@cc070000 {
|
||||||
|
cell-index = <2>;
|
||||||
|
compatible = "sirf,marco-uart";
|
||||||
|
reg = <0xcc070000 0x1000>;
|
||||||
|
interrupts = <0 19 0>;
|
||||||
|
fifosize = <128>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart3: uart@cc190000 {
|
||||||
|
cell-index = <3>;
|
||||||
|
compatible = "sirf,marco-uart";
|
||||||
|
reg = <0xcc190000 0x1000>;
|
||||||
|
interrupts = <0 66 0>;
|
||||||
|
fifosize = <128>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart4: uart@cc1a0000 {
|
||||||
|
cell-index = <4>;
|
||||||
|
compatible = "sirf,marco-uart";
|
||||||
|
reg = <0xcc1a0000 0x1000>;
|
||||||
|
interrupts = <0 69 0>;
|
||||||
|
fifosize = <128>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usp0: usp@cc080000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-usp";
|
||||||
|
reg = <0xcc080000 0x10000>;
|
||||||
|
interrupts = <0 20 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usp1: usp@cc090000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-usp";
|
||||||
|
reg = <0xcc090000 0x10000>;
|
||||||
|
interrupts = <0 21 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usp2: usp@cc0a0000 {
|
||||||
|
cell-index = <2>;
|
||||||
|
compatible = "sirf,marco-usp";
|
||||||
|
reg = <0xcc0a0000 0x10000>;
|
||||||
|
interrupts = <0 22 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
dmac0: dma-controller@cc0b0000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-dmac";
|
||||||
|
reg = <0xcc0b0000 0x10000>;
|
||||||
|
interrupts = <0 12 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dmac1: dma-controller@cc160000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-dmac";
|
||||||
|
reg = <0xcc160000 0x10000>;
|
||||||
|
interrupts = <0 13 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vip@cc0c0000 {
|
||||||
|
compatible = "sirf,marco-vip";
|
||||||
|
reg = <0xcc0c0000 0x10000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi0: spi@cc0d0000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-spi";
|
||||||
|
reg = <0xcc0d0000 0x10000>;
|
||||||
|
interrupts = <0 15 0>;
|
||||||
|
sirf,spi-num-chipselects = <1>;
|
||||||
|
cs-gpios = <&gpio 0 0>;
|
||||||
|
sirf,spi-dma-rx-channel = <25>;
|
||||||
|
sirf,spi-dma-tx-channel = <20>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi1: spi@cc170000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-spi";
|
||||||
|
reg = <0xcc170000 0x10000>;
|
||||||
|
interrupts = <0 16 0>;
|
||||||
|
sirf,spi-num-chipselects = <1>;
|
||||||
|
cs-gpios = <&gpio 0 0>;
|
||||||
|
sirf,spi-dma-rx-channel = <12>;
|
||||||
|
sirf,spi-dma-tx-channel = <13>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c0: i2c@cc0e0000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-i2c";
|
||||||
|
reg = <0xcc0e0000 0x10000>;
|
||||||
|
interrupts = <0 24 0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: i2c@cc0f0000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-i2c";
|
||||||
|
reg = <0xcc0f0000 0x10000>;
|
||||||
|
interrupts = <0 25 0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tsc@cc110000 {
|
||||||
|
compatible = "sirf,marco-tsc";
|
||||||
|
reg = <0xcc110000 0x10000>;
|
||||||
|
interrupts = <0 33 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio: pinctrl@cc120000 {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
compatible = "sirf,marco-pinctrl";
|
||||||
|
reg = <0xcc120000 0x10000>;
|
||||||
|
interrupts = <0 43 0>,
|
||||||
|
<0 44 0>,
|
||||||
|
<0 45 0>,
|
||||||
|
<0 46 0>,
|
||||||
|
<0 47 0>;
|
||||||
|
gpio-controller;
|
||||||
|
interrupt-controller;
|
||||||
|
|
||||||
|
lcd_16pins_a: lcd0_0 {
|
||||||
|
lcd {
|
||||||
|
sirf,pins = "lcd_16bitsgrp";
|
||||||
|
sirf,function = "lcd_16bits";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
lcd_18pins_a: lcd0_1 {
|
||||||
|
lcd {
|
||||||
|
sirf,pins = "lcd_18bitsgrp";
|
||||||
|
sirf,function = "lcd_18bits";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
lcd_24pins_a: lcd0_2 {
|
||||||
|
lcd {
|
||||||
|
sirf,pins = "lcd_24bitsgrp";
|
||||||
|
sirf,function = "lcd_24bits";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
lcdrom_pins_a: lcdrom0_0 {
|
||||||
|
lcd {
|
||||||
|
sirf,pins = "lcdromgrp";
|
||||||
|
sirf,function = "lcdrom";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uart0_pins_a: uart0_0 {
|
||||||
|
uart {
|
||||||
|
sirf,pins = "uart0grp";
|
||||||
|
sirf,function = "uart0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uart1_pins_a: uart1_0 {
|
||||||
|
uart {
|
||||||
|
sirf,pins = "uart1grp";
|
||||||
|
sirf,function = "uart1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uart2_pins_a: uart2_0 {
|
||||||
|
uart {
|
||||||
|
sirf,pins = "uart2grp";
|
||||||
|
sirf,function = "uart2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
uart2_noflow_pins_a: uart2_1 {
|
||||||
|
uart {
|
||||||
|
sirf,pins = "uart2_nostreamctrlgrp";
|
||||||
|
sirf,function = "uart2_nostreamctrl";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
spi0_pins_a: spi0_0 {
|
||||||
|
spi {
|
||||||
|
sirf,pins = "spi0grp";
|
||||||
|
sirf,function = "spi0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
spi1_pins_a: spi1_0 {
|
||||||
|
spi {
|
||||||
|
sirf,pins = "spi1grp";
|
||||||
|
sirf,function = "spi1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
i2c0_pins_a: i2c0_0 {
|
||||||
|
i2c {
|
||||||
|
sirf,pins = "i2c0grp";
|
||||||
|
sirf,function = "i2c0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
i2c1_pins_a: i2c1_0 {
|
||||||
|
i2c {
|
||||||
|
sirf,pins = "i2c1grp";
|
||||||
|
sirf,function = "i2c1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pwm0_pins_a: pwm0_0 {
|
||||||
|
pwm {
|
||||||
|
sirf,pins = "pwm0grp";
|
||||||
|
sirf,function = "pwm0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pwm1_pins_a: pwm1_0 {
|
||||||
|
pwm {
|
||||||
|
sirf,pins = "pwm1grp";
|
||||||
|
sirf,function = "pwm1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pwm2_pins_a: pwm2_0 {
|
||||||
|
pwm {
|
||||||
|
sirf,pins = "pwm2grp";
|
||||||
|
sirf,function = "pwm2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pwm3_pins_a: pwm3_0 {
|
||||||
|
pwm {
|
||||||
|
sirf,pins = "pwm3grp";
|
||||||
|
sirf,function = "pwm3";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
gps_pins_a: gps_0 {
|
||||||
|
gps {
|
||||||
|
sirf,pins = "gpsgrp";
|
||||||
|
sirf,function = "gps";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
vip_pins_a: vip_0 {
|
||||||
|
vip {
|
||||||
|
sirf,pins = "vipgrp";
|
||||||
|
sirf,function = "vip";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc0_pins_a: sdmmc0_0 {
|
||||||
|
sdmmc0 {
|
||||||
|
sirf,pins = "sdmmc0grp";
|
||||||
|
sirf,function = "sdmmc0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc1_pins_a: sdmmc1_0 {
|
||||||
|
sdmmc1 {
|
||||||
|
sirf,pins = "sdmmc1grp";
|
||||||
|
sirf,function = "sdmmc1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc2_pins_a: sdmmc2_0 {
|
||||||
|
sdmmc2 {
|
||||||
|
sirf,pins = "sdmmc2grp";
|
||||||
|
sirf,function = "sdmmc2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc3_pins_a: sdmmc3_0 {
|
||||||
|
sdmmc3 {
|
||||||
|
sirf,pins = "sdmmc3grp";
|
||||||
|
sirf,function = "sdmmc3";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc4_pins_a: sdmmc4_0 {
|
||||||
|
sdmmc4 {
|
||||||
|
sirf,pins = "sdmmc4grp";
|
||||||
|
sirf,function = "sdmmc4";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sdmmc5_pins_a: sdmmc5_0 {
|
||||||
|
sdmmc5 {
|
||||||
|
sirf,pins = "sdmmc5grp";
|
||||||
|
sirf,function = "sdmmc5";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
i2s_pins_a: i2s_0 {
|
||||||
|
i2s {
|
||||||
|
sirf,pins = "i2sgrp";
|
||||||
|
sirf,function = "i2s";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
ac97_pins_a: ac97_0 {
|
||||||
|
ac97 {
|
||||||
|
sirf,pins = "ac97grp";
|
||||||
|
sirf,function = "ac97";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
nand_pins_a: nand_0 {
|
||||||
|
nand {
|
||||||
|
sirf,pins = "nandgrp";
|
||||||
|
sirf,function = "nand";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
usp0_pins_a: usp0_0 {
|
||||||
|
usp0 {
|
||||||
|
sirf,pins = "usp0grp";
|
||||||
|
sirf,function = "usp0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
usp1_pins_a: usp1_0 {
|
||||||
|
usp1 {
|
||||||
|
sirf,pins = "usp1grp";
|
||||||
|
sirf,function = "usp1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
usp2_pins_a: usp2_0 {
|
||||||
|
usp2 {
|
||||||
|
sirf,pins = "usp2grp";
|
||||||
|
sirf,function = "usp2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
|
||||||
|
usb0_utmi_drvbus {
|
||||||
|
sirf,pins = "usb0_utmi_drvbusgrp";
|
||||||
|
sirf,function = "usb0_utmi_drvbus";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
|
||||||
|
usb1_utmi_drvbus {
|
||||||
|
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||||
|
sirf,function = "usb1_utmi_drvbus";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
warm_rst_pins_a: warm_rst_0 {
|
||||||
|
warm_rst {
|
||||||
|
sirf,pins = "warm_rstgrp";
|
||||||
|
sirf,function = "warm_rst";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
pulse_count_pins_a: pulse_count_0 {
|
||||||
|
pulse_count {
|
||||||
|
sirf,pins = "pulse_countgrp";
|
||||||
|
sirf,function = "pulse_count";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
cko0_rst_pins_a: cko0_rst_0 {
|
||||||
|
cko0_rst {
|
||||||
|
sirf,pins = "cko0_rstgrp";
|
||||||
|
sirf,function = "cko0_rst";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
cko1_rst_pins_a: cko1_rst_0 {
|
||||||
|
cko1_rst {
|
||||||
|
sirf,pins = "cko1_rstgrp";
|
||||||
|
sirf,function = "cko1_rst";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pwm@cc130000 {
|
||||||
|
compatible = "sirf,marco-pwm";
|
||||||
|
reg = <0xcc130000 0x10000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
efusesys@cc140000 {
|
||||||
|
compatible = "sirf,marco-efuse";
|
||||||
|
reg = <0xcc140000 0x10000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pulsec@cc150000 {
|
||||||
|
compatible = "sirf,marco-pulsec";
|
||||||
|
reg = <0xcc150000 0x10000>;
|
||||||
|
interrupts = <0 48 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pci-iobg {
|
||||||
|
compatible = "sirf,marco-pciiobg", "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xcd000000 0xcd000000 0x1000000>;
|
||||||
|
|
||||||
|
sd0: sdhci@cd000000 {
|
||||||
|
cell-index = <0>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd000000 0x100000>;
|
||||||
|
interrupts = <0 38 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sd1: sdhci@cd100000 {
|
||||||
|
cell-index = <1>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd100000 0x100000>;
|
||||||
|
interrupts = <0 38 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sd2: sdhci@cd200000 {
|
||||||
|
cell-index = <2>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd200000 0x100000>;
|
||||||
|
interrupts = <0 23 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sd3: sdhci@cd300000 {
|
||||||
|
cell-index = <3>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd300000 0x100000>;
|
||||||
|
interrupts = <0 23 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sd4: sdhci@cd400000 {
|
||||||
|
cell-index = <4>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd400000 0x100000>;
|
||||||
|
interrupts = <0 39 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
sd5: sdhci@cd500000 {
|
||||||
|
cell-index = <5>;
|
||||||
|
compatible = "sirf,marco-sdhc";
|
||||||
|
reg = <0xcd500000 0x100000>;
|
||||||
|
interrupts = <0 39 0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pci-copy@cd900000 {
|
||||||
|
compatible = "sirf,marco-pcicp";
|
||||||
|
reg = <0xcd900000 0x100000>;
|
||||||
|
interrupts = <0 40 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rom-interface@cda00000 {
|
||||||
|
compatible = "sirf,marco-romif";
|
||||||
|
reg = <0xcda00000 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc-iobg {
|
||||||
|
compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
reg = <0xc1000000 0x10000>;
|
||||||
|
|
||||||
|
gpsrtc@1000 {
|
||||||
|
compatible = "sirf,marco-gpsrtc";
|
||||||
|
reg = <0x1000 0x1000>;
|
||||||
|
interrupts = <0 55 0>,
|
||||||
|
<0 56 0>,
|
||||||
|
<0 57 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysrtc@2000 {
|
||||||
|
compatible = "sirf,marco-sysrtc";
|
||||||
|
reg = <0x2000 0x1000>;
|
||||||
|
interrupts = <0 52 0>,
|
||||||
|
<0 53 0>,
|
||||||
|
<0 54 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pwrc@3000 {
|
||||||
|
compatible = "sirf,marco-pwrc";
|
||||||
|
reg = <0x3000 0x1000>;
|
||||||
|
interrupts = <0 32 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uus-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xce000000 0xce000000 0x1000000>;
|
||||||
|
|
||||||
|
usb0: usb@ce000000 {
|
||||||
|
compatible = "chipidea,ci13611a-marco";
|
||||||
|
reg = <0xce000000 0x10000>;
|
||||||
|
interrupts = <0 10 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb1: usb@ce010000 {
|
||||||
|
compatible = "chipidea,ci13611a-marco";
|
||||||
|
reg = <0xce010000 0x10000>;
|
||||||
|
interrupts = <0 11 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
security@ce020000 {
|
||||||
|
compatible = "sirf,marco-security";
|
||||||
|
reg = <0xce020000 0x10000>;
|
||||||
|
interrupts = <0 42 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
can-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xd0000000 0xd0000000 0x1000000>;
|
||||||
|
|
||||||
|
can0: can@d0000000 {
|
||||||
|
compatible = "sirf,marco-can";
|
||||||
|
reg = <0xd0000000 0x10000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
can1: can@d0010000 {
|
||||||
|
compatible = "sirf,marco-can";
|
||||||
|
reg = <0xd0010000 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
lvds-iobg {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0xd1000000 0xd1000000 0x1000000>;
|
||||||
|
|
||||||
|
lvds@d1000000 {
|
||||||
|
compatible = "sirf,marco-lvds";
|
||||||
|
reg = <0xd1000000 0x10000>;
|
||||||
|
interrupts = <0 64 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for the SH73A0 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||||
|
*
|
||||||
|
* This file is licensed under the terms of the GNU General Public License
|
||||||
|
* version 2. This program is licensed "as is" without any warranty of any
|
||||||
|
* kind, whether express or implied.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "sh73a0.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "renesas,sh73a0";
|
||||||
|
|
||||||
|
mmcif: mmcif@0x10010000 {
|
||||||
|
compatible = "renesas,sh-mmcif";
|
||||||
|
reg = <0xe6bd0000 0x100>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 140 0x4
|
||||||
|
0 141 0x4>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
/*
|
||||||
|
* Device Tree Source for the SH73A0 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||||
|
*
|
||||||
|
* This file is licensed under the terms of the GNU General Public License
|
||||||
|
* version 2. This program is licensed "as is" without any warranty of any
|
||||||
|
* kind, whether express or implied.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "renesas,sh73a0";
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@f0001000 {
|
||||||
|
compatible = "arm,cortex-a9-gic";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0xf0001000 0x1000>,
|
||||||
|
<0xf0000100 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c0: i2c@0xe6820000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "renesas,rmobile-iic";
|
||||||
|
reg = <0xe6820000 0x425>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 167 0x4
|
||||||
|
0 168 0x4
|
||||||
|
0 169 0x4
|
||||||
|
0 170 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: i2c@0xe6822000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "renesas,rmobile-iic";
|
||||||
|
reg = <0xe6822000 0x425>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 51 0x4
|
||||||
|
0 52 0x4
|
||||||
|
0 53 0x4
|
||||||
|
0 54 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c2: i2c@0xe6824000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "renesas,rmobile-iic";
|
||||||
|
reg = <0xe6824000 0x425>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 171 0x4
|
||||||
|
0 172 0x4
|
||||||
|
0 173 0x4
|
||||||
|
0 174 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c3: i2c@0xe6826000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "renesas,rmobile-iic";
|
||||||
|
reg = <0xe6826000 0x425>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 183 0x4
|
||||||
|
0 184 0x4
|
||||||
|
0 185 0x4
|
||||||
|
0 186 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c4: i2c@0xe6828000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "renesas,rmobile-iic";
|
||||||
|
reg = <0xe6828000 0x425>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <0 187 0x4
|
||||||
|
0 188 0x4
|
||||||
|
0 189 0x4
|
||||||
|
0 190 0x4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -25,6 +25,10 @@
|
||||||
ethernet0 = &gmac0;
|
ethernet0 = &gmac0;
|
||||||
serial0 = &uart0;
|
serial0 = &uart0;
|
||||||
serial1 = &uart1;
|
serial1 = &uart1;
|
||||||
|
timer0 = &timer0;
|
||||||
|
timer1 = &timer1;
|
||||||
|
timer2 = &timer2;
|
||||||
|
timer3 = &timer3;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
|
|
@ -98,47 +102,41 @@
|
||||||
interrupts = <1 13 0xf04>;
|
interrupts = <1 13 0xf04>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer0: timer@ffc08000 {
|
timer0: timer0@ffc08000 {
|
||||||
compatible = "snps,dw-apb-timer-sp";
|
compatible = "snps,dw-apb-timer-sp";
|
||||||
interrupts = <0 167 4>;
|
interrupts = <0 167 4>;
|
||||||
clock-frequency = <200000000>;
|
|
||||||
reg = <0xffc08000 0x1000>;
|
reg = <0xffc08000 0x1000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer1: timer@ffc09000 {
|
timer1: timer1@ffc09000 {
|
||||||
compatible = "snps,dw-apb-timer-sp";
|
compatible = "snps,dw-apb-timer-sp";
|
||||||
interrupts = <0 168 4>;
|
interrupts = <0 168 4>;
|
||||||
clock-frequency = <200000000>;
|
|
||||||
reg = <0xffc09000 0x1000>;
|
reg = <0xffc09000 0x1000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer2: timer@ffd00000 {
|
timer2: timer2@ffd00000 {
|
||||||
compatible = "snps,dw-apb-timer-osc";
|
compatible = "snps,dw-apb-timer-osc";
|
||||||
interrupts = <0 169 4>;
|
interrupts = <0 169 4>;
|
||||||
clock-frequency = <200000000>;
|
|
||||||
reg = <0xffd00000 0x1000>;
|
reg = <0xffd00000 0x1000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
timer3: timer@ffd01000 {
|
timer3: timer3@ffd01000 {
|
||||||
compatible = "snps,dw-apb-timer-osc";
|
compatible = "snps,dw-apb-timer-osc";
|
||||||
interrupts = <0 170 4>;
|
interrupts = <0 170 4>;
|
||||||
clock-frequency = <200000000>;
|
|
||||||
reg = <0xffd01000 0x1000>;
|
reg = <0xffd01000 0x1000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart0: uart@ffc02000 {
|
uart0: serial0@ffc02000 {
|
||||||
compatible = "snps,dw-apb-uart";
|
compatible = "snps,dw-apb-uart";
|
||||||
reg = <0xffc02000 0x1000>;
|
reg = <0xffc02000 0x1000>;
|
||||||
clock-frequency = <7372800>;
|
|
||||||
interrupts = <0 162 4>;
|
interrupts = <0 162 4>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart1: uart@ffc03000 {
|
uart1: serial1@ffc03000 {
|
||||||
compatible = "snps,dw-apb-uart";
|
compatible = "snps,dw-apb-uart";
|
||||||
reg = <0xffc03000 0x1000>;
|
reg = <0xffc03000 0x1000>;
|
||||||
clock-frequency = <7372800>;
|
|
||||||
interrupts = <0 163 4>;
|
interrupts = <0 163 4>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
|
|
|
||||||
|
|
@ -20,7 +20,7 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "Altera SOCFPGA Cyclone V";
|
model = "Altera SOCFPGA Cyclone V";
|
||||||
compatible = "altr,socfpga-cyclone5";
|
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
bootargs = "console=ttyS0,57600";
|
bootargs = "console=ttyS0,57600";
|
||||||
|
|
@ -29,6 +29,36 @@
|
||||||
memory {
|
memory {
|
||||||
name = "memory";
|
name = "memory";
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x0 0x10000000>; /* 256MB */
|
reg = <0x0 0x40000000>; /* 1GB */
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
timer0@ffc08000 {
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1@ffc09000 {
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer2@ffd00000 {
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3@ffd01000 {
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0@ffc02000 {
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1@ffc03000 {
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysmgr@ffd08000 {
|
||||||
|
cpu1-start-addr = <0xffd080c4>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,64 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/include/ "socfpga.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Altera SOCFPGA VT";
|
||||||
|
compatible = "altr,socfpga-vt", "altr,socfpga";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=ttyS0,57600";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
name = "memory";
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x0 0x40000000>; /* 1 GB */
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
timer0@ffc08000 {
|
||||||
|
clock-frequency = <7000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer1@ffc09000 {
|
||||||
|
clock-frequency = <7000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer2@ffd00000 {
|
||||||
|
clock-frequency = <7000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer3@ffd01000 {
|
||||||
|
clock-frequency = <7000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial0@ffc02000 {
|
||||||
|
clock-frequency = <7372800>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial1@ffc03000 {
|
||||||
|
clock-frequency = <7372800>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysmgr@ffd08000 {
|
||||||
|
cpu1-start-addr = <0xffd08010>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tegra114.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NVIDIA Tegra114 Dalmore evaluation board";
|
||||||
|
compatible = "nvidia,dalmore", "nvidia,tegra114";
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x80000000 0x40000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006300 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <408000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc {
|
||||||
|
nvidia,invert-interrupt;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/include/ "tegra114.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NVIDIA Tegra114 Pluto evaluation board";
|
||||||
|
compatible = "nvidia,pluto", "nvidia,tegra114";
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x80000000 0x40000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006300 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <408000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc {
|
||||||
|
nvidia,invert-interrupt;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,153 @@
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "nvidia,tegra114";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
|
||||||
|
gic: interrupt-controller {
|
||||||
|
compatible = "arm,cortex-a15-gic";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x50041000 0x1000>,
|
||||||
|
<0x50042000 0x1000>,
|
||||||
|
<0x50044000 0x2000>,
|
||||||
|
<0x50046000 0x2000>;
|
||||||
|
interrupts = <1 9 0xf04>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@60005000 {
|
||||||
|
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
|
||||||
|
reg = <0x60005000 0x400>;
|
||||||
|
interrupts = <0 0 0x04
|
||||||
|
0 1 0x04
|
||||||
|
0 41 0x04
|
||||||
|
0 42 0x04
|
||||||
|
0 121 0x04
|
||||||
|
0 122 0x04>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_car: clock {
|
||||||
|
compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
|
||||||
|
reg = <0x60006000 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ahb: ahb {
|
||||||
|
compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
|
||||||
|
reg = <0x6000c004 0x14c>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio: gpio {
|
||||||
|
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
|
||||||
|
reg = <0x6000d000 0x1000>;
|
||||||
|
interrupts = <0 32 0x04
|
||||||
|
0 33 0x04
|
||||||
|
0 34 0x04
|
||||||
|
0 35 0x04
|
||||||
|
0 55 0x04
|
||||||
|
0 87 0x04
|
||||||
|
0 89 0x04
|
||||||
|
0 125 0x04>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux: pinmux {
|
||||||
|
compatible = "nvidia,tegra114-pinmux";
|
||||||
|
reg = <0x70000868 0x148 /* Pad control registers */
|
||||||
|
0x70003000 0x40c>; /* Mux registers */
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006000 {
|
||||||
|
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||||
|
reg = <0x70006000 0x40>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <0 36 0x04>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006040 {
|
||||||
|
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||||
|
reg = <0x70006040 0x40>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <0 37 0x04>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006200 {
|
||||||
|
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||||
|
reg = <0x70006200 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <0 46 0x04>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
serial@70006300 {
|
||||||
|
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
|
||||||
|
reg = <0x70006300 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
interrupts = <0 90 0x04>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc {
|
||||||
|
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
||||||
|
reg = <0x7000e000 0x100>;
|
||||||
|
interrupts = <0 2 0x04>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc {
|
||||||
|
compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
|
||||||
|
reg = <0x7000e400 0x400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
iommu {
|
||||||
|
compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
|
||||||
|
reg = <0x7000f010 0x02c
|
||||||
|
0x7000f1f0 0x010
|
||||||
|
0x7000f228 0x074>;
|
||||||
|
nvidia,#asids = <4>;
|
||||||
|
dma-window = <0 0x40000000>;
|
||||||
|
nvidia,swgroups = <0x18659fe>;
|
||||||
|
nvidia,ahb = <&ahb>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a15";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a15";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a15";
|
||||||
|
reg = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@3 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a15";
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv7-timer";
|
||||||
|
interrupts = <1 13 0xf08>,
|
||||||
|
<1 14 0xf08>,
|
||||||
|
<1 11 0xf08>,
|
||||||
|
<1 10 0xf08>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -432,6 +432,10 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb-phy@c5004400 {
|
||||||
|
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
|
||||||
|
};
|
||||||
|
|
||||||
sdhci@c8000200 {
|
sdhci@c8000200 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||||
|
|
|
||||||
|
|
@ -266,6 +266,8 @@
|
||||||
clock-frequency = <80000>;
|
clock-frequency = <80000>;
|
||||||
request-gpios = <&gpio 170 0>; /* gpio PV2 */
|
request-gpios = <&gpio 170 0>; /* gpio PV2 */
|
||||||
slave-addr = <138>;
|
slave-addr = <138>;
|
||||||
|
clocks = <&tegra_car 67>, <&tegra_car 124>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c@7000d000 {
|
i2c@7000d000 {
|
||||||
|
|
@ -418,6 +420,10 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb-phy@c5004400 {
|
||||||
|
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
|
||||||
|
};
|
||||||
|
|
||||||
sdhci@c8000000 {
|
sdhci@c8000000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
|
||||||
|
|
|
||||||
|
|
@ -561,6 +561,10 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb-phy@c5004400 {
|
||||||
|
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
|
||||||
|
};
|
||||||
|
|
||||||
sdhci@c8000000 {
|
sdhci@c8000000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
||||||
|
|
|
||||||
|
|
@ -310,6 +310,10 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb-phy@c5004400 {
|
||||||
|
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
|
||||||
|
};
|
||||||
|
|
||||||
sdhci@c8000000 {
|
sdhci@c8000000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
|
|
|
||||||
|
|
@ -497,6 +497,10 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
usb-phy@c5004400 {
|
||||||
|
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
|
||||||
|
};
|
||||||
|
|
||||||
sdhci@c8000000 {
|
sdhci@c8000000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
||||||
|
|
|
||||||
|
|
@ -9,6 +9,7 @@
|
||||||
reg = <0x50000000 0x00024000>;
|
reg = <0x50000000 0x00024000>;
|
||||||
interrupts = <0 65 0x04 /* mpcore syncpt */
|
interrupts = <0 65 0x04 /* mpcore syncpt */
|
||||||
0 67 0x04>; /* mpcore general */
|
0 67 0x04>; /* mpcore general */
|
||||||
|
clocks = <&tegra_car 28>;
|
||||||
|
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
@ -19,41 +20,49 @@
|
||||||
compatible = "nvidia,tegra20-mpe";
|
compatible = "nvidia,tegra20-mpe";
|
||||||
reg = <0x54040000 0x00040000>;
|
reg = <0x54040000 0x00040000>;
|
||||||
interrupts = <0 68 0x04>;
|
interrupts = <0 68 0x04>;
|
||||||
|
clocks = <&tegra_car 60>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vi {
|
vi {
|
||||||
compatible = "nvidia,tegra20-vi";
|
compatible = "nvidia,tegra20-vi";
|
||||||
reg = <0x54080000 0x00040000>;
|
reg = <0x54080000 0x00040000>;
|
||||||
interrupts = <0 69 0x04>;
|
interrupts = <0 69 0x04>;
|
||||||
|
clocks = <&tegra_car 100>;
|
||||||
};
|
};
|
||||||
|
|
||||||
epp {
|
epp {
|
||||||
compatible = "nvidia,tegra20-epp";
|
compatible = "nvidia,tegra20-epp";
|
||||||
reg = <0x540c0000 0x00040000>;
|
reg = <0x540c0000 0x00040000>;
|
||||||
interrupts = <0 70 0x04>;
|
interrupts = <0 70 0x04>;
|
||||||
|
clocks = <&tegra_car 19>;
|
||||||
};
|
};
|
||||||
|
|
||||||
isp {
|
isp {
|
||||||
compatible = "nvidia,tegra20-isp";
|
compatible = "nvidia,tegra20-isp";
|
||||||
reg = <0x54100000 0x00040000>;
|
reg = <0x54100000 0x00040000>;
|
||||||
interrupts = <0 71 0x04>;
|
interrupts = <0 71 0x04>;
|
||||||
|
clocks = <&tegra_car 23>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gr2d {
|
gr2d {
|
||||||
compatible = "nvidia,tegra20-gr2d";
|
compatible = "nvidia,tegra20-gr2d";
|
||||||
reg = <0x54140000 0x00040000>;
|
reg = <0x54140000 0x00040000>;
|
||||||
interrupts = <0 72 0x04>;
|
interrupts = <0 72 0x04>;
|
||||||
|
clocks = <&tegra_car 21>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gr3d {
|
gr3d {
|
||||||
compatible = "nvidia,tegra20-gr3d";
|
compatible = "nvidia,tegra20-gr3d";
|
||||||
reg = <0x54180000 0x00040000>;
|
reg = <0x54180000 0x00040000>;
|
||||||
|
clocks = <&tegra_car 24>;
|
||||||
};
|
};
|
||||||
|
|
||||||
dc@54200000 {
|
dc@54200000 {
|
||||||
compatible = "nvidia,tegra20-dc";
|
compatible = "nvidia,tegra20-dc";
|
||||||
reg = <0x54200000 0x00040000>;
|
reg = <0x54200000 0x00040000>;
|
||||||
interrupts = <0 73 0x04>;
|
interrupts = <0 73 0x04>;
|
||||||
|
clocks = <&tegra_car 27>, <&tegra_car 121>;
|
||||||
|
clock-names = "disp1", "parent";
|
||||||
|
|
||||||
rgb {
|
rgb {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -64,6 +73,8 @@
|
||||||
compatible = "nvidia,tegra20-dc";
|
compatible = "nvidia,tegra20-dc";
|
||||||
reg = <0x54240000 0x00040000>;
|
reg = <0x54240000 0x00040000>;
|
||||||
interrupts = <0 74 0x04>;
|
interrupts = <0 74 0x04>;
|
||||||
|
clocks = <&tegra_car 26>, <&tegra_car 121>;
|
||||||
|
clock-names = "disp2", "parent";
|
||||||
|
|
||||||
rgb {
|
rgb {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -74,6 +85,8 @@
|
||||||
compatible = "nvidia,tegra20-hdmi";
|
compatible = "nvidia,tegra20-hdmi";
|
||||||
reg = <0x54280000 0x00040000>;
|
reg = <0x54280000 0x00040000>;
|
||||||
interrupts = <0 75 0x04>;
|
interrupts = <0 75 0x04>;
|
||||||
|
clocks = <&tegra_car 51>, <&tegra_car 117>;
|
||||||
|
clock-names = "hdmi", "parent";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -81,12 +94,14 @@
|
||||||
compatible = "nvidia,tegra20-tvo";
|
compatible = "nvidia,tegra20-tvo";
|
||||||
reg = <0x542c0000 0x00040000>;
|
reg = <0x542c0000 0x00040000>;
|
||||||
interrupts = <0 76 0x04>;
|
interrupts = <0 76 0x04>;
|
||||||
|
clocks = <&tegra_car 102>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
dsi {
|
dsi {
|
||||||
compatible = "nvidia,tegra20-dsi";
|
compatible = "nvidia,tegra20-dsi";
|
||||||
reg = <0x54300000 0x00040000>;
|
reg = <0x54300000 0x00040000>;
|
||||||
|
clocks = <&tegra_car 48>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -123,6 +138,12 @@
|
||||||
0 42 0x04>;
|
0 42 0x04>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tegra_car: clock {
|
||||||
|
compatible = "nvidia,tegra20-car";
|
||||||
|
reg = <0x60006000 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
apbdma: dma {
|
apbdma: dma {
|
||||||
compatible = "nvidia,tegra20-apbdma";
|
compatible = "nvidia,tegra20-apbdma";
|
||||||
reg = <0x6000a000 0x1200>;
|
reg = <0x6000a000 0x1200>;
|
||||||
|
|
@ -142,6 +163,7 @@
|
||||||
0 117 0x04
|
0 117 0x04
|
||||||
0 118 0x04
|
0 118 0x04
|
||||||
0 119 0x04>;
|
0 119 0x04>;
|
||||||
|
clocks = <&tegra_car 34>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ahb {
|
ahb {
|
||||||
|
|
@ -183,6 +205,7 @@
|
||||||
reg = <0x70002800 0x200>;
|
reg = <0x70002800 0x200>;
|
||||||
interrupts = <0 13 0x04>;
|
interrupts = <0 13 0x04>;
|
||||||
nvidia,dma-request-selector = <&apbdma 2>;
|
nvidia,dma-request-selector = <&apbdma 2>;
|
||||||
|
clocks = <&tegra_car 11>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -191,6 +214,7 @@
|
||||||
reg = <0x70002a00 0x200>;
|
reg = <0x70002a00 0x200>;
|
||||||
interrupts = <0 3 0x04>;
|
interrupts = <0 3 0x04>;
|
||||||
nvidia,dma-request-selector = <&apbdma 1>;
|
nvidia,dma-request-selector = <&apbdma 1>;
|
||||||
|
clocks = <&tegra_car 18>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -199,6 +223,7 @@
|
||||||
reg = <0x70006000 0x40>;
|
reg = <0x70006000 0x40>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 36 0x04>;
|
interrupts = <0 36 0x04>;
|
||||||
|
clocks = <&tegra_car 6>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -207,6 +232,7 @@
|
||||||
reg = <0x70006040 0x40>;
|
reg = <0x70006040 0x40>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 37 0x04>;
|
interrupts = <0 37 0x04>;
|
||||||
|
clocks = <&tegra_car 96>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -215,6 +241,7 @@
|
||||||
reg = <0x70006200 0x100>;
|
reg = <0x70006200 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 46 0x04>;
|
interrupts = <0 46 0x04>;
|
||||||
|
clocks = <&tegra_car 55>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -223,6 +250,7 @@
|
||||||
reg = <0x70006300 0x100>;
|
reg = <0x70006300 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 90 0x04>;
|
interrupts = <0 90 0x04>;
|
||||||
|
clocks = <&tegra_car 65>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -231,6 +259,7 @@
|
||||||
reg = <0x70006400 0x100>;
|
reg = <0x70006400 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 91 0x04>;
|
interrupts = <0 91 0x04>;
|
||||||
|
clocks = <&tegra_car 66>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -238,6 +267,7 @@
|
||||||
compatible = "nvidia,tegra20-pwm";
|
compatible = "nvidia,tegra20-pwm";
|
||||||
reg = <0x7000a000 0x100>;
|
reg = <0x7000a000 0x100>;
|
||||||
#pwm-cells = <2>;
|
#pwm-cells = <2>;
|
||||||
|
clocks = <&tegra_car 17>;
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc {
|
rtc {
|
||||||
|
|
@ -252,6 +282,8 @@
|
||||||
interrupts = <0 38 0x04>;
|
interrupts = <0 38 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 12>, <&tegra_car 124>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -262,6 +294,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 11>;
|
nvidia,dma-request-selector = <&apbdma 11>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 43>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -271,6 +304,8 @@
|
||||||
interrupts = <0 84 0x04>;
|
interrupts = <0 84 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 54>, <&tegra_car 124>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -280,6 +315,8 @@
|
||||||
interrupts = <0 92 0x04>;
|
interrupts = <0 92 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 67>, <&tegra_car 124>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -289,6 +326,8 @@
|
||||||
interrupts = <0 53 0x04>;
|
interrupts = <0 53 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 47>, <&tegra_car 124>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -299,6 +338,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 15>;
|
nvidia,dma-request-selector = <&apbdma 15>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 41>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -309,6 +349,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 16>;
|
nvidia,dma-request-selector = <&apbdma 16>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 44>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -319,6 +360,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 17>;
|
nvidia,dma-request-selector = <&apbdma 17>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 46>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -329,6 +371,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 18>;
|
nvidia,dma-request-selector = <&apbdma 18>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 68>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -357,12 +400,40 @@
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
phy1: usb-phy@c5000400 {
|
||||||
|
compatible = "nvidia,tegra20-usb-phy";
|
||||||
|
reg = <0xc5000400 0x3c00>;
|
||||||
|
phy_type = "utmi";
|
||||||
|
nvidia,has-legacy-mode;
|
||||||
|
clocks = <&tegra_car 22>, <&tegra_car 127>;
|
||||||
|
clock-names = "phy", "pll_u";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy2: usb-phy@c5004400 {
|
||||||
|
compatible = "nvidia,tegra20-usb-phy";
|
||||||
|
reg = <0xc5004400 0x3c00>;
|
||||||
|
phy_type = "ulpi";
|
||||||
|
clocks = <&tegra_car 94>, <&tegra_car 127>;
|
||||||
|
clock-names = "phy", "pll_u";
|
||||||
|
};
|
||||||
|
|
||||||
|
phy3: usb-phy@c5008400 {
|
||||||
|
compatible = "nvidia,tegra20-usb-phy";
|
||||||
|
reg = <0xc5008400 0x3C00>;
|
||||||
|
phy_type = "utmi";
|
||||||
|
clocks = <&tegra_car 22>, <&tegra_car 127>;
|
||||||
|
clock-names = "phy", "pll_u";
|
||||||
|
};
|
||||||
|
|
||||||
usb@c5000000 {
|
usb@c5000000 {
|
||||||
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
||||||
reg = <0xc5000000 0x4000>;
|
reg = <0xc5000000 0x4000>;
|
||||||
interrupts = <0 20 0x04>;
|
interrupts = <0 20 0x04>;
|
||||||
phy_type = "utmi";
|
phy_type = "utmi";
|
||||||
nvidia,has-legacy-mode;
|
nvidia,has-legacy-mode;
|
||||||
|
clocks = <&tegra_car 22>;
|
||||||
|
nvidia,needs-double-reset;
|
||||||
|
nvidia,phy = <&phy1>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -371,6 +442,8 @@
|
||||||
reg = <0xc5004000 0x4000>;
|
reg = <0xc5004000 0x4000>;
|
||||||
interrupts = <0 21 0x04>;
|
interrupts = <0 21 0x04>;
|
||||||
phy_type = "ulpi";
|
phy_type = "ulpi";
|
||||||
|
clocks = <&tegra_car 58>;
|
||||||
|
nvidia,phy = <&phy2>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -379,6 +452,8 @@
|
||||||
reg = <0xc5008000 0x4000>;
|
reg = <0xc5008000 0x4000>;
|
||||||
interrupts = <0 97 0x04>;
|
interrupts = <0 97 0x04>;
|
||||||
phy_type = "utmi";
|
phy_type = "utmi";
|
||||||
|
clocks = <&tegra_car 59>;
|
||||||
|
nvidia,phy = <&phy3>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -386,6 +461,7 @@
|
||||||
compatible = "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra20-sdhci";
|
||||||
reg = <0xc8000000 0x200>;
|
reg = <0xc8000000 0x200>;
|
||||||
interrupts = <0 14 0x04>;
|
interrupts = <0 14 0x04>;
|
||||||
|
clocks = <&tegra_car 14>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -393,6 +469,7 @@
|
||||||
compatible = "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra20-sdhci";
|
||||||
reg = <0xc8000200 0x200>;
|
reg = <0xc8000200 0x200>;
|
||||||
interrupts = <0 15 0x04>;
|
interrupts = <0 15 0x04>;
|
||||||
|
clocks = <&tegra_car 9>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -400,6 +477,7 @@
|
||||||
compatible = "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra20-sdhci";
|
||||||
reg = <0xc8000400 0x200>;
|
reg = <0xc8000400 0x200>;
|
||||||
interrupts = <0 19 0x04>;
|
interrupts = <0 19 0x04>;
|
||||||
|
clocks = <&tegra_car 69>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -407,9 +485,27 @@
|
||||||
compatible = "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra20-sdhci";
|
||||||
reg = <0xc8000600 0x200>;
|
reg = <0xc8000600 0x200>;
|
||||||
interrupts = <0 31 0x04>;
|
interrupts = <0 31 0x04>;
|
||||||
|
clocks = <&tegra_car 15>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
pmu {
|
pmu {
|
||||||
compatible = "arm,cortex-a9-pmu";
|
compatible = "arm,cortex-a9-pmu";
|
||||||
interrupts = <0 56 0x04
|
interrupts = <0 56 0x04
|
||||||
|
|
|
||||||
|
|
@ -9,6 +9,7 @@
|
||||||
reg = <0x50000000 0x00024000>;
|
reg = <0x50000000 0x00024000>;
|
||||||
interrupts = <0 65 0x04 /* mpcore syncpt */
|
interrupts = <0 65 0x04 /* mpcore syncpt */
|
||||||
0 67 0x04>; /* mpcore general */
|
0 67 0x04>; /* mpcore general */
|
||||||
|
clocks = <&tegra_car 28>;
|
||||||
|
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
@ -19,41 +20,50 @@
|
||||||
compatible = "nvidia,tegra30-mpe";
|
compatible = "nvidia,tegra30-mpe";
|
||||||
reg = <0x54040000 0x00040000>;
|
reg = <0x54040000 0x00040000>;
|
||||||
interrupts = <0 68 0x04>;
|
interrupts = <0 68 0x04>;
|
||||||
|
clocks = <&tegra_car 60>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vi {
|
vi {
|
||||||
compatible = "nvidia,tegra30-vi";
|
compatible = "nvidia,tegra30-vi";
|
||||||
reg = <0x54080000 0x00040000>;
|
reg = <0x54080000 0x00040000>;
|
||||||
interrupts = <0 69 0x04>;
|
interrupts = <0 69 0x04>;
|
||||||
|
clocks = <&tegra_car 164>;
|
||||||
};
|
};
|
||||||
|
|
||||||
epp {
|
epp {
|
||||||
compatible = "nvidia,tegra30-epp";
|
compatible = "nvidia,tegra30-epp";
|
||||||
reg = <0x540c0000 0x00040000>;
|
reg = <0x540c0000 0x00040000>;
|
||||||
interrupts = <0 70 0x04>;
|
interrupts = <0 70 0x04>;
|
||||||
|
clocks = <&tegra_car 19>;
|
||||||
};
|
};
|
||||||
|
|
||||||
isp {
|
isp {
|
||||||
compatible = "nvidia,tegra30-isp";
|
compatible = "nvidia,tegra30-isp";
|
||||||
reg = <0x54100000 0x00040000>;
|
reg = <0x54100000 0x00040000>;
|
||||||
interrupts = <0 71 0x04>;
|
interrupts = <0 71 0x04>;
|
||||||
|
clocks = <&tegra_car 23>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gr2d {
|
gr2d {
|
||||||
compatible = "nvidia,tegra30-gr2d";
|
compatible = "nvidia,tegra30-gr2d";
|
||||||
reg = <0x54140000 0x00040000>;
|
reg = <0x54140000 0x00040000>;
|
||||||
interrupts = <0 72 0x04>;
|
interrupts = <0 72 0x04>;
|
||||||
|
clocks = <&tegra_car 21>;
|
||||||
};
|
};
|
||||||
|
|
||||||
gr3d {
|
gr3d {
|
||||||
compatible = "nvidia,tegra30-gr3d";
|
compatible = "nvidia,tegra30-gr3d";
|
||||||
reg = <0x54180000 0x00040000>;
|
reg = <0x54180000 0x00040000>;
|
||||||
|
clocks = <&tegra_car 24 &tegra_car 98>;
|
||||||
|
clock-names = "3d", "3d2";
|
||||||
};
|
};
|
||||||
|
|
||||||
dc@54200000 {
|
dc@54200000 {
|
||||||
compatible = "nvidia,tegra30-dc";
|
compatible = "nvidia,tegra30-dc";
|
||||||
reg = <0x54200000 0x00040000>;
|
reg = <0x54200000 0x00040000>;
|
||||||
interrupts = <0 73 0x04>;
|
interrupts = <0 73 0x04>;
|
||||||
|
clocks = <&tegra_car 27>, <&tegra_car 179>;
|
||||||
|
clock-names = "disp1", "parent";
|
||||||
|
|
||||||
rgb {
|
rgb {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -64,6 +74,8 @@
|
||||||
compatible = "nvidia,tegra30-dc";
|
compatible = "nvidia,tegra30-dc";
|
||||||
reg = <0x54240000 0x00040000>;
|
reg = <0x54240000 0x00040000>;
|
||||||
interrupts = <0 74 0x04>;
|
interrupts = <0 74 0x04>;
|
||||||
|
clocks = <&tegra_car 26>, <&tegra_car 179>;
|
||||||
|
clock-names = "disp2", "parent";
|
||||||
|
|
||||||
rgb {
|
rgb {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -74,6 +86,8 @@
|
||||||
compatible = "nvidia,tegra30-hdmi";
|
compatible = "nvidia,tegra30-hdmi";
|
||||||
reg = <0x54280000 0x00040000>;
|
reg = <0x54280000 0x00040000>;
|
||||||
interrupts = <0 75 0x04>;
|
interrupts = <0 75 0x04>;
|
||||||
|
clocks = <&tegra_car 51>, <&tegra_car 189>;
|
||||||
|
clock-names = "hdmi", "parent";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -81,12 +95,14 @@
|
||||||
compatible = "nvidia,tegra30-tvo";
|
compatible = "nvidia,tegra30-tvo";
|
||||||
reg = <0x542c0000 0x00040000>;
|
reg = <0x542c0000 0x00040000>;
|
||||||
interrupts = <0 76 0x04>;
|
interrupts = <0 76 0x04>;
|
||||||
|
clocks = <&tegra_car 169>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
dsi {
|
dsi {
|
||||||
compatible = "nvidia,tegra30-dsi";
|
compatible = "nvidia,tegra30-dsi";
|
||||||
reg = <0x54300000 0x00040000>;
|
reg = <0x54300000 0x00040000>;
|
||||||
|
clocks = <&tegra_car 48>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -125,6 +141,12 @@
|
||||||
0 122 0x04>;
|
0 122 0x04>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tegra_car: clock {
|
||||||
|
compatible = "nvidia,tegra30-car";
|
||||||
|
reg = <0x60006000 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
apbdma: dma {
|
apbdma: dma {
|
||||||
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
||||||
reg = <0x6000a000 0x1400>;
|
reg = <0x6000a000 0x1400>;
|
||||||
|
|
@ -160,6 +182,7 @@
|
||||||
0 141 0x04
|
0 141 0x04
|
||||||
0 142 0x04
|
0 142 0x04
|
||||||
0 143 0x04>;
|
0 143 0x04>;
|
||||||
|
clocks = <&tegra_car 34>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ahb: ahb {
|
ahb: ahb {
|
||||||
|
|
@ -195,6 +218,7 @@
|
||||||
reg = <0x70006000 0x40>;
|
reg = <0x70006000 0x40>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 36 0x04>;
|
interrupts = <0 36 0x04>;
|
||||||
|
clocks = <&tegra_car 6>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -203,6 +227,7 @@
|
||||||
reg = <0x70006040 0x40>;
|
reg = <0x70006040 0x40>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 37 0x04>;
|
interrupts = <0 37 0x04>;
|
||||||
|
clocks = <&tegra_car 160>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -211,6 +236,7 @@
|
||||||
reg = <0x70006200 0x100>;
|
reg = <0x70006200 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 46 0x04>;
|
interrupts = <0 46 0x04>;
|
||||||
|
clocks = <&tegra_car 55>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -219,6 +245,7 @@
|
||||||
reg = <0x70006300 0x100>;
|
reg = <0x70006300 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 90 0x04>;
|
interrupts = <0 90 0x04>;
|
||||||
|
clocks = <&tegra_car 65>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -227,6 +254,7 @@
|
||||||
reg = <0x70006400 0x100>;
|
reg = <0x70006400 0x100>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
interrupts = <0 91 0x04>;
|
interrupts = <0 91 0x04>;
|
||||||
|
clocks = <&tegra_car 66>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -234,6 +262,7 @@
|
||||||
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
|
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
|
||||||
reg = <0x7000a000 0x100>;
|
reg = <0x7000a000 0x100>;
|
||||||
#pwm-cells = <2>;
|
#pwm-cells = <2>;
|
||||||
|
clocks = <&tegra_car 17>;
|
||||||
};
|
};
|
||||||
|
|
||||||
rtc {
|
rtc {
|
||||||
|
|
@ -248,6 +277,8 @@
|
||||||
interrupts = <0 38 0x04>;
|
interrupts = <0 38 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 12>, <&tegra_car 182>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -257,6 +288,8 @@
|
||||||
interrupts = <0 84 0x04>;
|
interrupts = <0 84 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 54>, <&tegra_car 182>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -266,6 +299,8 @@
|
||||||
interrupts = <0 92 0x04>;
|
interrupts = <0 92 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 67>, <&tegra_car 182>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -275,6 +310,8 @@
|
||||||
interrupts = <0 120 0x04>;
|
interrupts = <0 120 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 103>, <&tegra_car 182>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -284,6 +321,8 @@
|
||||||
interrupts = <0 53 0x04>;
|
interrupts = <0 53 0x04>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 47>, <&tegra_car 182>;
|
||||||
|
clock-names = "div-clk", "fast-clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -294,6 +333,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 15>;
|
nvidia,dma-request-selector = <&apbdma 15>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 41>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -304,6 +344,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 16>;
|
nvidia,dma-request-selector = <&apbdma 16>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 44>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -314,6 +355,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 17>;
|
nvidia,dma-request-selector = <&apbdma 17>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 46>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -324,6 +366,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 18>;
|
nvidia,dma-request-selector = <&apbdma 18>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 68>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -334,6 +377,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 27>;
|
nvidia,dma-request-selector = <&apbdma 27>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 104>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -344,6 +388,7 @@
|
||||||
nvidia,dma-request-selector = <&apbdma 28>;
|
nvidia,dma-request-selector = <&apbdma 28>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
clocks = <&tegra_car 105>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -377,7 +422,13 @@
|
||||||
0x70080200 0x100>;
|
0x70080200 0x100>;
|
||||||
interrupts = <0 103 0x04>;
|
interrupts = <0 103 0x04>;
|
||||||
nvidia,dma-request-selector = <&apbdma 1>;
|
nvidia,dma-request-selector = <&apbdma 1>;
|
||||||
|
clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
|
||||||
|
<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
|
||||||
|
<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
|
||||||
|
<&tegra_car 110>, <&tegra_car 162>;
|
||||||
|
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
||||||
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
||||||
|
"spdif_in";
|
||||||
ranges;
|
ranges;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
@ -386,6 +437,7 @@
|
||||||
compatible = "nvidia,tegra30-i2s";
|
compatible = "nvidia,tegra30-i2s";
|
||||||
reg = <0x70080300 0x100>;
|
reg = <0x70080300 0x100>;
|
||||||
nvidia,ahub-cif-ids = <4 4>;
|
nvidia,ahub-cif-ids = <4 4>;
|
||||||
|
clocks = <&tegra_car 30>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -393,6 +445,7 @@
|
||||||
compatible = "nvidia,tegra30-i2s";
|
compatible = "nvidia,tegra30-i2s";
|
||||||
reg = <0x70080400 0x100>;
|
reg = <0x70080400 0x100>;
|
||||||
nvidia,ahub-cif-ids = <5 5>;
|
nvidia,ahub-cif-ids = <5 5>;
|
||||||
|
clocks = <&tegra_car 11>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -400,6 +453,7 @@
|
||||||
compatible = "nvidia,tegra30-i2s";
|
compatible = "nvidia,tegra30-i2s";
|
||||||
reg = <0x70080500 0x100>;
|
reg = <0x70080500 0x100>;
|
||||||
nvidia,ahub-cif-ids = <6 6>;
|
nvidia,ahub-cif-ids = <6 6>;
|
||||||
|
clocks = <&tegra_car 18>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -407,6 +461,7 @@
|
||||||
compatible = "nvidia,tegra30-i2s";
|
compatible = "nvidia,tegra30-i2s";
|
||||||
reg = <0x70080600 0x100>;
|
reg = <0x70080600 0x100>;
|
||||||
nvidia,ahub-cif-ids = <7 7>;
|
nvidia,ahub-cif-ids = <7 7>;
|
||||||
|
clocks = <&tegra_car 101>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -414,6 +469,7 @@
|
||||||
compatible = "nvidia,tegra30-i2s";
|
compatible = "nvidia,tegra30-i2s";
|
||||||
reg = <0x70080700 0x100>;
|
reg = <0x70080700 0x100>;
|
||||||
nvidia,ahub-cif-ids = <8 8>;
|
nvidia,ahub-cif-ids = <8 8>;
|
||||||
|
clocks = <&tegra_car 102>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
@ -422,6 +478,7 @@
|
||||||
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
||||||
reg = <0x78000000 0x200>;
|
reg = <0x78000000 0x200>;
|
||||||
interrupts = <0 14 0x04>;
|
interrupts = <0 14 0x04>;
|
||||||
|
clocks = <&tegra_car 14>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -429,6 +486,7 @@
|
||||||
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
||||||
reg = <0x78000200 0x200>;
|
reg = <0x78000200 0x200>;
|
||||||
interrupts = <0 15 0x04>;
|
interrupts = <0 15 0x04>;
|
||||||
|
clocks = <&tegra_car 9>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -436,6 +494,7 @@
|
||||||
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
||||||
reg = <0x78000400 0x200>;
|
reg = <0x78000400 0x200>;
|
||||||
interrupts = <0 19 0x04>;
|
interrupts = <0 19 0x04>;
|
||||||
|
clocks = <&tegra_car 69>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -443,9 +502,39 @@
|
||||||
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
||||||
reg = <0x78000600 0x200>;
|
reg = <0x78000600 0x200>;
|
||||||
interrupts = <0 31 0x04>;
|
interrupts = <0 31 0x04>;
|
||||||
|
clocks = <&tegra_car 15>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@3 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,cortex-a9";
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
pmu {
|
pmu {
|
||||||
compatible = "arm,cortex-a9-pmu";
|
compatible = "arm,cortex-a9-pmu";
|
||||||
interrupts = <0 144 0x04
|
interrupts = <0 144 0x04
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
/*
|
||||||
|
* wm8850-w70v2.dts
|
||||||
|
* - Device tree file for Wondermedia WM8850 Tablet
|
||||||
|
* - 'W70-V2' mainboard
|
||||||
|
* - HongLianYing 'HLY070ML268-21A' 7" LCD panel
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/include/ "wm8850.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Wondermedia WM8850-W70v2 Tablet";
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Display node is based on Sascha Hauer's patch on dri-devel.
|
||||||
|
* Added a bpp property to calculate the size of the framebuffer
|
||||||
|
* until the binding is formalized.
|
||||||
|
*/
|
||||||
|
display: display@0 {
|
||||||
|
modes {
|
||||||
|
mode0: mode@0 {
|
||||||
|
hactive = <800>;
|
||||||
|
vactive = <480>;
|
||||||
|
hback-porch = <88>;
|
||||||
|
hfront-porch = <40>;
|
||||||
|
hsync-len = <0>;
|
||||||
|
vback-porch = <32>;
|
||||||
|
vfront-porch = <11>;
|
||||||
|
vsync-len = <1>;
|
||||||
|
clock = <0>; /* unused but required */
|
||||||
|
bpp = <16>; /* non-standard but required */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
backlight {
|
||||||
|
compatible = "pwm-backlight";
|
||||||
|
pwms = <&pwm 0 50000 1>; /* duty inverted */
|
||||||
|
|
||||||
|
brightness-levels = <0 40 60 80 100 130 190 255>;
|
||||||
|
default-brightness-level = <5>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,224 @@
|
||||||
|
/*
|
||||||
|
* wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "wm,wm8850";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
serial1 = &uart1;
|
||||||
|
serial2 = &uart2;
|
||||||
|
serial3 = &uart3;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "simple-bus";
|
||||||
|
ranges;
|
||||||
|
interrupt-parent = <&intc0>;
|
||||||
|
|
||||||
|
intc0: interrupt-controller@d8140000 {
|
||||||
|
compatible = "via,vt8500-intc";
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0xd8140000 0x10000>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Secondary IC cascaded to intc0 */
|
||||||
|
intc1: interrupt-controller@d8150000 {
|
||||||
|
compatible = "via,vt8500-intc";
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
reg = <0xD8150000 0x10000>;
|
||||||
|
interrupts = <56 57 58 59 60 61 62 63>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio: gpio-controller@d8110000 {
|
||||||
|
compatible = "wm,wm8650-gpio";
|
||||||
|
gpio-controller;
|
||||||
|
reg = <0xd8110000 0x10000>;
|
||||||
|
#gpio-cells = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc@d8130000 {
|
||||||
|
compatible = "via,vt8500-pmc";
|
||||||
|
reg = <0xd8130000 0x1000>;
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
ref25: ref25M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <25000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ref24: ref24M {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <24000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
plla: plla {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "wm,wm8750-pll-clock";
|
||||||
|
clocks = <&ref25>;
|
||||||
|
reg = <0x200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pllb: pllb {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "wm,wm8750-pll-clock";
|
||||||
|
clocks = <&ref25>;
|
||||||
|
reg = <0x204>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkuart0: uart0 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&ref24>;
|
||||||
|
enable-reg = <0x254>;
|
||||||
|
enable-bit = <24>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkuart1: uart1 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&ref24>;
|
||||||
|
enable-reg = <0x254>;
|
||||||
|
enable-bit = <25>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkuart2: uart2 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&ref24>;
|
||||||
|
enable-reg = <0x254>;
|
||||||
|
enable-bit = <26>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkuart3: uart3 {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&ref24>;
|
||||||
|
enable-reg = <0x254>;
|
||||||
|
enable-bit = <27>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkpwm: pwm {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&pllb>;
|
||||||
|
divisor-reg = <0x350>;
|
||||||
|
enable-reg = <0x250>;
|
||||||
|
enable-bit = <17>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clksdhc: sdhc {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "via,vt8500-device-clock";
|
||||||
|
clocks = <&pllb>;
|
||||||
|
divisor-reg = <0x330>;
|
||||||
|
divisor-mask = <0x3f>;
|
||||||
|
enable-reg = <0x250>;
|
||||||
|
enable-bit = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fb@d8051700 {
|
||||||
|
compatible = "wm,wm8505-fb";
|
||||||
|
reg = <0xd8051700 0x200>;
|
||||||
|
display = <&display>;
|
||||||
|
default-mode = <&mode0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ge_rops@d8050400 {
|
||||||
|
compatible = "wm,prizm-ge-rops";
|
||||||
|
reg = <0xd8050400 0x100>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pwm: pwm@d8220000 {
|
||||||
|
#pwm-cells = <3>;
|
||||||
|
compatible = "via,vt8500-pwm";
|
||||||
|
reg = <0xd8220000 0x100>;
|
||||||
|
clocks = <&clkpwm>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@d8130100 {
|
||||||
|
compatible = "via,vt8500-timer";
|
||||||
|
reg = <0xd8130100 0x28>;
|
||||||
|
interrupts = <36>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ehci@d8007900 {
|
||||||
|
compatible = "via,vt8500-ehci";
|
||||||
|
reg = <0xd8007900 0x200>;
|
||||||
|
interrupts = <26>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uhci@d8007b00 {
|
||||||
|
compatible = "platform-uhci";
|
||||||
|
reg = <0xd8007b00 0x200>;
|
||||||
|
interrupts = <26>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uhci@d8008d00 {
|
||||||
|
compatible = "platform-uhci";
|
||||||
|
reg = <0xd8008d00 0x200>;
|
||||||
|
interrupts = <26>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: uart@d8200000 {
|
||||||
|
compatible = "via,vt8500-uart";
|
||||||
|
reg = <0xd8200000 0x1040>;
|
||||||
|
interrupts = <32>;
|
||||||
|
clocks = <&clkuart0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: uart@d82b0000 {
|
||||||
|
compatible = "via,vt8500-uart";
|
||||||
|
reg = <0xd82b0000 0x1040>;
|
||||||
|
interrupts = <33>;
|
||||||
|
clocks = <&clkuart1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart2: uart@d8210000 {
|
||||||
|
compatible = "via,vt8500-uart";
|
||||||
|
reg = <0xd8210000 0x1040>;
|
||||||
|
interrupts = <47>;
|
||||||
|
clocks = <&clkuart2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart3: uart@d82c0000 {
|
||||||
|
compatible = "via,vt8500-uart";
|
||||||
|
reg = <0xd82c0000 0x1040>;
|
||||||
|
interrupts = <50>;
|
||||||
|
clocks = <&clkuart3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@d8100000 {
|
||||||
|
compatible = "via,vt8500-rtc";
|
||||||
|
reg = <0xd8100000 0x10000>;
|
||||||
|
interrupts = <48>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhc@d800a000 {
|
||||||
|
compatible = "wm,wm8505-sdhc";
|
||||||
|
reg = <0xd800a000 0x1000>;
|
||||||
|
interrupts = <20 21>;
|
||||||
|
clocks = <&clksdhc>;
|
||||||
|
bus-width = <4>;
|
||||||
|
sdon-inverted;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -19,6 +19,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
|
||||||
CONFIG_ARCH_MXC=y
|
CONFIG_ARCH_MXC=y
|
||||||
CONFIG_ARCH_MULTI_V6=y
|
CONFIG_ARCH_MULTI_V6=y
|
||||||
CONFIG_ARCH_MULTI_V7=y
|
CONFIG_ARCH_MULTI_V7=y
|
||||||
|
CONFIG_MACH_IMX31_DT=y
|
||||||
CONFIG_MACH_MX31LILLY=y
|
CONFIG_MACH_MX31LILLY=y
|
||||||
CONFIG_MACH_MX31LITE=y
|
CONFIG_MACH_MX31LITE=y
|
||||||
CONFIG_MACH_PCM037=y
|
CONFIG_MACH_PCM037=y
|
||||||
|
|
@ -150,6 +151,7 @@ CONFIG_MFD_MC13XXX_I2C=y
|
||||||
CONFIG_REGULATOR=y
|
CONFIG_REGULATOR=y
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||||
CONFIG_REGULATOR_DA9052=y
|
CONFIG_REGULATOR_DA9052=y
|
||||||
|
CONFIG_REGULATOR_ANATOP=y
|
||||||
CONFIG_REGULATOR_MC13783=y
|
CONFIG_REGULATOR_MC13783=y
|
||||||
CONFIG_REGULATOR_MC13892=y
|
CONFIG_REGULATOR_MC13892=y
|
||||||
CONFIG_MEDIA_SUPPORT=y
|
CONFIG_MEDIA_SUPPORT=y
|
||||||
|
|
@ -158,6 +160,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||||
CONFIG_SOC_CAMERA=y
|
CONFIG_SOC_CAMERA=y
|
||||||
CONFIG_SOC_CAMERA_OV2640=y
|
CONFIG_SOC_CAMERA_OV2640=y
|
||||||
|
CONFIG_DRM=y
|
||||||
CONFIG_VIDEO_MX3=y
|
CONFIG_VIDEO_MX3=y
|
||||||
CONFIG_FB=y
|
CONFIG_FB=y
|
||||||
CONFIG_LCD_PLATFORM=y
|
CONFIG_LCD_PLATFORM=y
|
||||||
|
|
@ -196,9 +199,14 @@ CONFIG_RTC_CLASS=y
|
||||||
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
||||||
CONFIG_RTC_DRV_MC13XXX=y
|
CONFIG_RTC_DRV_MC13XXX=y
|
||||||
CONFIG_RTC_DRV_MXC=y
|
CONFIG_RTC_DRV_MXC=y
|
||||||
|
CONFIG_RTC_DRV_SNVS=y
|
||||||
CONFIG_DMADEVICES=y
|
CONFIG_DMADEVICES=y
|
||||||
CONFIG_IMX_SDMA=y
|
CONFIG_IMX_SDMA=y
|
||||||
CONFIG_MXS_DMA=y
|
CONFIG_MXS_DMA=y
|
||||||
|
CONFIG_STAGING=y
|
||||||
|
CONFIG_DRM_IMX=y
|
||||||
|
CONFIG_DRM_IMX_IPUV3_CORE=y
|
||||||
|
CONFIG_DRM_IMX_IPUV3=y
|
||||||
CONFIG_COMMON_CLK_DEBUG=y
|
CONFIG_COMMON_CLK_DEBUG=y
|
||||||
# CONFIG_IOMMU_SUPPORT is not set
|
# CONFIG_IOMMU_SUPPORT is not set
|
||||||
CONFIG_EXT2_FS=y
|
CONFIG_EXT2_FS=y
|
||||||
|
|
|
||||||
|
|
@ -56,6 +56,7 @@ CONFIG_AEABI=y
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||||
CONFIG_CPU_IDLE=y
|
CONFIG_CPU_IDLE=y
|
||||||
|
CONFIG_CPU_IDLE_KIRKWOOD=y
|
||||||
CONFIG_NET=y
|
CONFIG_NET=y
|
||||||
CONFIG_PACKET=y
|
CONFIG_PACKET=y
|
||||||
CONFIG_UNIX=y
|
CONFIG_UNIX=y
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,7 @@
|
||||||
CONFIG_EXPERIMENTAL=y
|
CONFIG_EXPERIMENTAL=y
|
||||||
CONFIG_SYSVIPC=y
|
CONFIG_SYSVIPC=y
|
||||||
|
CONFIG_NO_HZ=y
|
||||||
|
CONFIG_HIGH_RES_TIMERS=y
|
||||||
CONFIG_TASKSTATS=y
|
CONFIG_TASKSTATS=y
|
||||||
CONFIG_TASK_DELAY_ACCT=y
|
CONFIG_TASK_DELAY_ACCT=y
|
||||||
CONFIG_TASK_XACCT=y
|
CONFIG_TASK_XACCT=y
|
||||||
|
|
@ -8,7 +10,6 @@ CONFIG_IKCONFIG=y
|
||||||
CONFIG_IKCONFIG_PROC=y
|
CONFIG_IKCONFIG_PROC=y
|
||||||
# CONFIG_UTS_NS is not set
|
# CONFIG_UTS_NS is not set
|
||||||
# CONFIG_IPC_NS is not set
|
# CONFIG_IPC_NS is not set
|
||||||
# CONFIG_USER_NS is not set
|
|
||||||
# CONFIG_PID_NS is not set
|
# CONFIG_PID_NS is not set
|
||||||
# CONFIG_NET_NS is not set
|
# CONFIG_NET_NS is not set
|
||||||
CONFIG_PERF_EVENTS=y
|
CONFIG_PERF_EVENTS=y
|
||||||
|
|
@ -24,8 +25,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
|
||||||
CONFIG_ARCH_MXS=y
|
CONFIG_ARCH_MXS=y
|
||||||
CONFIG_MACH_MXS_DT=y
|
CONFIG_MACH_MXS_DT=y
|
||||||
# CONFIG_ARM_THUMB is not set
|
# CONFIG_ARM_THUMB is not set
|
||||||
CONFIG_NO_HZ=y
|
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
|
||||||
CONFIG_PREEMPT_VOLUNTARY=y
|
CONFIG_PREEMPT_VOLUNTARY=y
|
||||||
CONFIG_AEABI=y
|
CONFIG_AEABI=y
|
||||||
CONFIG_AUTO_ZRELADDR=y
|
CONFIG_AUTO_ZRELADDR=y
|
||||||
|
|
@ -46,25 +45,34 @@ CONFIG_SYN_COOKIES=y
|
||||||
CONFIG_CAN=m
|
CONFIG_CAN=m
|
||||||
CONFIG_CAN_RAW=m
|
CONFIG_CAN_RAW=m
|
||||||
CONFIG_CAN_BCM=m
|
CONFIG_CAN_BCM=m
|
||||||
CONFIG_CAN_DEV=m
|
|
||||||
CONFIG_CAN_FLEXCAN=m
|
CONFIG_CAN_FLEXCAN=m
|
||||||
# CONFIG_WIRELESS is not set
|
# CONFIG_WIRELESS is not set
|
||||||
CONFIG_DEVTMPFS=y
|
CONFIG_DEVTMPFS=y
|
||||||
|
CONFIG_DEVTMPFS_MOUNT=y
|
||||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||||
# CONFIG_BLK_DEV is not set
|
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
|
CONFIG_MTD_CMDLINE_PARTS=y
|
||||||
CONFIG_MTD_CHAR=y
|
CONFIG_MTD_CHAR=y
|
||||||
|
CONFIG_MTD_BLOCK=y
|
||||||
CONFIG_MTD_DATAFLASH=y
|
CONFIG_MTD_DATAFLASH=y
|
||||||
CONFIG_MTD_M25P80
|
CONFIG_MTD_M25P80=y
|
||||||
|
# CONFIG_M25PXX_USE_FAST_READ is not set
|
||||||
|
CONFIG_MTD_SST25L=y
|
||||||
CONFIG_MTD_NAND=y
|
CONFIG_MTD_NAND=y
|
||||||
CONFIG_MTD_NAND_GPMI_NAND=y
|
CONFIG_MTD_NAND_GPMI_NAND=y
|
||||||
|
CONFIG_MTD_UBI=y
|
||||||
|
# CONFIG_BLK_DEV is not set
|
||||||
|
CONFIG_EEPROM_AT24=y
|
||||||
|
CONFIG_SCSI=y
|
||||||
|
CONFIG_BLK_DEV_SD=y
|
||||||
CONFIG_NETDEVICES=y
|
CONFIG_NETDEVICES=y
|
||||||
CONFIG_NET_ETHERNET=y
|
|
||||||
CONFIG_ENC28J60=y
|
CONFIG_ENC28J60=y
|
||||||
CONFIG_USB_USBNET=y
|
CONFIG_USB_USBNET=y
|
||||||
CONFIG_USB_NET_SMSC95XX=y
|
CONFIG_USB_NET_SMSC95XX=y
|
||||||
# CONFIG_NETDEV_1000 is not set
|
CONFIG_SMSC_PHY=y
|
||||||
# CONFIG_NETDEV_10000 is not set
|
CONFIG_ICPLUS_PHY=y
|
||||||
|
CONFIG_REALTEK_PHY=y
|
||||||
|
CONFIG_MICREL_PHY=y
|
||||||
# CONFIG_WLAN is not set
|
# CONFIG_WLAN is not set
|
||||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||||
CONFIG_INPUT_EVDEV=m
|
CONFIG_INPUT_EVDEV=m
|
||||||
|
|
@ -91,21 +99,6 @@ CONFIG_SPI_MXS=y
|
||||||
CONFIG_DEBUG_GPIO=y
|
CONFIG_DEBUG_GPIO=y
|
||||||
CONFIG_GPIO_SYSFS=y
|
CONFIG_GPIO_SYSFS=y
|
||||||
# CONFIG_HWMON is not set
|
# CONFIG_HWMON is not set
|
||||||
# CONFIG_MFD_SUPPORT is not set
|
|
||||||
CONFIG_DISPLAY_SUPPORT=m
|
|
||||||
# CONFIG_HID_SUPPORT is not set
|
|
||||||
CONFIG_SOUND=y
|
|
||||||
CONFIG_SND=y
|
|
||||||
CONFIG_SND_TIMER=y
|
|
||||||
CONFIG_SND_PCM=y
|
|
||||||
CONFIG_SND_JACK=y
|
|
||||||
CONFIG_SND_DRIVERS=y
|
|
||||||
CONFIG_SND_ARM=y
|
|
||||||
CONFIG_SND_SOC=y
|
|
||||||
CONFIG_SND_MXS_SOC=y
|
|
||||||
CONFIG_SND_SOC_MXS_SGTL5000=y
|
|
||||||
CONFIG_SND_SOC_I2C_AND_SPI=y
|
|
||||||
CONFIG_SND_SOC_SGTL5000=y
|
|
||||||
CONFIG_REGULATOR=y
|
CONFIG_REGULATOR=y
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||||
CONFIG_FB=y
|
CONFIG_FB=y
|
||||||
|
|
@ -117,13 +110,16 @@ CONFIG_BACKLIGHT_PWM=y
|
||||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||||
CONFIG_FONTS=y
|
CONFIG_FONTS=y
|
||||||
CONFIG_LOGO=y
|
CONFIG_LOGO=y
|
||||||
|
CONFIG_SOUND=y
|
||||||
|
CONFIG_SND=y
|
||||||
|
CONFIG_SND_SOC=y
|
||||||
|
CONFIG_SND_MXS_SOC=y
|
||||||
|
CONFIG_SND_SOC_MXS_SGTL5000=y
|
||||||
CONFIG_USB=y
|
CONFIG_USB=y
|
||||||
CONFIG_USB_CHIPIDEA=y
|
CONFIG_USB_CHIPIDEA=y
|
||||||
CONFIG_USB_CHIPIDEA_HOST=y
|
CONFIG_USB_CHIPIDEA_HOST=y
|
||||||
CONFIG_USB_STORAGE=y
|
CONFIG_USB_STORAGE=y
|
||||||
CONFIG_USB_MXS_PHY=y
|
CONFIG_USB_MXS_PHY=y
|
||||||
CONFIG_SCSI=y
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_MMC=y
|
CONFIG_MMC=y
|
||||||
CONFIG_MMC_MXS=y
|
CONFIG_MMC_MXS=y
|
||||||
CONFIG_NEW_LEDS=y
|
CONFIG_NEW_LEDS=y
|
||||||
|
|
@ -147,16 +143,23 @@ CONFIG_COMMON_CLK_DEBUG=y
|
||||||
CONFIG_IIO=y
|
CONFIG_IIO=y
|
||||||
CONFIG_PWM=y
|
CONFIG_PWM=y
|
||||||
CONFIG_PWM_MXS=y
|
CONFIG_PWM_MXS=y
|
||||||
|
CONFIG_EXT2_FS=y
|
||||||
|
CONFIG_EXT2_FS_XATTR=y
|
||||||
CONFIG_EXT3_FS=y
|
CONFIG_EXT3_FS=y
|
||||||
|
CONFIG_EXT4_FS=y
|
||||||
# CONFIG_DNOTIFY is not set
|
# CONFIG_DNOTIFY is not set
|
||||||
CONFIG_FSCACHE=m
|
CONFIG_FSCACHE=m
|
||||||
CONFIG_FSCACHE_STATS=y
|
CONFIG_FSCACHE_STATS=y
|
||||||
CONFIG_CACHEFILES=m
|
CONFIG_CACHEFILES=m
|
||||||
CONFIG_TMPFS=y
|
CONFIG_TMPFS=y
|
||||||
CONFIG_TMPFS_POSIX_ACL=y
|
CONFIG_TMPFS_POSIX_ACL=y
|
||||||
# CONFIG_MISC_FILESYSTEMS is not set
|
CONFIG_JFFS2_FS=y
|
||||||
|
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||||
|
CONFIG_JFFS2_LZO=y
|
||||||
|
CONFIG_JFFS2_RUBIN=y
|
||||||
|
CONFIG_UBIFS_FS=y
|
||||||
|
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||||
CONFIG_NFS_FS=y
|
CONFIG_NFS_FS=y
|
||||||
CONFIG_NFS_V3=y
|
|
||||||
CONFIG_NFS_V3_ACL=y
|
CONFIG_NFS_V3_ACL=y
|
||||||
CONFIG_NFS_V4=y
|
CONFIG_NFS_V4=y
|
||||||
CONFIG_ROOT_NFS=y
|
CONFIG_ROOT_NFS=y
|
||||||
|
|
@ -170,17 +173,12 @@ CONFIG_MAGIC_SYSRQ=y
|
||||||
CONFIG_UNUSED_SYMBOLS=y
|
CONFIG_UNUSED_SYMBOLS=y
|
||||||
CONFIG_DEBUG_KERNEL=y
|
CONFIG_DEBUG_KERNEL=y
|
||||||
CONFIG_LOCKUP_DETECTOR=y
|
CONFIG_LOCKUP_DETECTOR=y
|
||||||
CONFIG_DETECT_HUNG_TASK=y
|
|
||||||
CONFIG_TIMER_STATS=y
|
CONFIG_TIMER_STATS=y
|
||||||
CONFIG_PROVE_LOCKING=y
|
CONFIG_PROVE_LOCKING=y
|
||||||
CONFIG_DEBUG_SPINLOCK_SLEEP=y
|
|
||||||
CONFIG_DEBUG_INFO=y
|
CONFIG_DEBUG_INFO=y
|
||||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
|
||||||
CONFIG_BLK_DEV_IO_TRACE=y
|
CONFIG_BLK_DEV_IO_TRACE=y
|
||||||
CONFIG_STRICT_DEVMEM=y
|
CONFIG_STRICT_DEVMEM=y
|
||||||
CONFIG_DEBUG_USER=y
|
CONFIG_DEBUG_USER=y
|
||||||
CONFIG_CRYPTO=y
|
|
||||||
CONFIG_CRYPTO_CRC32C=m
|
|
||||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||||
# CONFIG_CRYPTO_HW is not set
|
# CONFIG_CRYPTO_HW is not set
|
||||||
CONFIG_CRC_ITU_T=m
|
CONFIG_CRC_ITU_T=m
|
||||||
|
|
|
||||||
|
|
@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
|
||||||
CONFIG_BSD_DISKLABEL=y
|
CONFIG_BSD_DISKLABEL=y
|
||||||
CONFIG_SOLARIS_X86_PARTITION=y
|
CONFIG_SOLARIS_X86_PARTITION=y
|
||||||
CONFIG_ARCH_SIRF=y
|
CONFIG_ARCH_SIRF=y
|
||||||
|
# CONFIG_SWP_EMULATE is not set
|
||||||
|
CONFIG_SMP=y
|
||||||
|
CONFIG_SCHED_MC=y
|
||||||
CONFIG_PREEMPT=y
|
CONFIG_PREEMPT=y
|
||||||
CONFIG_AEABI=y
|
CONFIG_AEABI=y
|
||||||
CONFIG_KEXEC=y
|
CONFIG_KEXEC=y
|
||||||
|
|
|
||||||
|
|
@ -6,6 +6,23 @@
|
||||||
#define SCU_PM_POWEROFF 3
|
#define SCU_PM_POWEROFF 3
|
||||||
|
|
||||||
#ifndef __ASSEMBLER__
|
#ifndef __ASSEMBLER__
|
||||||
|
|
||||||
|
#include <asm/cputype.h>
|
||||||
|
|
||||||
|
static inline bool scu_a9_has_base(void)
|
||||||
|
{
|
||||||
|
return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline unsigned long scu_a9_get_base(void)
|
||||||
|
{
|
||||||
|
unsigned long pa;
|
||||||
|
|
||||||
|
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
|
||||||
|
|
||||||
|
return pa;
|
||||||
|
}
|
||||||
|
|
||||||
unsigned int scu_get_core_count(void __iomem *);
|
unsigned int scu_get_core_count(void __iomem *);
|
||||||
int scu_power_mode(void __iomem *, unsigned int);
|
int scu_power_mode(void __iomem *, unsigned int);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,88 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DEBUG_IMX_UART_H
|
||||||
|
#define __DEBUG_IMX_UART_H
|
||||||
|
|
||||||
|
#define IMX1_UART1_BASE_ADDR 0x00206000
|
||||||
|
#define IMX1_UART2_BASE_ADDR 0x00207000
|
||||||
|
#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
|
||||||
|
#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX21_UART1_BASE_ADDR 0x1000a000
|
||||||
|
#define IMX21_UART2_BASE_ADDR 0x1000b000
|
||||||
|
#define IMX21_UART3_BASE_ADDR 0x1000c000
|
||||||
|
#define IMX21_UART4_BASE_ADDR 0x1000d000
|
||||||
|
#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
|
||||||
|
#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX25_UART1_BASE_ADDR 0x43f90000
|
||||||
|
#define IMX25_UART2_BASE_ADDR 0x43f94000
|
||||||
|
#define IMX25_UART3_BASE_ADDR 0x5000c000
|
||||||
|
#define IMX25_UART4_BASE_ADDR 0x50008000
|
||||||
|
#define IMX25_UART5_BASE_ADDR 0x5002c000
|
||||||
|
#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
|
||||||
|
#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX31_UART1_BASE_ADDR 0x43f90000
|
||||||
|
#define IMX31_UART2_BASE_ADDR 0x43f94000
|
||||||
|
#define IMX31_UART3_BASE_ADDR 0x5000c000
|
||||||
|
#define IMX31_UART4_BASE_ADDR 0x43fb0000
|
||||||
|
#define IMX31_UART5_BASE_ADDR 0x43fb4000
|
||||||
|
#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
|
||||||
|
#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX35_UART1_BASE_ADDR 0x43f90000
|
||||||
|
#define IMX35_UART2_BASE_ADDR 0x43f94000
|
||||||
|
#define IMX35_UART3_BASE_ADDR 0x5000c000
|
||||||
|
#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
|
||||||
|
#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX51_UART1_BASE_ADDR 0x73fbc000
|
||||||
|
#define IMX51_UART2_BASE_ADDR 0x73fc0000
|
||||||
|
#define IMX51_UART3_BASE_ADDR 0x7000c000
|
||||||
|
#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
|
||||||
|
#define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX53_UART1_BASE_ADDR 0x53fbc000
|
||||||
|
#define IMX53_UART2_BASE_ADDR 0x53fc0000
|
||||||
|
#define IMX53_UART3_BASE_ADDR 0x5000c000
|
||||||
|
#define IMX53_UART4_BASE_ADDR 0x53ff0000
|
||||||
|
#define IMX53_UART5_BASE_ADDR 0x63f90000
|
||||||
|
#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
|
||||||
|
#define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX6Q_UART1_BASE_ADDR 0x02020000
|
||||||
|
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
|
||||||
|
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
|
||||||
|
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
|
||||||
|
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
|
||||||
|
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
|
||||||
|
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
|
||||||
|
|
||||||
|
#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
|
||||||
|
|
||||||
|
#ifdef CONFIG_DEBUG_IMX1_UART
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX25_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX31_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX35_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX51_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX53_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
|
||||||
|
#elif defined(CONFIG_DEBUG_IMX6Q_UART)
|
||||||
|
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __DEBUG_IMX_UART_H */
|
||||||
|
|
@ -10,35 +10,8 @@
|
||||||
* published by the Free Software Foundation.
|
* published by the Free Software Foundation.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
#define IMX6Q_UART1_BASE_ADDR 0x02020000
|
|
||||||
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
|
|
||||||
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
|
|
||||||
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
|
|
||||||
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
|
|
||||||
|
|
||||||
/*
|
#include "imx-uart.h"
|
||||||
* IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
|
|
||||||
* of IMX6Q_UART##n##_BASE_ADDR.
|
|
||||||
*/
|
|
||||||
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
|
|
||||||
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
|
|
||||||
#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
|
|
||||||
|
|
||||||
#ifdef CONFIG_DEBUG_IMX1_UART
|
|
||||||
#define UART_PADDR 0x00206000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX25_UART)
|
|
||||||
#define UART_PADDR 0x43f90000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
|
|
||||||
#define UART_PADDR 0x1000a000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
|
|
||||||
#define UART_PADDR 0x43f90000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX51_UART)
|
|
||||||
#define UART_PADDR 0x73fbc000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX53_UART)
|
|
||||||
#define UART_PADDR 0x53fbc000
|
|
||||||
#elif defined (CONFIG_DEBUG_IMX6Q_UART)
|
|
||||||
#define UART_PADDR IMX6Q_DEBUG_UART_BASE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
|
* FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
|
||||||
|
|
|
||||||
|
|
@ -26,11 +26,13 @@
|
||||||
#include <mach/bcm2835_soc.h>
|
#include <mach/bcm2835_soc.h>
|
||||||
|
|
||||||
#define PM_RSTC 0x1c
|
#define PM_RSTC 0x1c
|
||||||
|
#define PM_RSTS 0x20
|
||||||
#define PM_WDOG 0x24
|
#define PM_WDOG 0x24
|
||||||
|
|
||||||
#define PM_PASSWORD 0x5a000000
|
#define PM_PASSWORD 0x5a000000
|
||||||
#define PM_RSTC_WRCFG_MASK 0x00000030
|
#define PM_RSTC_WRCFG_MASK 0x00000030
|
||||||
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
||||||
|
#define PM_RSTS_HADWRH_SET 0x00000040
|
||||||
|
|
||||||
static void __iomem *wdt_regs;
|
static void __iomem *wdt_regs;
|
||||||
|
|
||||||
|
|
@ -67,6 +69,29 @@ static void bcm2835_restart(char mode, const char *cmd)
|
||||||
mdelay(1);
|
mdelay(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We can't really power off, but if we do the normal reset scheme, and
|
||||||
|
* indicate to bootcode.bin not to reboot, then most of the chip will be
|
||||||
|
* powered off.
|
||||||
|
*/
|
||||||
|
static void bcm2835_power_off(void)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We set the watchdog hard reset bit here to distinguish this reset
|
||||||
|
* from the normal (full) reset. bootcode.bin will not reboot after a
|
||||||
|
* hard reset.
|
||||||
|
*/
|
||||||
|
val = readl_relaxed(wdt_regs + PM_RSTS);
|
||||||
|
val &= ~PM_RSTC_WRCFG_MASK;
|
||||||
|
val |= PM_PASSWORD | PM_RSTS_HADWRH_SET;
|
||||||
|
writel_relaxed(val, wdt_regs + PM_RSTS);
|
||||||
|
|
||||||
|
/* Continue with normal reset mechanism */
|
||||||
|
bcm2835_restart(0, "");
|
||||||
|
}
|
||||||
|
|
||||||
static struct map_desc io_map __initdata = {
|
static struct map_desc io_map __initdata = {
|
||||||
.virtual = BCM2835_PERIPH_VIRT,
|
.virtual = BCM2835_PERIPH_VIRT,
|
||||||
.pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
|
.pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
|
||||||
|
|
@ -84,6 +109,9 @@ static void __init bcm2835_init(void)
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
bcm2835_setup_restart();
|
bcm2835_setup_restart();
|
||||||
|
if (wdt_regs)
|
||||||
|
pm_power_off = bcm2835_power_off;
|
||||||
|
|
||||||
bcm2835_init_clocks();
|
bcm2835_init_clocks();
|
||||||
|
|
||||||
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
||||||
|
|
|
||||||
|
|
@ -652,8 +652,13 @@ static __init void da830_evm_init(void)
|
||||||
if (ret)
|
if (ret)
|
||||||
pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
|
pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
|
||||||
|
|
||||||
ret = da8xx_register_spi(0, da830evm_spi_info,
|
ret = spi_register_board_info(da830evm_spi_info,
|
||||||
ARRAY_SIZE(da830evm_spi_info));
|
ARRAY_SIZE(da830evm_spi_info));
|
||||||
|
if (ret)
|
||||||
|
pr_warn("%s: spi info registration failed: %d\n", __func__,
|
||||||
|
ret);
|
||||||
|
|
||||||
|
ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
|
||||||
if (ret)
|
if (ret)
|
||||||
pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
|
pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
|
||||||
ret);
|
ret);
|
||||||
|
|
|
||||||
|
|
@ -1565,8 +1565,13 @@ static __init void da850_evm_init(void)
|
||||||
|
|
||||||
da850_vpif_init();
|
da850_vpif_init();
|
||||||
|
|
||||||
ret = da8xx_register_spi(1, da850evm_spi_info,
|
ret = spi_register_board_info(da850evm_spi_info,
|
||||||
ARRAY_SIZE(da850evm_spi_info));
|
ARRAY_SIZE(da850evm_spi_info));
|
||||||
|
if (ret)
|
||||||
|
pr_warn("%s: spi info registration failed: %d\n", __func__,
|
||||||
|
ret);
|
||||||
|
|
||||||
|
ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
|
||||||
if (ret)
|
if (ret)
|
||||||
pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
|
pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
|
||||||
ret);
|
ret);
|
||||||
|
|
|
||||||
|
|
@ -529,8 +529,13 @@ static void __init mityomapl138_init(void)
|
||||||
|
|
||||||
mityomapl138_setup_nand();
|
mityomapl138_setup_nand();
|
||||||
|
|
||||||
ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
|
ret = spi_register_board_info(mityomapl138_spi_flash_info,
|
||||||
ARRAY_SIZE(mityomapl138_spi_flash_info));
|
ARRAY_SIZE(mityomapl138_spi_flash_info));
|
||||||
|
if (ret)
|
||||||
|
pr_warn("spi info registration failed: %d\n", ret);
|
||||||
|
|
||||||
|
ret = da8xx_register_spi_bus(1,
|
||||||
|
ARRAY_SIZE(mityomapl138_spi_flash_info));
|
||||||
if (ret)
|
if (ret)
|
||||||
pr_warning("spi 1 registration failed: %d\n", ret);
|
pr_warning("spi 1 registration failed: %d\n", ret);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -52,6 +52,40 @@ static void __clk_disable(struct clk *clk)
|
||||||
__clk_disable(clk->parent);
|
__clk_disable(clk->parent);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int davinci_clk_reset(struct clk *clk, bool reset)
|
||||||
|
{
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
if (clk == NULL || IS_ERR(clk))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&clockfw_lock, flags);
|
||||||
|
if (clk->flags & CLK_PSC)
|
||||||
|
davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
|
||||||
|
spin_unlock_irqrestore(&clockfw_lock, flags);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(davinci_clk_reset);
|
||||||
|
|
||||||
|
int davinci_clk_reset_assert(struct clk *clk)
|
||||||
|
{
|
||||||
|
if (clk == NULL || IS_ERR(clk) || !clk->reset)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return clk->reset(clk, true);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(davinci_clk_reset_assert);
|
||||||
|
|
||||||
|
int davinci_clk_reset_deassert(struct clk *clk)
|
||||||
|
{
|
||||||
|
if (clk == NULL || IS_ERR(clk) || !clk->reset)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return clk->reset(clk, false);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(davinci_clk_reset_deassert);
|
||||||
|
|
||||||
int clk_enable(struct clk *clk)
|
int clk_enable(struct clk *clk)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
@ -535,7 +569,7 @@ int davinci_set_refclk_rate(unsigned long rate)
|
||||||
}
|
}
|
||||||
|
|
||||||
int __init davinci_clk_init(struct clk_lookup *clocks)
|
int __init davinci_clk_init(struct clk_lookup *clocks)
|
||||||
{
|
{
|
||||||
struct clk_lookup *c;
|
struct clk_lookup *c;
|
||||||
struct clk *clk;
|
struct clk *clk;
|
||||||
size_t num_clocks = 0;
|
size_t num_clocks = 0;
|
||||||
|
|
@ -576,6 +610,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
|
||||||
if (clk->lpsc)
|
if (clk->lpsc)
|
||||||
clk->flags |= CLK_PSC;
|
clk->flags |= CLK_PSC;
|
||||||
|
|
||||||
|
if (clk->flags & PSC_LRST)
|
||||||
|
clk->reset = davinci_clk_reset;
|
||||||
|
|
||||||
clk_register(clk);
|
clk_register(clk);
|
||||||
num_clocks++;
|
num_clocks++;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -103,6 +103,7 @@ struct clk {
|
||||||
unsigned long (*recalc) (struct clk *);
|
unsigned long (*recalc) (struct clk *);
|
||||||
int (*set_rate) (struct clk *clk, unsigned long rate);
|
int (*set_rate) (struct clk *clk, unsigned long rate);
|
||||||
int (*round_rate) (struct clk *clk, unsigned long rate);
|
int (*round_rate) (struct clk *clk, unsigned long rate);
|
||||||
|
int (*reset) (struct clk *clk, bool reset);
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Clock flags: SoC-specific flags start at BIT(16) */
|
/* Clock flags: SoC-specific flags start at BIT(16) */
|
||||||
|
|
@ -112,6 +113,7 @@ struct clk {
|
||||||
#define PRE_PLL BIT(4) /* source is before PLL mult/div */
|
#define PRE_PLL BIT(4) /* source is before PLL mult/div */
|
||||||
#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
|
#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
|
||||||
#define PSC_FORCE BIT(6) /* Force module state transtition */
|
#define PSC_FORCE BIT(6) /* Force module state transtition */
|
||||||
|
#define PSC_LRST BIT(8) /* Use local reset on enable/disable */
|
||||||
|
|
||||||
#define CLK(dev, con, ck) \
|
#define CLK(dev, con, ck) \
|
||||||
{ \
|
{ \
|
||||||
|
|
@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
||||||
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
|
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
|
||||||
int davinci_set_refclk_rate(unsigned long rate);
|
int davinci_set_refclk_rate(unsigned long rate);
|
||||||
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
|
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
|
||||||
|
int davinci_clk_reset(struct clk *clk, bool reset);
|
||||||
|
|
||||||
extern struct platform_device davinci_wdt_device;
|
extern struct platform_device davinci_wdt_device;
|
||||||
extern void davinci_watchdog_reset(struct platform_device *);
|
extern void davinci_watchdog_reset(struct platform_device *);
|
||||||
|
|
|
||||||
|
|
@ -76,6 +76,13 @@ static struct clk pll0_aux_clk = {
|
||||||
.flags = CLK_PLL | PRE_PLL,
|
.flags = CLK_PLL | PRE_PLL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk pll0_sysclk1 = {
|
||||||
|
.name = "pll0_sysclk1",
|
||||||
|
.parent = &pll0_clk,
|
||||||
|
.flags = CLK_PLL,
|
||||||
|
.div_reg = PLLDIV1,
|
||||||
|
};
|
||||||
|
|
||||||
static struct clk pll0_sysclk2 = {
|
static struct clk pll0_sysclk2 = {
|
||||||
.name = "pll0_sysclk2",
|
.name = "pll0_sysclk2",
|
||||||
.parent = &pll0_clk,
|
.parent = &pll0_clk,
|
||||||
|
|
@ -368,10 +375,19 @@ static struct clk sata_clk = {
|
||||||
.flags = PSC_FORCE,
|
.flags = PSC_FORCE,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk dsp_clk = {
|
||||||
|
.name = "dsp",
|
||||||
|
.parent = &pll0_sysclk1,
|
||||||
|
.domain = DAVINCI_GPSC_DSPDOMAIN,
|
||||||
|
.lpsc = DA8XX_LPSC0_GEM,
|
||||||
|
.flags = PSC_LRST | PSC_FORCE,
|
||||||
|
};
|
||||||
|
|
||||||
static struct clk_lookup da850_clks[] = {
|
static struct clk_lookup da850_clks[] = {
|
||||||
CLK(NULL, "ref", &ref_clk),
|
CLK(NULL, "ref", &ref_clk),
|
||||||
CLK(NULL, "pll0", &pll0_clk),
|
CLK(NULL, "pll0", &pll0_clk),
|
||||||
CLK(NULL, "pll0_aux", &pll0_aux_clk),
|
CLK(NULL, "pll0_aux", &pll0_aux_clk),
|
||||||
|
CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
|
||||||
CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
|
CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
|
||||||
CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
|
CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
|
||||||
CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
|
CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
|
||||||
|
|
@ -413,6 +429,7 @@ static struct clk_lookup da850_clks[] = {
|
||||||
CLK("spi_davinci.1", NULL, &spi1_clk),
|
CLK("spi_davinci.1", NULL, &spi1_clk),
|
||||||
CLK("vpif", NULL, &vpif_clk),
|
CLK("vpif", NULL, &vpif_clk),
|
||||||
CLK("ahci", NULL, &sata_clk),
|
CLK("ahci", NULL, &sata_clk),
|
||||||
|
CLK("davinci-rproc.0", NULL, &dsp_clk),
|
||||||
CLK(NULL, NULL, NULL),
|
CLK(NULL, NULL, NULL),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -751,7 +751,7 @@ void __iomem * __init da8xx_get_mem_ctlr(void)
|
||||||
|
|
||||||
da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
|
da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
|
||||||
if (!da8xx_ddr2_ctlr_base)
|
if (!da8xx_ddr2_ctlr_base)
|
||||||
pr_warning("%s: Unable to map DDR2 controller", __func__);
|
pr_warn("%s: Unable to map DDR2 controller", __func__);
|
||||||
|
|
||||||
return da8xx_ddr2_ctlr_base;
|
return da8xx_ddr2_ctlr_base;
|
||||||
}
|
}
|
||||||
|
|
@ -832,7 +832,7 @@ static struct resource da8xx_spi1_resources[] = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
struct davinci_spi_platform_data da8xx_spi_pdata[] = {
|
static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.version = SPI_VERSION_2,
|
.version = SPI_VERSION_2,
|
||||||
.intr_line = 1,
|
.intr_line = 1,
|
||||||
|
|
@ -866,20 +866,12 @@ static struct platform_device da8xx_spi_device[] = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
|
int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
|
||||||
unsigned len)
|
|
||||||
{
|
{
|
||||||
int ret;
|
|
||||||
|
|
||||||
if (instance < 0 || instance > 1)
|
if (instance < 0 || instance > 1)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
ret = spi_register_board_info(info, len);
|
da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
|
||||||
if (ret)
|
|
||||||
pr_warning("%s: failed to register board info for spi %d :"
|
|
||||||
" %d\n", __func__, instance, ret);
|
|
||||||
|
|
||||||
da8xx_spi_pdata[instance].num_chipselect = len;
|
|
||||||
|
|
||||||
if (instance == 1 && cpu_is_davinci_da850()) {
|
if (instance == 1 && cpu_is_davinci_da850()) {
|
||||||
da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
|
da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
|
||||||
|
|
|
||||||
|
|
@ -18,4 +18,7 @@ struct clk;
|
||||||
extern int clk_register(struct clk *clk);
|
extern int clk_register(struct clk *clk);
|
||||||
extern void clk_unregister(struct clk *clk);
|
extern void clk_unregister(struct clk *clk);
|
||||||
|
|
||||||
|
int davinci_clk_reset_assert(struct clk *c);
|
||||||
|
int davinci_clk_reset_deassert(struct clk *c);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -82,8 +82,7 @@ void __init da850_init(void);
|
||||||
int da830_register_edma(struct edma_rsv_info *rsv);
|
int da830_register_edma(struct edma_rsv_info *rsv);
|
||||||
int da850_register_edma(struct edma_rsv_info *rsv[2]);
|
int da850_register_edma(struct edma_rsv_info *rsv[2]);
|
||||||
int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
|
int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
|
||||||
int da8xx_register_spi(int instance,
|
int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
|
||||||
const struct spi_board_info *info, unsigned len);
|
|
||||||
int da8xx_register_watchdog(void);
|
int da8xx_register_watchdog(void);
|
||||||
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
|
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
|
||||||
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
|
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
|
||||||
|
|
@ -110,7 +109,6 @@ extern struct platform_device da8xx_serial_device;
|
||||||
extern struct emac_platform_data da8xx_emac_pdata;
|
extern struct emac_platform_data da8xx_emac_pdata;
|
||||||
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
|
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
|
||||||
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
|
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
|
||||||
extern struct davinci_spi_platform_data da8xx_spi_pdata[];
|
|
||||||
|
|
||||||
extern struct platform_device da8xx_wdt_device;
|
extern struct platform_device da8xx_wdt_device;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -246,6 +246,7 @@
|
||||||
|
|
||||||
#define MDSTAT_STATE_MASK 0x3f
|
#define MDSTAT_STATE_MASK 0x3f
|
||||||
#define PDSTAT_STATE_MASK 0x1f
|
#define PDSTAT_STATE_MASK 0x1f
|
||||||
|
#define MDCTL_LRST BIT(8)
|
||||||
#define MDCTL_FORCE BIT(31)
|
#define MDCTL_FORCE BIT(31)
|
||||||
#define PDCTL_NEXT BIT(0)
|
#define PDCTL_NEXT BIT(0)
|
||||||
#define PDCTL_EPCGOOD BIT(8)
|
#define PDCTL_EPCGOOD BIT(8)
|
||||||
|
|
@ -253,6 +254,8 @@
|
||||||
#ifndef __ASSEMBLER__
|
#ifndef __ASSEMBLER__
|
||||||
|
|
||||||
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
|
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
|
||||||
|
extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
|
||||||
|
bool reset);
|
||||||
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
||||||
unsigned int id, bool enable, u32 flags);
|
unsigned int id, bool enable, u32 flags);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -35,7 +35,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
|
||||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||||
|
|
||||||
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
||||||
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
|
pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
|
||||||
(int)soc_info->psc_bases, ctlr);
|
(int)soc_info->psc_bases, ctlr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -48,6 +48,31 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
|
||||||
return mdstat & BIT(12);
|
return mdstat & BIT(12);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Control "reset" line associated with PSC domain */
|
||||||
|
void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset)
|
||||||
|
{
|
||||||
|
u32 mdctl;
|
||||||
|
void __iomem *psc_base;
|
||||||
|
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||||
|
|
||||||
|
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
||||||
|
pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
|
||||||
|
(int)soc_info->psc_bases, ctlr);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
|
||||||
|
|
||||||
|
mdctl = readl(psc_base + MDCTL + 4 * id);
|
||||||
|
if (reset)
|
||||||
|
mdctl &= ~MDCTL_LRST;
|
||||||
|
else
|
||||||
|
mdctl |= MDCTL_LRST;
|
||||||
|
writel(mdctl, psc_base + MDCTL + 4 * id);
|
||||||
|
|
||||||
|
iounmap(psc_base);
|
||||||
|
}
|
||||||
|
|
||||||
/* Enable or disable a PSC domain */
|
/* Enable or disable a PSC domain */
|
||||||
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
||||||
unsigned int id, bool enable, u32 flags)
|
unsigned int id, bool enable, u32 flags)
|
||||||
|
|
@ -58,7 +83,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
||||||
u32 next_state = PSC_STATE_ENABLE;
|
u32 next_state = PSC_STATE_ENABLE;
|
||||||
|
|
||||||
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
||||||
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
|
pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
|
||||||
(int)soc_info->psc_bases, ctlr);
|
(int)soc_info->psc_bases, ctlr);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -28,7 +28,11 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o
|
||||||
obj-$(CONFIG_MXC_USE_EPIT) += epit.o
|
obj-$(CONFIG_MXC_USE_EPIT) += epit.o
|
||||||
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
|
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
|
||||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
|
obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
|
||||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
|
||||||
|
ifeq ($(CONFIG_CPU_IDLE),y)
|
||||||
|
obj-y += cpuidle.o
|
||||||
|
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
|
||||||
|
endif
|
||||||
|
|
||||||
ifdef CONFIG_SND_IMX_SOC
|
ifdef CONFIG_SND_IMX_SOC
|
||||||
obj-y += ssi-fiq.o
|
obj-y += ssi-fiq.o
|
||||||
|
|
|
||||||
|
|
@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = {
|
||||||
"32k", "usb_div", "dptc",
|
"32k", "usb_div", "dptc",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *ssi_sel_clks[] = { "spll", "mpll", };
|
static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
|
||||||
|
|
||||||
enum mx27_clks {
|
enum mx27_clks {
|
||||||
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
|
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
|
||||||
|
|
@ -82,7 +82,7 @@ enum mx27_clks {
|
||||||
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
|
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
|
||||||
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
|
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
|
||||||
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
|
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
|
||||||
mpll_sel, clk_max
|
mpll_sel, spll_gate, clk_max
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk *clk[clk_max];
|
static struct clk *clk[clk_max];
|
||||||
|
|
@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref)
|
||||||
ARRAY_SIZE(mpll_sel_clks));
|
ARRAY_SIZE(mpll_sel_clks));
|
||||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||||
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
|
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
|
||||||
|
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||||
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
||||||
|
|
||||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
||||||
|
|
@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref)
|
||||||
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
||||||
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
||||||
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
||||||
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
|
clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
|
||||||
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||||
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
||||||
|
|
|
||||||
|
|
@ -34,8 +34,8 @@ static const char *csi_sel[] = { "upll", "spll", };
|
||||||
static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
|
static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
|
||||||
|
|
||||||
enum mx31_clks {
|
enum mx31_clks {
|
||||||
ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
|
dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
|
||||||
per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
|
per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
|
||||||
fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
|
fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
|
||||||
iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
|
iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
|
||||||
uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
|
uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
|
||||||
|
|
@ -46,12 +46,15 @@ enum mx31_clks {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk *clk[clk_max];
|
static struct clk *clk[clk_max];
|
||||||
|
static struct clk_onecell_data clk_data;
|
||||||
|
|
||||||
int __init mx31_clocks_init(unsigned long fref)
|
int __init mx31_clocks_init(unsigned long fref)
|
||||||
{
|
{
|
||||||
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
|
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
|
||||||
int i;
|
int i;
|
||||||
|
struct device_node *np;
|
||||||
|
|
||||||
|
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||||
clk[ckih] = imx_clk_fixed("ckih", fref);
|
clk[ckih] = imx_clk_fixed("ckih", fref);
|
||||||
clk[ckil] = imx_clk_fixed("ckil", 32768);
|
clk[ckil] = imx_clk_fixed("ckil", 32768);
|
||||||
clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
|
clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
|
||||||
|
|
@ -116,6 +119,14 @@ int __init mx31_clocks_init(unsigned long fref)
|
||||||
pr_err("imx31 clk %d: register failed with %ld\n",
|
pr_err("imx31 clk %d: register failed with %ld\n",
|
||||||
i, PTR_ERR(clk[i]));
|
i, PTR_ERR(clk[i]));
|
||||||
|
|
||||||
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
|
||||||
|
|
||||||
|
if (np) {
|
||||||
|
clk_data.clks = clk;
|
||||||
|
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||||
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||||
|
}
|
||||||
|
|
||||||
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
|
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
|
||||||
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
||||||
clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
|
clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
|
||||||
|
|
|
||||||
|
|
@ -67,13 +67,13 @@ enum mx35_clks {
|
||||||
|
|
||||||
static struct clk *clk[clk_max];
|
static struct clk *clk[clk_max];
|
||||||
|
|
||||||
int __init mx35_clocks_init()
|
int __init mx35_clocks_init(void)
|
||||||
{
|
{
|
||||||
void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
|
void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
|
||||||
u32 pdr0, consumer_sel, hsp_sel;
|
u32 pdr0, consumer_sel, hsp_sel;
|
||||||
struct arm_ahb_div *aad;
|
struct arm_ahb_div *aad;
|
||||||
unsigned char *hsp_div;
|
unsigned char *hsp_div;
|
||||||
int i;
|
u32 i;
|
||||||
|
|
||||||
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
|
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
|
||||||
consumer_sel = (pdr0 >> 16) & 0xf;
|
consumer_sel = (pdr0 >> 16) & 0xf;
|
||||||
|
|
|
||||||
|
|
@ -54,8 +54,19 @@
|
||||||
#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
|
#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
|
||||||
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
|
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
|
||||||
|
|
||||||
|
#define CGPR 0x64
|
||||||
|
#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
|
||||||
|
|
||||||
static void __iomem *ccm_base;
|
static void __iomem *ccm_base;
|
||||||
|
|
||||||
|
void imx6q_set_chicken_bit(void)
|
||||||
|
{
|
||||||
|
u32 val = readl_relaxed(ccm_base + CGPR);
|
||||||
|
|
||||||
|
val |= BM_CGPR_CHICKEN_BIT;
|
||||||
|
writel_relaxed(val, ccm_base + CGPR);
|
||||||
|
}
|
||||||
|
|
||||||
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||||
{
|
{
|
||||||
u32 val = readl_relaxed(ccm_base + CLPCR);
|
u32 val = readl_relaxed(ccm_base + CLPCR);
|
||||||
|
|
@ -66,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||||
break;
|
break;
|
||||||
case WAIT_UNCLOCKED:
|
case WAIT_UNCLOCKED:
|
||||||
val |= 0x1 << BP_CLPCR_LPM;
|
val |= 0x1 << BP_CLPCR_LPM;
|
||||||
|
val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
|
||||||
break;
|
break;
|
||||||
case STOP_POWER_ON:
|
case STOP_POWER_ON:
|
||||||
val |= 0x2 << BP_CLPCR_LPM;
|
val |= 0x2 << BP_CLPCR_LPM;
|
||||||
|
|
|
||||||
|
|
@ -116,9 +116,11 @@ extern u32 *pl310_get_save_ptr(void);
|
||||||
extern void v7_secondary_startup(void);
|
extern void v7_secondary_startup(void);
|
||||||
extern void imx_scu_map_io(void);
|
extern void imx_scu_map_io(void);
|
||||||
extern void imx_smp_prepare(void);
|
extern void imx_smp_prepare(void);
|
||||||
|
extern void imx_scu_standby_enable(void);
|
||||||
#else
|
#else
|
||||||
static inline void imx_scu_map_io(void) {}
|
static inline void imx_scu_map_io(void) {}
|
||||||
static inline void imx_smp_prepare(void) {}
|
static inline void imx_smp_prepare(void) {}
|
||||||
|
static inline void imx_scu_standby_enable(void) {}
|
||||||
#endif
|
#endif
|
||||||
extern void imx_enable_cpu(int cpu, bool enable);
|
extern void imx_enable_cpu(int cpu, bool enable);
|
||||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||||
|
|
@ -128,6 +130,7 @@ extern void imx_gpc_init(void);
|
||||||
extern void imx_gpc_pre_suspend(void);
|
extern void imx_gpc_pre_suspend(void);
|
||||||
extern void imx_gpc_post_resume(void);
|
extern void imx_gpc_post_resume(void);
|
||||||
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
||||||
|
extern void imx6q_set_chicken_bit(void);
|
||||||
|
|
||||||
extern void imx_cpu_die(unsigned int cpu);
|
extern void imx_cpu_die(unsigned int cpu);
|
||||||
extern int imx_cpu_kill(unsigned int cpu);
|
extern int imx_cpu_kill(unsigned int cpu);
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,95 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/clockchips.h>
|
||||||
|
#include <linux/cpuidle.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <asm/cpuidle.h>
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
|
|
||||||
|
#include "common.h"
|
||||||
|
#include "cpuidle.h"
|
||||||
|
|
||||||
|
static atomic_t master = ATOMIC_INIT(0);
|
||||||
|
static DEFINE_SPINLOCK(master_lock);
|
||||||
|
|
||||||
|
static int imx6q_enter_wait(struct cpuidle_device *dev,
|
||||||
|
struct cpuidle_driver *drv, int index)
|
||||||
|
{
|
||||||
|
int cpu = dev->cpu;
|
||||||
|
|
||||||
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
|
||||||
|
|
||||||
|
if (atomic_inc_return(&master) == num_online_cpus()) {
|
||||||
|
/*
|
||||||
|
* With this lock, we prevent other cpu to exit and enter
|
||||||
|
* this function again and become the master.
|
||||||
|
*/
|
||||||
|
if (!spin_trylock(&master_lock))
|
||||||
|
goto idle;
|
||||||
|
imx6q_set_lpm(WAIT_UNCLOCKED);
|
||||||
|
cpu_do_idle();
|
||||||
|
imx6q_set_lpm(WAIT_CLOCKED);
|
||||||
|
spin_unlock(&master_lock);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
|
||||||
|
idle:
|
||||||
|
cpu_do_idle();
|
||||||
|
done:
|
||||||
|
atomic_dec(&master);
|
||||||
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
|
||||||
|
|
||||||
|
return index;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For each cpu, setup the broadcast timer because local timer
|
||||||
|
* stops for the states other than WFI.
|
||||||
|
*/
|
||||||
|
static void imx6q_setup_broadcast_timer(void *arg)
|
||||||
|
{
|
||||||
|
int cpu = smp_processor_id();
|
||||||
|
|
||||||
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct cpuidle_driver imx6q_cpuidle_driver = {
|
||||||
|
.name = "imx6q_cpuidle",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.en_core_tk_irqen = 1,
|
||||||
|
.states = {
|
||||||
|
/* WFI */
|
||||||
|
ARM_CPUIDLE_WFI_STATE,
|
||||||
|
/* WAIT */
|
||||||
|
{
|
||||||
|
.exit_latency = 50,
|
||||||
|
.target_residency = 75,
|
||||||
|
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||||
|
.enter = imx6q_enter_wait,
|
||||||
|
.name = "WAIT",
|
||||||
|
.desc = "Clock off",
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.state_count = 2,
|
||||||
|
.safe_state_index = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
int __init imx6q_cpuidle_init(void)
|
||||||
|
{
|
||||||
|
/* Need to enable SCU standby for entering WAIT modes */
|
||||||
|
imx_scu_standby_enable();
|
||||||
|
|
||||||
|
/* Set chicken bit to get a reliable WAIT mode support */
|
||||||
|
imx6q_set_chicken_bit();
|
||||||
|
|
||||||
|
/* Configure the broadcast timer on each cpu */
|
||||||
|
on_each_cpu(imx6q_setup_broadcast_timer, NULL, 1);
|
||||||
|
|
||||||
|
return imx_cpuidle_init(&imx6q_cpuidle_driver);
|
||||||
|
}
|
||||||
|
|
@ -14,9 +14,14 @@
|
||||||
|
|
||||||
#ifdef CONFIG_CPU_IDLE
|
#ifdef CONFIG_CPU_IDLE
|
||||||
extern int imx_cpuidle_init(struct cpuidle_driver *drv);
|
extern int imx_cpuidle_init(struct cpuidle_driver *drv);
|
||||||
|
extern int imx6q_cpuidle_init(void);
|
||||||
#else
|
#else
|
||||||
static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
|
static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
|
||||||
{
|
{
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
static inline int imx6q_cpuidle_init(void)
|
||||||
|
{
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d)
|
||||||
void __init imx_gpc_init(void)
|
void __init imx_gpc_init(void)
|
||||||
{
|
{
|
||||||
struct device_node *np;
|
struct device_node *np;
|
||||||
|
int i;
|
||||||
|
|
||||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
||||||
gpc_base = of_iomap(np, 0);
|
gpc_base = of_iomap(np, 0);
|
||||||
WARN_ON(!gpc_base);
|
WARN_ON(!gpc_base);
|
||||||
|
|
||||||
|
/* Initially mask all interrupts */
|
||||||
|
for (i = 0; i < IMR_NUM; i++)
|
||||||
|
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
|
||||||
|
|
||||||
/* Register GPC as the secondary interrupt controller behind GIC */
|
/* Register GPC as the secondary interrupt controller behind GIC */
|
||||||
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
|
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
|
||||||
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
|
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
|
||||||
|
|
|
||||||
|
|
@ -17,53 +17,6 @@
|
||||||
|
|
||||||
.section ".text.head", "ax"
|
.section ".text.head", "ax"
|
||||||
|
|
||||||
/*
|
|
||||||
* The secondary kernel init calls v7_flush_dcache_all before it enables
|
|
||||||
* the L1; however, the L1 comes out of reset in an undefined state, so
|
|
||||||
* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
|
|
||||||
* of cache lines with uninitialized data and uninitialized tags to get
|
|
||||||
* written out to memory, which does really unpleasant things to the main
|
|
||||||
* processor. We fix this by performing an invalidate, rather than a
|
|
||||||
* clean + invalidate, before jumping into the kernel.
|
|
||||||
*
|
|
||||||
* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
|
|
||||||
* to be called for both secondary cores startup and primary core resume
|
|
||||||
* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
|
|
||||||
*/
|
|
||||||
ENTRY(v7_invalidate_l1)
|
|
||||||
mov r0, #0
|
|
||||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
|
||||||
mcr p15, 2, r0, c0, c0, 0
|
|
||||||
mrc p15, 1, r0, c0, c0, 0
|
|
||||||
|
|
||||||
ldr r1, =0x7fff
|
|
||||||
and r2, r1, r0, lsr #13
|
|
||||||
|
|
||||||
ldr r1, =0x3ff
|
|
||||||
|
|
||||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
|
||||||
add r2, r2, #1 @ NumSets
|
|
||||||
|
|
||||||
and r0, r0, #0x7
|
|
||||||
add r0, r0, #4 @ SetShift
|
|
||||||
|
|
||||||
clz r1, r3 @ WayShift
|
|
||||||
add r4, r3, #1 @ NumWays
|
|
||||||
1: sub r2, r2, #1 @ NumSets--
|
|
||||||
mov r3, r4 @ Temp = NumWays
|
|
||||||
2: subs r3, r3, #1 @ Temp--
|
|
||||||
mov r5, r3, lsl r1
|
|
||||||
mov r6, r2, lsl r0
|
|
||||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
|
||||||
mcr p15, 0, r5, c7, c6, 2
|
|
||||||
bgt 2b
|
|
||||||
cmp r2, #0
|
|
||||||
bgt 1b
|
|
||||||
dsb
|
|
||||||
isb
|
|
||||||
mov pc, lr
|
|
||||||
ENDPROC(v7_invalidate_l1)
|
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
ENTRY(v7_secondary_startup)
|
ENTRY(v7_secondary_startup)
|
||||||
bl v7_invalidate_l1
|
bl v7_invalidate_l1
|
||||||
|
|
|
||||||
|
|
@ -18,24 +18,9 @@
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "mx31.h"
|
#include "mx31.h"
|
||||||
|
|
||||||
static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
|
|
||||||
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
|
|
||||||
"imx21-uart.0", NULL),
|
|
||||||
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
|
|
||||||
"imx21-uart.1", NULL),
|
|
||||||
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
|
|
||||||
"imx21-uart.2", NULL),
|
|
||||||
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
|
|
||||||
"imx21-uart.3", NULL),
|
|
||||||
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
|
|
||||||
"imx21-uart.4", NULL),
|
|
||||||
{ /* sentinel */ }
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init imx31_dt_init(void)
|
static void __init imx31_dt_init(void)
|
||||||
{
|
{
|
||||||
of_platform_populate(NULL, of_default_bus_match_table,
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||||
imx31_auxdata_lookup, NULL);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const char *imx31_dt_board_compat[] __initdata = {
|
static const char *imx31_dt_board_compat[] __initdata = {
|
||||||
|
|
|
||||||
|
|
@ -12,7 +12,6 @@
|
||||||
|
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/clkdev.h>
|
#include <linux/clkdev.h>
|
||||||
#include <linux/cpuidle.h>
|
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
#include <linux/export.h>
|
#include <linux/export.h>
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
|
|
@ -27,7 +26,6 @@
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/micrel_phy.h>
|
#include <linux/micrel_phy.h>
|
||||||
#include <linux/mfd/syscon.h>
|
#include <linux/mfd/syscon.h>
|
||||||
#include <asm/cpuidle.h>
|
|
||||||
#include <asm/smp_twd.h>
|
#include <asm/smp_twd.h>
|
||||||
#include <asm/hardware/cache-l2x0.h>
|
#include <asm/hardware/cache-l2x0.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
|
|
@ -202,17 +200,14 @@ static void __init imx6q_init_machine(void)
|
||||||
imx6q_1588_init();
|
imx6q_1588_init();
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct cpuidle_driver imx6q_cpuidle_driver = {
|
|
||||||
.name = "imx6q_cpuidle",
|
|
||||||
.owner = THIS_MODULE,
|
|
||||||
.en_core_tk_irqen = 1,
|
|
||||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
|
||||||
.state_count = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init imx6q_init_late(void)
|
static void __init imx6q_init_late(void)
|
||||||
{
|
{
|
||||||
imx_cpuidle_init(&imx6q_cpuidle_driver);
|
/*
|
||||||
|
* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
|
||||||
|
* to run cpuidle on them.
|
||||||
|
*/
|
||||||
|
if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
|
||||||
|
imx6q_cpuidle_init();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init imx6q_map_io(void)
|
static void __init imx6q_map_io(void)
|
||||||
|
|
|
||||||
|
|
@ -20,6 +20,8 @@
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "hardware.h"
|
#include "hardware.h"
|
||||||
|
|
||||||
|
#define SCU_STANDBY_ENABLE (1 << 5)
|
||||||
|
|
||||||
static void __iomem *scu_base;
|
static void __iomem *scu_base;
|
||||||
|
|
||||||
static struct map_desc scu_io_desc __initdata = {
|
static struct map_desc scu_io_desc __initdata = {
|
||||||
|
|
@ -42,6 +44,14 @@ void __init imx_scu_map_io(void)
|
||||||
scu_base = IMX_IO_ADDRESS(base);
|
scu_base = IMX_IO_ADDRESS(base);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void imx_scu_standby_enable(void)
|
||||||
|
{
|
||||||
|
u32 val = readl_relaxed(scu_base);
|
||||||
|
|
||||||
|
val |= SCU_STANDBY_ENABLE;
|
||||||
|
writel_relaxed(val, scu_base);
|
||||||
|
}
|
||||||
|
|
||||||
static void __cpuinit imx_secondary_init(unsigned int cpu)
|
static void __cpuinit imx_secondary_init(unsigned int cpu)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -152,7 +152,8 @@ static int v2_set_next_event(unsigned long evt,
|
||||||
|
|
||||||
__raw_writel(tcmp, timer_base + V2_TCMP);
|
__raw_writel(tcmp, timer_base + V2_TCMP);
|
||||||
|
|
||||||
return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
|
return evt < 0x7fffffff &&
|
||||||
|
(int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
|
||||||
-ETIME : 0;
|
-ETIME : 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -19,7 +19,6 @@ obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
|
||||||
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
|
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
|
||||||
obj-$(CONFIG_MACH_T5325) += t5325-setup.o
|
obj-$(CONFIG_MACH_T5325) += t5325-setup.o
|
||||||
|
|
||||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
|
||||||
obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
|
obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
|
||||||
obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
|
obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
|
||||||
obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
|
obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
|
||||||
|
|
|
||||||
|
|
@ -98,6 +98,8 @@ static void __init kirkwood_dt_init(void)
|
||||||
/* Setup root of clk tree */
|
/* Setup root of clk tree */
|
||||||
kirkwood_of_clk_init();
|
kirkwood_of_clk_init();
|
||||||
|
|
||||||
|
kirkwood_cpuidle_init();
|
||||||
|
|
||||||
#ifdef CONFIG_KEXEC
|
#ifdef CONFIG_KEXEC
|
||||||
kexec_reinit = kirkwood_enable_pcie;
|
kexec_reinit = kirkwood_enable_pcie;
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -499,6 +499,28 @@ void __init kirkwood_wdt_init(void)
|
||||||
orion_wdt_init();
|
orion_wdt_init();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* CPU idle
|
||||||
|
****************************************************************************/
|
||||||
|
static struct resource kirkwood_cpuidle_resource[] = {
|
||||||
|
{
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
.start = DDR_OPERATION_BASE,
|
||||||
|
.end = DDR_OPERATION_BASE + 3,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device kirkwood_cpuidle = {
|
||||||
|
.name = "kirkwood_cpuidle",
|
||||||
|
.id = -1,
|
||||||
|
.resource = kirkwood_cpuidle_resource,
|
||||||
|
.num_resources = 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
void __init kirkwood_cpuidle_init(void)
|
||||||
|
{
|
||||||
|
platform_device_register(&kirkwood_cpuidle);
|
||||||
|
}
|
||||||
|
|
||||||
/*****************************************************************************
|
/*****************************************************************************
|
||||||
* Time handling
|
* Time handling
|
||||||
|
|
@ -667,6 +689,7 @@ void __init kirkwood_init(void)
|
||||||
kirkwood_xor1_init();
|
kirkwood_xor1_init();
|
||||||
kirkwood_crypto_init();
|
kirkwood_crypto_init();
|
||||||
|
|
||||||
|
kirkwood_cpuidle_init();
|
||||||
#ifdef CONFIG_KEXEC
|
#ifdef CONFIG_KEXEC
|
||||||
kexec_reinit = kirkwood_enable_pcie;
|
kexec_reinit = kirkwood_enable_pcie;
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -50,6 +50,7 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
|
||||||
void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
|
void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
|
||||||
int (*dev_ready)(struct mtd_info *));
|
int (*dev_ready)(struct mtd_info *));
|
||||||
void kirkwood_audio_init(void);
|
void kirkwood_audio_init(void);
|
||||||
|
void kirkwood_cpuidle_init(void);
|
||||||
void kirkwood_restart(char, const char *);
|
void kirkwood_restart(char, const char *);
|
||||||
void kirkwood_clk_init(void);
|
void kirkwood_clk_init(void);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -60,8 +60,9 @@
|
||||||
* Register Map
|
* Register Map
|
||||||
*/
|
*/
|
||||||
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
|
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
|
||||||
|
#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
|
||||||
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500)
|
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500)
|
||||||
#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418)
|
#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
|
||||||
|
|
||||||
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
|
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
|
||||||
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
|
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
|
||||||
|
|
|
||||||
|
|
@ -247,13 +247,9 @@ static struct hw_pci kirkwood_pci __initdata = {
|
||||||
|
|
||||||
static void __init add_pcie_port(int index, void __iomem *base)
|
static void __init add_pcie_port(int index, void __iomem *base)
|
||||||
{
|
{
|
||||||
pr_info("Kirkwood PCIe port %d: ", index);
|
pcie_port_map[num_pcie_ports++] = index;
|
||||||
|
pr_info("Kirkwood PCIe port %d: link %s\n", index,
|
||||||
if (orion_pcie_link_up(base)) {
|
orion_pcie_link_up(base) ? "up" : "down");
|
||||||
pr_info("link up\n");
|
|
||||||
pcie_port_map[num_pcie_ports++] = index;
|
|
||||||
} else
|
|
||||||
pr_info("link down, ignoring\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init kirkwood_pcie_init(unsigned int portmask)
|
void __init kirkwood_pcie_init(unsigned int portmask)
|
||||||
|
|
|
||||||
|
|
@ -72,8 +72,9 @@
|
||||||
#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
|
#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
|
||||||
#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
|
#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
|
||||||
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
||||||
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
|
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
|
||||||
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
|
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
|
||||||
|
#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
|
||||||
|
|
||||||
static struct clock_event_device mxs_clockevent_device;
|
static struct clock_event_device mxs_clockevent_device;
|
||||||
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
|
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
|
||||||
|
|
@ -206,7 +207,8 @@ static int __init mxs_clockevent_init(struct clk *timer_clk)
|
||||||
mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
|
mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
|
||||||
mxs_clockevent_device.cpumask = cpumask_of(0);
|
mxs_clockevent_device.cpumask = cpumask_of(0);
|
||||||
clockevents_config_and_register(&mxs_clockevent_device,
|
clockevents_config_and_register(&mxs_clockevent_device,
|
||||||
clk_get_rate(timer_clk), 0xf,
|
clk_get_rate(timer_clk),
|
||||||
|
timrot_is_v1() ? 0xf : 0x2,
|
||||||
timrot_is_v1() ? 0xfffe : 0xfffffffe);
|
timrot_is_v1() ? 0xfffe : 0xfffffffe);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -274,7 +276,7 @@ void __init mxs_timer_init(void)
|
||||||
/* one for clock_event */
|
/* one for clock_event */
|
||||||
__raw_writel((timrot_is_v1() ?
|
__raw_writel((timrot_is_v1() ?
|
||||||
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
||||||
BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
|
BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
|
||||||
BM_TIMROT_TIMCTRLn_UPDATE |
|
BM_TIMROT_TIMCTRLn_UPDATE |
|
||||||
BM_TIMROT_TIMCTRLn_IRQ_EN,
|
BM_TIMROT_TIMCTRLn_IRQ_EN,
|
||||||
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
|
mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
|
||||||
|
|
@ -282,7 +284,7 @@ void __init mxs_timer_init(void)
|
||||||
/* another for clocksource */
|
/* another for clocksource */
|
||||||
__raw_writel((timrot_is_v1() ?
|
__raw_writel((timrot_is_v1() ?
|
||||||
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
|
||||||
BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
|
BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
|
||||||
BM_TIMROT_TIMCTRLn_RELOAD,
|
BM_TIMROT_TIMCTRLn_RELOAD,
|
||||||
mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
|
mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -63,7 +63,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
|
|
||||||
pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
|
pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
|
||||||
NULL, 0, false);
|
false);
|
||||||
if (IS_ERR(pdev)) {
|
if (IS_ERR(pdev)) {
|
||||||
WARN(1, "Can't build omap_device for %s:%s.\n",
|
WARN(1, "Can't build omap_device for %s:%s.\n",
|
||||||
oh->class->name, oh->name);
|
oh->class->name, oh->name);
|
||||||
|
|
|
||||||
|
|
@ -425,7 +425,7 @@ static void enable_board_wakeup_source(void)
|
||||||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -53,7 +53,7 @@ static void enable_board_wakeup_source(void)
|
||||||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -40,7 +40,7 @@ static struct omap_board_mux board_mux[] __initdata = {
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -274,7 +274,7 @@ static __init void am3517_evm_mcbsp1_init(void)
|
||||||
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
|
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
|
#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
|
||||||
defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
|
defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
|
||||||
|
|
|
||||||
|
|
@ -419,7 +419,7 @@ static struct omap2_hsmmc_info mmc[] = {
|
||||||
{} /* Terminator */
|
{} /* Terminator */
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -166,7 +166,7 @@ static inline void cm_t3517_init_rtc(void) {}
|
||||||
#define HSUSB2_RESET_GPIO (147)
|
#define HSUSB2_RESET_GPIO (147)
|
||||||
#define USB_HUB_RESET_GPIO (152)
|
#define USB_HUB_RESET_GPIO (152)
|
||||||
|
|
||||||
static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = {
|
static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -436,7 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
|
||||||
&omap_dm9000_dev,
|
&omap_dm9000_dev,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -527,7 +527,7 @@ static void __init igep_i2c_init(void)
|
||||||
omap3_pmic_init("twl4030", &igep_twldata);
|
omap3_pmic_init("twl4030", &igep_twldata);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
@ -538,7 +538,7 @@ static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
|
||||||
.reset_gpio_port[2] = -EINVAL,
|
.reset_gpio_port[2] = -EINVAL,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -431,7 +431,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
|
||||||
&madc_hwmon,
|
&madc_hwmon,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -539,7 +539,7 @@ static int __init omap3_evm_i2c_init(void)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -568,7 +568,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
|
||||||
&pandora_backlight,
|
&pandora_backlight,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -362,7 +362,7 @@ static struct platform_device *omap3_stalker_devices[] __initdata = {
|
||||||
&keys_gpio,
|
&keys_gpio,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -310,7 +310,7 @@ static struct platform_device *omap3_touchbook_devices[] __initdata = {
|
||||||
&keys_gpio,
|
&keys_gpio,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
|
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
|
|
|
||||||
|
|
@ -140,7 +140,7 @@ static struct platform_device *panda_devices[] __initdata = {
|
||||||
&btwilink_device,
|
&btwilink_device,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -458,7 +458,7 @@ static int __init overo_spi_init(void)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -92,7 +92,7 @@ static struct mtd_partition zoom_nand_partitions[] = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
|
||||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||||
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||||
|
|
|
||||||
|
|
@ -622,15 +622,10 @@ static struct clk_hw_omap gpios_fck_hw = {
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
|
DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
|
||||||
|
|
||||||
static struct clk wu_l4_ick;
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
|
|
||||||
DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
|
|
||||||
|
|
||||||
static struct clk gpios_ick;
|
static struct clk gpios_ick;
|
||||||
|
|
||||||
static const char *gpios_ick_parent_names[] = {
|
static const char *gpios_ick_parent_names[] = {
|
||||||
"wu_l4_ick",
|
"sys_ck",
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_hw_omap gpios_ick_hw = {
|
static struct clk_hw_omap gpios_ick_hw = {
|
||||||
|
|
@ -1682,13 +1677,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
|
DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
|
||||||
|
|
||||||
static struct clk wdt1_osc_ck;
|
|
||||||
|
|
||||||
static const struct clk_ops wdt1_osc_ck_ops = {};
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
|
|
||||||
DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
|
|
||||||
|
|
||||||
static struct clk wdt3_fck;
|
static struct clk wdt3_fck;
|
||||||
|
|
||||||
static struct clk_hw_omap wdt3_fck_hw = {
|
static struct clk_hw_omap wdt3_fck_hw = {
|
||||||
|
|
@ -1767,7 +1755,6 @@ static struct omap_clk omap2420_clks[] = {
|
||||||
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
|
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
|
||||||
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
|
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
|
||||||
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
|
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
|
||||||
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
|
|
||||||
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
|
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
|
||||||
CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
|
CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
|
||||||
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
|
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
|
||||||
|
|
@ -1797,7 +1784,6 @@ static struct omap_clk omap2420_clks[] = {
|
||||||
/* L4 domain clocks */
|
/* L4 domain clocks */
|
||||||
CLK(NULL, "l4_ck", &l4_ck, CK_242X),
|
CLK(NULL, "l4_ck", &l4_ck, CK_242X),
|
||||||
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
|
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
|
||||||
CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
|
|
||||||
/* virtual meta-group clock */
|
/* virtual meta-group clock */
|
||||||
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
|
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
|
||||||
/* general l4 interface ck, multi-parent functional clk */
|
/* general l4 interface ck, multi-parent functional clk */
|
||||||
|
|
|
||||||
|
|
@ -601,15 +601,10 @@ static struct clk_hw_omap gpios_fck_hw = {
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
|
DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
|
||||||
|
|
||||||
static struct clk wu_l4_ick;
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
|
|
||||||
DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
|
|
||||||
|
|
||||||
static struct clk gpios_ick;
|
static struct clk gpios_ick;
|
||||||
|
|
||||||
static const char *gpios_ick_parent_names[] = {
|
static const char *gpios_ick_parent_names[] = {
|
||||||
"wu_l4_ick",
|
"sys_ck",
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_hw_omap gpios_ick_hw = {
|
static struct clk_hw_omap gpios_ick_hw = {
|
||||||
|
|
@ -1811,13 +1806,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
|
DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
|
||||||
|
|
||||||
static struct clk wdt1_osc_ck;
|
|
||||||
|
|
||||||
static const struct clk_ops wdt1_osc_ck_ops = {};
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
|
|
||||||
DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
|
|
||||||
|
|
||||||
static struct clk wdt4_fck;
|
static struct clk wdt4_fck;
|
||||||
|
|
||||||
static struct clk_hw_omap wdt4_fck_hw = {
|
static struct clk_hw_omap wdt4_fck_hw = {
|
||||||
|
|
@ -1869,7 +1857,6 @@ static struct omap_clk omap2430_clks[] = {
|
||||||
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
|
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
|
||||||
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
|
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
|
||||||
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
|
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
|
||||||
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
|
|
||||||
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
|
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
|
||||||
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
|
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
|
||||||
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
|
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
|
||||||
|
|
@ -1898,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
|
||||||
/* L4 domain clocks */
|
/* L4 domain clocks */
|
||||||
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
|
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
|
||||||
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
|
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
|
||||||
CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
|
|
||||||
/* virtual meta-group clock */
|
/* virtual meta-group clock */
|
||||||
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
|
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
|
||||||
/* general l4 interface ck, multi-parent functional clk */
|
/* general l4 interface ck, multi-parent functional clk */
|
||||||
|
|
|
||||||
|
|
@ -16,6 +16,10 @@
|
||||||
* XXX Some of the ES1 clocks have been removed/changed; once support
|
* XXX Some of the ES1 clocks have been removed/changed; once support
|
||||||
* is added for discriminating clocks by ES level, these should be added back
|
* is added for discriminating clocks by ES level, these should be added back
|
||||||
* in.
|
* in.
|
||||||
|
*
|
||||||
|
* XXX All of the remaining MODULEMODE clock nodes should be removed
|
||||||
|
* once the drivers are updated to use pm_runtime or to use the appropriate
|
||||||
|
* upstream clock node for rate/parent selection.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
|
|
@ -315,7 +319,7 @@ DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
|
||||||
OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
|
OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
|
||||||
OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
|
OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
|
||||||
|
|
||||||
static const struct clk_ops dmic_fck_ops = {
|
static const struct clk_ops dpll_hsd_ops = {
|
||||||
.enable = &omap2_dflt_clk_enable,
|
.enable = &omap2_dflt_clk_enable,
|
||||||
.disable = &omap2_dflt_clk_disable,
|
.disable = &omap2_dflt_clk_disable,
|
||||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||||
|
|
@ -325,6 +329,12 @@ static const struct clk_ops dmic_fck_ops = {
|
||||||
.init = &omap2_init_clk_clkdm,
|
.init = &omap2_init_clk_clkdm,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops func_dmic_abe_gfclk_ops = {
|
||||||
|
.recalc_rate = &omap2_clksel_recalc,
|
||||||
|
.get_parent = &omap2_clksel_find_parent_index,
|
||||||
|
.set_parent = &omap2_clksel_set_parent,
|
||||||
|
};
|
||||||
|
|
||||||
static const char *dpll_core_m3x2_ck_parents[] = {
|
static const char *dpll_core_m3x2_ck_parents[] = {
|
||||||
"dpll_core_x2_ck",
|
"dpll_core_x2_ck",
|
||||||
};
|
};
|
||||||
|
|
@ -340,7 +350,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
|
||||||
OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
||||||
OMAP4430_CM_DIV_M3_DPLL_CORE,
|
OMAP4430_CM_DIV_M3_DPLL_CORE,
|
||||||
OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
|
OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
|
||||||
dpll_core_m3x2_ck_parents, dmic_fck_ops);
|
dpll_core_m3x2_ck_parents, dpll_hsd_ops);
|
||||||
|
|
||||||
DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
|
DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
|
||||||
&dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
|
&dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
|
||||||
|
|
@ -547,7 +557,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
|
||||||
OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
|
||||||
OMAP4430_CM_DIV_M3_DPLL_PER,
|
OMAP4430_CM_DIV_M3_DPLL_PER,
|
||||||
OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
|
OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
|
||||||
dpll_per_m3x2_ck_parents, dmic_fck_ops);
|
dpll_per_m3x2_ck_parents, dpll_hsd_ops);
|
||||||
|
|
||||||
DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
|
DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
|
||||||
0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
|
0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
|
||||||
|
|
@ -749,10 +759,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
|
||||||
OMAP4430_CM_L4SEC_AES2_CLKCTRL,
|
OMAP4430_CM_L4SEC_AES2_CLKCTRL,
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
|
|
||||||
OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
|
OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
|
||||||
|
|
@ -774,11 +780,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
|
||||||
OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
|
OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
static const char *dmic_sync_mux_ck_parents[] = {
|
static const char *dmic_sync_mux_ck_parents[] = {
|
||||||
"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
|
"abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
|
||||||
};
|
};
|
||||||
|
|
@ -795,23 +796,13 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *dmic_fck_parents[] = {
|
static const char *func_dmic_abe_gfclk_parents[] = {
|
||||||
"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
"dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged func_dmic_abe_gfclk into dmic */
|
DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
|
||||||
static struct clk dmic_fck;
|
OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
|
||||||
|
func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
|
|
||||||
OMAP4430_CM1_ABE_DMIC_CLKCTRL,
|
|
||||||
OMAP4430_CLKSEL_SOURCE_MASK,
|
|
||||||
OMAP4430_CM1_ABE_DMIC_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
dmic_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
|
|
||||||
OMAP4430_CM_TESLA_TESLA_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
|
DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
|
||||||
OMAP4430_CM_DSS_DSS_CLKCTRL,
|
OMAP4430_CM_DSS_DSS_CLKCTRL,
|
||||||
|
|
@ -833,177 +824,57 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
|
||||||
OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
|
|
||||||
OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
|
|
||||||
OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
|
|
||||||
OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
|
DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
|
||||||
OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
|
OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
|
||||||
OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
|
OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
|
OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
|
|
||||||
OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
|
OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
|
||||||
OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
static const struct clksel sgx_clk_mux_sel[] = {
|
static const struct clksel sgx_clk_mux_sel[] = {
|
||||||
{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
|
{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
|
||||||
{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
|
{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *gpu_fck_parents[] = {
|
static const char *sgx_clk_mux_parents[] = {
|
||||||
"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
|
"dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged sgx_clk_mux into gpu */
|
DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
|
OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
|
||||||
OMAP4430_CM_GFX_GFX_CLKCTRL,
|
sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CLKSEL_SGX_FCLK_MASK,
|
|
||||||
OMAP4430_CM_GFX_GFX_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
gpu_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
|
DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
|
||||||
OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
|
OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
|
||||||
OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
|
OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
|
||||||
NULL);
|
NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_I2C1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_I2C2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_I2C3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_I2C4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
|
|
||||||
OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
|
DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
|
||||||
OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
|
OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
|
|
||||||
OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
|
|
||||||
OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
|
|
||||||
OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
static struct clk l3_instr_ick;
|
|
||||||
|
|
||||||
static const char *l3_instr_ick_parent_names[] = {
|
|
||||||
"l3_div_ck",
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops l3_instr_ick_ops = {
|
|
||||||
.enable = &omap2_dflt_clk_enable,
|
|
||||||
.disable = &omap2_dflt_clk_disable,
|
|
||||||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
|
||||||
.init = &omap2_init_clk_clkdm,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_hw_omap l3_instr_ick_hw = {
|
|
||||||
.hw = {
|
|
||||||
.clk = &l3_instr_ick,
|
|
||||||
},
|
|
||||||
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
|
|
||||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
.clkdm_name = "l3_instr_clkdm",
|
|
||||||
};
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
|
|
||||||
|
|
||||||
static struct clk l3_main_3_ick;
|
|
||||||
static struct clk_hw_omap l3_main_3_ick_hw = {
|
|
||||||
.hw = {
|
|
||||||
.clk = &l3_main_3_ick,
|
|
||||||
},
|
|
||||||
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
|
|
||||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
.clkdm_name = "l3_instr_clkdm",
|
|
||||||
};
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
||||||
OMAP4430_CM1_ABE_MCASP_CLKCTRL,
|
OMAP4430_CM1_ABE_MCASP_CLKCTRL,
|
||||||
OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
|
OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
|
||||||
|
|
@ -1016,17 +887,13 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mcasp_fck_parents[] = {
|
static const char *func_mcasp_abe_gfclk_parents[] = {
|
||||||
"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
"mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged func_mcasp_abe_gfclk into mcasp */
|
DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
|
OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
|
||||||
OMAP4430_CM1_ABE_MCASP_CLKCTRL,
|
func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CLKSEL_SOURCE_MASK,
|
|
||||||
OMAP4430_CM1_ABE_MCASP_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mcasp_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
||||||
OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
|
OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
|
||||||
|
|
@ -1040,17 +907,14 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mcbsp1_fck_parents[] = {
|
static const char *func_mcbsp1_gfclk_parents[] = {
|
||||||
"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
"mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged func_mcbsp1_gfclk into mcbsp1 */
|
DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
|
OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
|
||||||
OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
|
OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
|
||||||
OMAP4430_CLKSEL_SOURCE_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mcbsp1_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
||||||
OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
|
OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
|
||||||
|
|
@ -1064,17 +928,14 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mcbsp2_fck_parents[] = {
|
static const char *func_mcbsp2_gfclk_parents[] = {
|
||||||
"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
"mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged func_mcbsp2_gfclk into mcbsp2 */
|
DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
|
OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
|
||||||
OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
|
OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
|
||||||
OMAP4430_CLKSEL_SOURCE_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mcbsp2_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
|
||||||
OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
|
OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
|
||||||
|
|
@ -1088,17 +949,14 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mcbsp3_fck_parents[] = {
|
static const char *func_mcbsp3_gfclk_parents[] = {
|
||||||
"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
"mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged func_mcbsp3_gfclk into mcbsp3 */
|
DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
|
OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
|
||||||
OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
|
OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
|
||||||
OMAP4430_CLKSEL_SOURCE_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mcbsp3_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
static const char *mcbsp4_sync_mux_ck_parents[] = {
|
static const char *mcbsp4_sync_mux_ck_parents[] = {
|
||||||
"func_96m_fclk", "per_abe_nc_fclk",
|
"func_96m_fclk", "per_abe_nc_fclk",
|
||||||
|
|
@ -1115,37 +973,14 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mcbsp4_fck_parents[] = {
|
static const char *per_mcbsp4_gfclk_parents[] = {
|
||||||
"mcbsp4_sync_mux_ck", "pad_clks_ck",
|
"mcbsp4_sync_mux_ck", "pad_clks_ck",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged per_mcbsp4_gfclk into mcbsp4 */
|
DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
|
OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
|
||||||
OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
|
OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
|
||||||
OMAP4430_CLKSEL_SOURCE_24_24_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mcbsp4_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
|
|
||||||
OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
static const struct clksel hsmmc1_fclk_sel[] = {
|
static const struct clksel hsmmc1_fclk_sel[] = {
|
||||||
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
|
||||||
|
|
@ -1153,69 +988,22 @@ static const struct clksel hsmmc1_fclk_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *mmc1_fck_parents[] = {
|
static const char *hsmmc1_fclk_parents[] = {
|
||||||
"func_64m_fclk", "func_96m_fclk",
|
"func_64m_fclk", "func_96m_fclk",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged hsmmc1_fclk into mmc1 */
|
DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
|
OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mmc1_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged hsmmc2_fclk into mmc2 */
|
DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
|
OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
mmc1_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
|
|
||||||
OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
static struct clk ocp_wp_noc_ick;
|
|
||||||
|
|
||||||
static struct clk_hw_omap ocp_wp_noc_ick_hw = {
|
|
||||||
.hw = {
|
|
||||||
.clk = &ocp_wp_noc_ick,
|
|
||||||
},
|
|
||||||
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
|
|
||||||
.enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
.clkdm_name = "l3_instr_clkdm",
|
|
||||||
};
|
|
||||||
|
|
||||||
DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
|
DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
|
||||||
OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
|
OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
|
|
||||||
OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
|
DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
|
||||||
OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
|
OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
|
||||||
|
|
@ -1232,10 +1020,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
|
||||||
OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
|
OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
|
|
||||||
OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
|
DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
|
||||||
OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
|
OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
|
||||||
|
|
@ -1249,10 +1033,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
|
||||||
OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
|
OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
|
||||||
OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
|
OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
|
DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
|
||||||
0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
|
0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
||||||
|
|
@ -1271,52 +1051,35 @@ static const struct clksel dmt1_clk_mux_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged dmt1_clk_mux into timer1 */
|
DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm10_mux into timer10 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm11_mux into timer11 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm2_mux into timer2 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm3_mux into timer3 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm4_mux into timer4 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
static const struct clksel timer5_sync_mux_sel[] = {
|
static const struct clksel timer5_sync_mux_sel[] = {
|
||||||
{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
|
{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
|
||||||
|
|
@ -1324,61 +1087,30 @@ static const struct clksel timer5_sync_mux_sel[] = {
|
||||||
{ .parent = NULL },
|
{ .parent = NULL },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *timer5_fck_parents[] = {
|
static const char *timer5_sync_mux_parents[] = {
|
||||||
"syc_clk_div_ck", "sys_32k_ck",
|
"syc_clk_div_ck", "sys_32k_ck",
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Merged timer5_sync_mux into timer5 */
|
DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
|
OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
timer5_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged timer6_sync_mux into timer6 */
|
DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
|
OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
timer5_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged timer7_sync_mux into timer7 */
|
DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
|
OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
timer5_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged timer8_sync_mux into timer8 */
|
DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
|
OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
timer5_fck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
/* Merged cm2_dm9_mux into timer9 */
|
DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
|
||||||
DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
|
OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||||
OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
|
abe_dpll_bypass_clk_mux_ck_parents,
|
||||||
OMAP4430_CLKSEL_MASK,
|
func_dmic_abe_gfclk_ops);
|
||||||
OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
|
|
||||||
abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_UART1_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_UART2_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_UART3_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
|
|
||||||
OMAP4430_CM_L4PER_UART4_CLKCTRL,
|
|
||||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
|
||||||
|
|
||||||
static struct clk usb_host_fs_fck;
|
static struct clk usb_host_fs_fck;
|
||||||
|
|
||||||
|
|
@ -1512,18 +1244,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
|
||||||
OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
|
OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
|
||||||
0x0, NULL);
|
0x0, NULL);
|
||||||
|
|
||||||
DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
|
|
||||||
OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
|
|
||||||
OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
|
|
||||||
OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
|
|
||||||
0x0, NULL);
|
|
||||||
|
|
||||||
/* Remaining optional clocks */
|
/* Remaining optional clocks */
|
||||||
static const char *pmd_stm_clock_mux_ck_parents[] = {
|
static const char *pmd_stm_clock_mux_ck_parents[] = {
|
||||||
"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
|
"sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
|
||||||
|
|
@ -1774,106 +1494,61 @@ static struct omap_clk omap44xx_clks[] = {
|
||||||
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
|
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
|
||||||
CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
|
CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
|
||||||
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
|
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
|
||||||
CLK(NULL, "aess_fck", &aess_fck, CK_443X),
|
|
||||||
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
|
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
|
||||||
CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
|
CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
|
||||||
CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
|
CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
|
||||||
CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
|
|
||||||
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
|
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
|
CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X),
|
||||||
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
|
|
||||||
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
|
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
|
||||||
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
|
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
|
||||||
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
|
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
|
||||||
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
|
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
|
||||||
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
|
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
|
||||||
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
|
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
|
||||||
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
|
|
||||||
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
|
|
||||||
CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
|
|
||||||
CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
|
CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
|
||||||
CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
|
|
||||||
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
|
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
|
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
|
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
|
CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
|
CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
|
CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
|
||||||
CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
|
CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X),
|
||||||
CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
|
|
||||||
CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
|
|
||||||
CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
|
|
||||||
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
|
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
|
||||||
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
|
|
||||||
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
|
|
||||||
CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
|
|
||||||
CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
|
|
||||||
CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
|
|
||||||
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
|
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
|
||||||
CLK(NULL, "iss_fck", &iss_fck, CK_443X),
|
|
||||||
CLK(NULL, "iva_fck", &iva_fck, CK_443X),
|
|
||||||
CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
|
|
||||||
CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
|
|
||||||
CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
|
|
||||||
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
|
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
|
CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X),
|
||||||
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
|
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
|
CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X),
|
||||||
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
|
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
|
CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X),
|
||||||
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
|
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
|
CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X),
|
||||||
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
|
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
|
||||||
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
|
CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
|
||||||
CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
|
CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
|
||||||
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
|
CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
|
||||||
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
|
|
||||||
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
|
|
||||||
CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
|
|
||||||
CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
|
|
||||||
CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
|
|
||||||
CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
|
|
||||||
CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
|
|
||||||
CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
|
|
||||||
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
|
|
||||||
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
|
|
||||||
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
|
|
||||||
CLK(NULL, "rng_ick", &rng_ick, CK_443X),
|
|
||||||
CLK("omap_rng", "ick", &rng_ick, CK_443X),
|
|
||||||
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
|
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
|
||||||
CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
|
|
||||||
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
|
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
|
||||||
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
|
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
|
||||||
CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
|
CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
|
||||||
CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
|
CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
|
||||||
CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
|
|
||||||
CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
|
CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
|
||||||
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
|
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
|
||||||
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
|
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
|
||||||
CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
|
|
||||||
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
|
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
|
||||||
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
|
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
|
||||||
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
|
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
|
||||||
CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
|
CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X),
|
||||||
CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
|
CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X),
|
||||||
CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
|
CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X),
|
||||||
CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
|
CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X),
|
||||||
CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
|
CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X),
|
||||||
CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
|
CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X),
|
||||||
CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
|
CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X),
|
||||||
CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
|
CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X),
|
||||||
CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
|
CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X),
|
||||||
CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
|
CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X),
|
||||||
CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
|
CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X),
|
||||||
CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
|
|
||||||
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
|
|
||||||
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
|
|
||||||
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
|
|
||||||
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
|
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
|
||||||
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
|
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
|
||||||
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
|
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
|
||||||
|
|
@ -1901,9 +1576,6 @@ static struct omap_clk omap44xx_clks[] = {
|
||||||
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
|
||||||
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
|
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
|
||||||
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
|
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
|
||||||
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
|
|
||||||
CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
|
|
||||||
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
|
|
||||||
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
|
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
|
||||||
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
|
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
|
||||||
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
|
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
|
||||||
|
|
@ -1980,15 +1652,6 @@ static struct omap_clk omap44xx_clks[] = {
|
||||||
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
|
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *enable_init_clks[] = {
|
|
||||||
"emif1_fck",
|
|
||||||
"emif2_fck",
|
|
||||||
"gpmc_ick",
|
|
||||||
"l3_instr_ick",
|
|
||||||
"l3_main_3_ick",
|
|
||||||
"ocp_wp_noc_ick",
|
|
||||||
};
|
|
||||||
|
|
||||||
int __init omap4xxx_clk_init(void)
|
int __init omap4xxx_clk_init(void)
|
||||||
{
|
{
|
||||||
u32 cpu_clkflg;
|
u32 cpu_clkflg;
|
||||||
|
|
@ -2019,9 +1682,6 @@ int __init omap4xxx_clk_init(void)
|
||||||
|
|
||||||
omap2_clk_disable_autoidle_all();
|
omap2_clk_disable_autoidle_all();
|
||||||
|
|
||||||
omap2_clk_enable_init_clocks(enable_init_clks,
|
|
||||||
ARRAY_SIZE(enable_init_clks));
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
|
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
|
||||||
* state when turning the ABE clock domain. Workaround this by
|
* state when turning the ABE clock domain. Workaround this by
|
||||||
|
|
|
||||||
|
|
@ -92,8 +92,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
|
||||||
|
|
||||||
pwrdm_add_clkdm(pwrdm, clkdm);
|
pwrdm_add_clkdm(pwrdm, clkdm);
|
||||||
|
|
||||||
spin_lock_init(&clkdm->lock);
|
|
||||||
|
|
||||||
pr_debug("clockdomain: registered %s\n", clkdm->name);
|
pr_debug("clockdomain: registered %s\n", clkdm->name);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -122,7 +120,7 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
|
||||||
return cd;
|
return cd;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/**
|
||||||
* _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
|
* _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
|
||||||
* @autodep: struct clkdm_autodep * to resolve
|
* @autodep: struct clkdm_autodep * to resolve
|
||||||
*
|
*
|
||||||
|
|
@ -154,66 +152,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
|
||||||
autodep->clkdm.ptr = clkdm;
|
autodep->clkdm.ptr = clkdm;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
* _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
|
|
||||||
* @clkdm: struct clockdomain *
|
|
||||||
*
|
|
||||||
* Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
|
|
||||||
* in hardware-supervised mode. Meant to be called from clock framework
|
|
||||||
* when a clock inside clockdomain 'clkdm' is enabled. No return value.
|
|
||||||
*
|
|
||||||
* XXX autodeps are deprecated and should be removed at the earliest
|
|
||||||
* opportunity
|
|
||||||
*/
|
|
||||||
void _clkdm_add_autodeps(struct clockdomain *clkdm)
|
|
||||||
{
|
|
||||||
struct clkdm_autodep *autodep;
|
|
||||||
|
|
||||||
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
|
|
||||||
return;
|
|
||||||
|
|
||||||
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
|
|
||||||
if (IS_ERR(autodep->clkdm.ptr))
|
|
||||||
continue;
|
|
||||||
|
|
||||||
pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
|
|
||||||
clkdm->name, autodep->clkdm.ptr->name);
|
|
||||||
|
|
||||||
clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
|
|
||||||
clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
|
|
||||||
* @clkdm: struct clockdomain *
|
|
||||||
*
|
|
||||||
* Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
|
|
||||||
* in hardware-supervised mode. Meant to be called from clock framework
|
|
||||||
* when a clock inside clockdomain 'clkdm' is disabled. No return value.
|
|
||||||
*
|
|
||||||
* XXX autodeps are deprecated and should be removed at the earliest
|
|
||||||
* opportunity
|
|
||||||
*/
|
|
||||||
void _clkdm_del_autodeps(struct clockdomain *clkdm)
|
|
||||||
{
|
|
||||||
struct clkdm_autodep *autodep;
|
|
||||||
|
|
||||||
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
|
|
||||||
return;
|
|
||||||
|
|
||||||
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
|
|
||||||
if (IS_ERR(autodep->clkdm.ptr))
|
|
||||||
continue;
|
|
||||||
|
|
||||||
pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
|
|
||||||
clkdm->name, autodep->clkdm.ptr->name);
|
|
||||||
|
|
||||||
clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
|
|
||||||
clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
|
* _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
|
||||||
* @clkdm: clockdomain that we are resolving dependencies for
|
* @clkdm: clockdomain that we are resolving dependencies for
|
||||||
|
|
@ -238,6 +176,184 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* _clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 (lockless)
|
||||||
|
* @clkdm1: wake this struct clockdomain * up (dependent)
|
||||||
|
* @clkdm2: when this struct clockdomain * wakes up (source)
|
||||||
|
*
|
||||||
|
* When the clockdomain represented by @clkdm2 wakes up, wake up
|
||||||
|
* @clkdm1. Implemented in hardware on the OMAP, this feature is
|
||||||
|
* designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
|
||||||
|
* Returns -EINVAL if presented with invalid clockdomain pointers,
|
||||||
|
* -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
|
||||||
|
* success.
|
||||||
|
*/
|
||||||
|
static int _clkdm_add_wkdep(struct clockdomain *clkdm1,
|
||||||
|
struct clockdomain *clkdm2)
|
||||||
|
{
|
||||||
|
struct clkdm_dep *cd;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (!clkdm1 || !clkdm2)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
|
if (IS_ERR(cd))
|
||||||
|
ret = PTR_ERR(cd);
|
||||||
|
|
||||||
|
if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
|
||||||
|
ret = -EINVAL;
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
cd->wkdep_usecount++;
|
||||||
|
if (cd->wkdep_usecount == 1) {
|
||||||
|
pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
|
||||||
|
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* _clkdm_del_wkdep - remove a wakeup dep from clkdm2 to clkdm1 (lockless)
|
||||||
|
* @clkdm1: wake this struct clockdomain * up (dependent)
|
||||||
|
* @clkdm2: when this struct clockdomain * wakes up (source)
|
||||||
|
*
|
||||||
|
* Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
|
||||||
|
* wakes up. Returns -EINVAL if presented with invalid clockdomain
|
||||||
|
* pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
|
||||||
|
* 0 upon success.
|
||||||
|
*/
|
||||||
|
static int _clkdm_del_wkdep(struct clockdomain *clkdm1,
|
||||||
|
struct clockdomain *clkdm2)
|
||||||
|
{
|
||||||
|
struct clkdm_dep *cd;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (!clkdm1 || !clkdm2)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
|
if (IS_ERR(cd))
|
||||||
|
ret = PTR_ERR(cd);
|
||||||
|
|
||||||
|
if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
|
||||||
|
ret = -EINVAL;
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
cd->wkdep_usecount--;
|
||||||
|
if (cd->wkdep_usecount == 0) {
|
||||||
|
pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
|
||||||
|
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* _clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 (lockless)
|
||||||
|
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
|
||||||
|
* @clkdm2: when this struct clockdomain * is active (source)
|
||||||
|
*
|
||||||
|
* Prevent @clkdm1 from automatically going inactive (and then to
|
||||||
|
* retention or off) if @clkdm2 is active. Returns -EINVAL if
|
||||||
|
* presented with invalid clockdomain pointers or called on a machine
|
||||||
|
* that does not support software-configurable hardware sleep
|
||||||
|
* dependencies, -ENOENT if the specified dependency cannot be set in
|
||||||
|
* hardware, or 0 upon success.
|
||||||
|
*/
|
||||||
|
static int _clkdm_add_sleepdep(struct clockdomain *clkdm1,
|
||||||
|
struct clockdomain *clkdm2)
|
||||||
|
{
|
||||||
|
struct clkdm_dep *cd;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (!clkdm1 || !clkdm2)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
|
||||||
|
if (IS_ERR(cd))
|
||||||
|
ret = PTR_ERR(cd);
|
||||||
|
|
||||||
|
if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
|
||||||
|
ret = -EINVAL;
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
cd->sleepdep_usecount++;
|
||||||
|
if (cd->sleepdep_usecount == 1) {
|
||||||
|
pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
|
||||||
|
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* _clkdm_del_sleepdep - remove a sleep dep from clkdm2 to clkdm1 (lockless)
|
||||||
|
* @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
|
||||||
|
* @clkdm2: when this struct clockdomain * is active (source)
|
||||||
|
*
|
||||||
|
* Allow @clkdm1 to automatically go inactive (and then to retention or
|
||||||
|
* off), independent of the activity state of @clkdm2. Returns -EINVAL
|
||||||
|
* if presented with invalid clockdomain pointers or called on a machine
|
||||||
|
* that does not support software-configurable hardware sleep dependencies,
|
||||||
|
* -ENOENT if the specified dependency cannot be cleared in hardware, or
|
||||||
|
* 0 upon success.
|
||||||
|
*/
|
||||||
|
static int _clkdm_del_sleepdep(struct clockdomain *clkdm1,
|
||||||
|
struct clockdomain *clkdm2)
|
||||||
|
{
|
||||||
|
struct clkdm_dep *cd;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (!clkdm1 || !clkdm2)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
|
||||||
|
if (IS_ERR(cd))
|
||||||
|
ret = PTR_ERR(cd);
|
||||||
|
|
||||||
|
if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
|
||||||
|
ret = -EINVAL;
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
cd->sleepdep_usecount--;
|
||||||
|
if (cd->sleepdep_usecount == 0) {
|
||||||
|
pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
|
||||||
|
clkdm1->name, clkdm2->name);
|
||||||
|
|
||||||
|
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
/* Public functions */
|
/* Public functions */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -456,30 +572,18 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
|
||||||
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
{
|
{
|
||||||
struct clkdm_dep *cd;
|
struct clkdm_dep *cd;
|
||||||
int ret = 0;
|
int ret;
|
||||||
|
|
||||||
if (!clkdm1 || !clkdm2)
|
if (!clkdm1 || !clkdm2)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
if (IS_ERR(cd))
|
if (IS_ERR(cd))
|
||||||
ret = PTR_ERR(cd);
|
return PTR_ERR(cd);
|
||||||
|
|
||||||
if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
|
pwrdm_lock(cd->clkdm->pwrdm.ptr);
|
||||||
ret = -EINVAL;
|
ret = _clkdm_add_wkdep(clkdm1, clkdm2);
|
||||||
|
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
|
||||||
if (ret) {
|
|
||||||
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
|
|
||||||
pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
|
|
||||||
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -497,30 +601,18 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
{
|
{
|
||||||
struct clkdm_dep *cd;
|
struct clkdm_dep *cd;
|
||||||
int ret = 0;
|
int ret;
|
||||||
|
|
||||||
if (!clkdm1 || !clkdm2)
|
if (!clkdm1 || !clkdm2)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
if (IS_ERR(cd))
|
if (IS_ERR(cd))
|
||||||
ret = PTR_ERR(cd);
|
return PTR_ERR(cd);
|
||||||
|
|
||||||
if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
|
pwrdm_lock(cd->clkdm->pwrdm.ptr);
|
||||||
ret = -EINVAL;
|
ret = _clkdm_del_wkdep(clkdm1, clkdm2);
|
||||||
|
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
|
||||||
if (ret) {
|
|
||||||
pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
|
|
||||||
pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
|
|
||||||
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -560,7 +652,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* XXX It's faster to return the atomic wkdep_usecount */
|
/* XXX It's faster to return the wkdep_usecount */
|
||||||
return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
|
return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -600,30 +692,18 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
|
||||||
int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
{
|
{
|
||||||
struct clkdm_dep *cd;
|
struct clkdm_dep *cd;
|
||||||
int ret = 0;
|
int ret;
|
||||||
|
|
||||||
if (!clkdm1 || !clkdm2)
|
if (!clkdm1 || !clkdm2)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
if (IS_ERR(cd))
|
if (IS_ERR(cd))
|
||||||
ret = PTR_ERR(cd);
|
return PTR_ERR(cd);
|
||||||
|
|
||||||
if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
|
pwrdm_lock(cd->clkdm->pwrdm.ptr);
|
||||||
ret = -EINVAL;
|
ret = _clkdm_add_sleepdep(clkdm1, clkdm2);
|
||||||
|
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
|
||||||
if (ret) {
|
|
||||||
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
|
|
||||||
pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
|
|
||||||
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -643,30 +723,18 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
{
|
{
|
||||||
struct clkdm_dep *cd;
|
struct clkdm_dep *cd;
|
||||||
int ret = 0;
|
int ret;
|
||||||
|
|
||||||
if (!clkdm1 || !clkdm2)
|
if (!clkdm1 || !clkdm2)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
|
cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
|
||||||
if (IS_ERR(cd))
|
if (IS_ERR(cd))
|
||||||
ret = PTR_ERR(cd);
|
return PTR_ERR(cd);
|
||||||
|
|
||||||
if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
|
pwrdm_lock(cd->clkdm->pwrdm.ptr);
|
||||||
ret = -EINVAL;
|
ret = _clkdm_del_sleepdep(clkdm1, clkdm2);
|
||||||
|
pwrdm_unlock(cd->clkdm->pwrdm.ptr);
|
||||||
if (ret) {
|
|
||||||
pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
|
|
||||||
pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
|
|
||||||
clkdm1->name, clkdm2->name);
|
|
||||||
|
|
||||||
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -708,7 +776,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* XXX It's faster to return the atomic sleepdep_usecount */
|
/* XXX It's faster to return the sleepdep_usecount */
|
||||||
return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
|
return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -734,18 +802,17 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* clkdm_sleep - force clockdomain sleep transition
|
* clkdm_sleep_nolock - force clockdomain sleep transition (lockless)
|
||||||
* @clkdm: struct clockdomain *
|
* @clkdm: struct clockdomain *
|
||||||
*
|
*
|
||||||
* Instruct the CM to force a sleep transition on the specified
|
* Instruct the CM to force a sleep transition on the specified
|
||||||
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if
|
* clockdomain @clkdm. Only for use by the powerdomain code. Returns
|
||||||
* clockdomain does not support software-initiated sleep; 0 upon
|
* -EINVAL if @clkdm is NULL or if clockdomain does not support
|
||||||
* success.
|
* software-initiated sleep; 0 upon success.
|
||||||
*/
|
*/
|
||||||
int clkdm_sleep(struct clockdomain *clkdm)
|
int clkdm_sleep_nolock(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
@ -761,26 +828,45 @@ int clkdm_sleep(struct clockdomain *clkdm)
|
||||||
|
|
||||||
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
|
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
|
||||||
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
||||||
ret = arch_clkdm->clkdm_sleep(clkdm);
|
ret = arch_clkdm->clkdm_sleep(clkdm);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* clkdm_wakeup - force clockdomain wakeup transition
|
* clkdm_sleep - force clockdomain sleep transition
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Instruct the CM to force a sleep transition on the specified
|
||||||
|
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if
|
||||||
|
* clockdomain does not support software-initiated sleep; 0 upon
|
||||||
|
* success.
|
||||||
|
*/
|
||||||
|
int clkdm_sleep(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
ret = clkdm_sleep_nolock(clkdm);
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_wakeup_nolock - force clockdomain wakeup transition (lockless)
|
||||||
* @clkdm: struct clockdomain *
|
* @clkdm: struct clockdomain *
|
||||||
*
|
*
|
||||||
* Instruct the CM to force a wakeup transition on the specified
|
* Instruct the CM to force a wakeup transition on the specified
|
||||||
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the
|
* clockdomain @clkdm. Only for use by the powerdomain code. Returns
|
||||||
* clockdomain does not support software-controlled wakeup; 0 upon
|
* -EINVAL if @clkdm is NULL or if the clockdomain does not support
|
||||||
* success.
|
* software-controlled wakeup; 0 upon success.
|
||||||
*/
|
*/
|
||||||
int clkdm_wakeup(struct clockdomain *clkdm)
|
int clkdm_wakeup_nolock(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
@ -796,28 +882,46 @@ int clkdm_wakeup(struct clockdomain *clkdm)
|
||||||
|
|
||||||
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
|
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
|
||||||
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
||||||
ret = arch_clkdm->clkdm_wakeup(clkdm);
|
ret = arch_clkdm->clkdm_wakeup(clkdm);
|
||||||
ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
|
ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* clkdm_allow_idle - enable hwsup idle transitions for clkdm
|
* clkdm_wakeup - force clockdomain wakeup transition
|
||||||
* @clkdm: struct clockdomain *
|
* @clkdm: struct clockdomain *
|
||||||
*
|
*
|
||||||
* Allow the hardware to automatically switch the clockdomain @clkdm into
|
* Instruct the CM to force a wakeup transition on the specified
|
||||||
* active or idle states, as needed by downstream clocks. If the
|
* clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the
|
||||||
|
* clockdomain does not support software-controlled wakeup; 0 upon
|
||||||
|
* success.
|
||||||
|
*/
|
||||||
|
int clkdm_wakeup(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
ret = clkdm_wakeup_nolock(clkdm);
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_allow_idle_nolock - enable hwsup idle transitions for clkdm
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Allow the hardware to automatically switch the clockdomain @clkdm
|
||||||
|
* into active or idle states, as needed by downstream clocks. If the
|
||||||
* clockdomain has any downstream clocks enabled in the clock
|
* clockdomain has any downstream clocks enabled in the clock
|
||||||
* framework, wkdep/sleepdep autodependencies are added; this is so
|
* framework, wkdep/sleepdep autodependencies are added; this is so
|
||||||
* device drivers can read and write to the device. No return value.
|
* device drivers can read and write to the device. Only for use by
|
||||||
|
* the powerdomain code. No return value.
|
||||||
*/
|
*/
|
||||||
void clkdm_allow_idle(struct clockdomain *clkdm)
|
void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
@ -833,11 +937,26 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
|
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
|
||||||
clkdm->name);
|
clkdm->name);
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
|
||||||
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
|
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
|
||||||
arch_clkdm->clkdm_allow_idle(clkdm);
|
arch_clkdm->clkdm_allow_idle(clkdm);
|
||||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_allow_idle - enable hwsup idle transitions for clkdm
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Allow the hardware to automatically switch the clockdomain @clkdm into
|
||||||
|
* active or idle states, as needed by downstream clocks. If the
|
||||||
|
* clockdomain has any downstream clocks enabled in the clock
|
||||||
|
* framework, wkdep/sleepdep autodependencies are added; this is so
|
||||||
|
* device drivers can read and write to the device. No return value.
|
||||||
|
*/
|
||||||
|
void clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
clkdm_allow_idle_nolock(clkdm);
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -847,12 +966,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
* Prevent the hardware from automatically switching the clockdomain
|
* Prevent the hardware from automatically switching the clockdomain
|
||||||
* @clkdm into inactive or idle states. If the clockdomain has
|
* @clkdm into inactive or idle states. If the clockdomain has
|
||||||
* downstream clocks enabled in the clock framework, wkdep/sleepdep
|
* downstream clocks enabled in the clock framework, wkdep/sleepdep
|
||||||
* autodependencies are removed. No return value.
|
* autodependencies are removed. Only for use by the powerdomain
|
||||||
|
* code. No return value.
|
||||||
*/
|
*/
|
||||||
void clkdm_deny_idle(struct clockdomain *clkdm)
|
void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
@ -868,11 +986,25 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
|
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
|
||||||
clkdm->name);
|
clkdm->name);
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
|
||||||
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
||||||
arch_clkdm->clkdm_deny_idle(clkdm);
|
arch_clkdm->clkdm_deny_idle(clkdm);
|
||||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_deny_idle - disable hwsup idle transitions for clkdm
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Prevent the hardware from automatically switching the clockdomain
|
||||||
|
* @clkdm into inactive or idle states. If the clockdomain has
|
||||||
|
* downstream clocks enabled in the clock framework, wkdep/sleepdep
|
||||||
|
* autodependencies are removed. No return value.
|
||||||
|
*/
|
||||||
|
void clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
clkdm_deny_idle_nolock(clkdm);
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -889,14 +1021,11 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
bool clkdm_in_hwsup(struct clockdomain *clkdm)
|
bool clkdm_in_hwsup(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
bool ret;
|
bool ret;
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
|
||||||
ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
|
ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
@ -918,30 +1047,91 @@ bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
|
||||||
return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
|
return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Public autodep handling functions (deprecated) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
|
||||||
|
* in hardware-supervised mode. Meant to be called from clock framework
|
||||||
|
* when a clock inside clockdomain 'clkdm' is enabled. No return value.
|
||||||
|
*
|
||||||
|
* XXX autodeps are deprecated and should be removed at the earliest
|
||||||
|
* opportunity
|
||||||
|
*/
|
||||||
|
void clkdm_add_autodeps(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
struct clkdm_autodep *autodep;
|
||||||
|
|
||||||
|
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
|
||||||
|
if (IS_ERR(autodep->clkdm.ptr))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
|
||||||
|
clkdm->name, autodep->clkdm.ptr->name);
|
||||||
|
|
||||||
|
_clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
|
||||||
|
_clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clkdm_del_autodeps - remove auto sleepdeps/wkdeps from clkdm
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
*
|
||||||
|
* Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
|
||||||
|
* in hardware-supervised mode. Meant to be called from clock framework
|
||||||
|
* when a clock inside clockdomain 'clkdm' is disabled. No return value.
|
||||||
|
*
|
||||||
|
* XXX autodeps are deprecated and should be removed at the earliest
|
||||||
|
* opportunity
|
||||||
|
*/
|
||||||
|
void clkdm_del_autodeps(struct clockdomain *clkdm)
|
||||||
|
{
|
||||||
|
struct clkdm_autodep *autodep;
|
||||||
|
|
||||||
|
if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
|
||||||
|
if (IS_ERR(autodep->clkdm.ptr))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
|
||||||
|
clkdm->name, autodep->clkdm.ptr->name);
|
||||||
|
|
||||||
|
_clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
|
||||||
|
_clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/* Clockdomain-to-clock/hwmod framework interface code */
|
/* Clockdomain-to-clock/hwmod framework interface code */
|
||||||
|
|
||||||
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
|
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
|
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For arch's with no autodeps, clkcm_clk_enable
|
* For arch's with no autodeps, clkcm_clk_enable
|
||||||
* should be called for every clock instance or hwmod that is
|
* should be called for every clock instance or hwmod that is
|
||||||
* enabled, so the clkdm can be force woken up.
|
* enabled, so the clkdm can be force woken up.
|
||||||
*/
|
*/
|
||||||
if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) {
|
clkdm->usecount++;
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
if (clkdm->usecount > 1 && autodeps) {
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
arch_clkdm->clkdm_clk_enable(clkdm);
|
arch_clkdm->clkdm_clk_enable(clkdm);
|
||||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
pr_debug("clockdomain: %s: enabled\n", clkdm->name);
|
pr_debug("clockdomain: %s: enabled\n", clkdm->name);
|
||||||
|
|
||||||
|
|
@ -990,36 +1180,34 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
|
||||||
*/
|
*/
|
||||||
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
|
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
|
if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
/* corner case: disabling unused clocks */
|
/* corner case: disabling unused clocks */
|
||||||
if ((__clk_get_enable_count(clk) == 0) &&
|
if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
|
||||||
(atomic_read(&clkdm->usecount) == 0))
|
|
||||||
goto ccd_exit;
|
goto ccd_exit;
|
||||||
|
|
||||||
if (atomic_read(&clkdm->usecount) == 0) {
|
if (clkdm->usecount == 0) {
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
WARN_ON(1); /* underflow */
|
WARN_ON(1); /* underflow */
|
||||||
return -ERANGE;
|
return -ERANGE;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (atomic_dec_return(&clkdm->usecount) > 0) {
|
clkdm->usecount--;
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
if (clkdm->usecount > 0) {
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
arch_clkdm->clkdm_clk_disable(clkdm);
|
arch_clkdm->clkdm_clk_disable(clkdm);
|
||||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
|
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
|
||||||
|
|
||||||
ccd_exit:
|
ccd_exit:
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -1072,8 +1260,6 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
|
||||||
*/
|
*/
|
||||||
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
|
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
/* The clkdm attribute does not exist yet prior OMAP4 */
|
/* The clkdm attribute does not exist yet prior OMAP4 */
|
||||||
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -1086,22 +1272,23 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
|
||||||
if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
|
if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
spin_lock_irqsave(&clkdm->lock, flags);
|
pwrdm_lock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
if (atomic_read(&clkdm->usecount) == 0) {
|
if (clkdm->usecount == 0) {
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
WARN_ON(1); /* underflow */
|
WARN_ON(1); /* underflow */
|
||||||
return -ERANGE;
|
return -ERANGE;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (atomic_dec_return(&clkdm->usecount) > 0) {
|
clkdm->usecount--;
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
if (clkdm->usecount > 0) {
|
||||||
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
arch_clkdm->clkdm_clk_disable(clkdm);
|
arch_clkdm->clkdm_clk_disable(clkdm);
|
||||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
|
||||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
pwrdm_unlock(clkdm->pwrdm.ptr);
|
||||||
|
|
||||||
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
|
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -15,7 +15,6 @@
|
||||||
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
|
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
|
||||||
|
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/spinlock.h>
|
|
||||||
|
|
||||||
#include "powerdomain.h"
|
#include "powerdomain.h"
|
||||||
#include "clock.h"
|
#include "clock.h"
|
||||||
|
|
@ -92,8 +91,8 @@ struct clkdm_autodep {
|
||||||
struct clkdm_dep {
|
struct clkdm_dep {
|
||||||
const char *clkdm_name;
|
const char *clkdm_name;
|
||||||
struct clockdomain *clkdm;
|
struct clockdomain *clkdm;
|
||||||
atomic_t wkdep_usecount;
|
s16 wkdep_usecount;
|
||||||
atomic_t sleepdep_usecount;
|
s16 sleepdep_usecount;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Possible flags for struct clockdomain._flags */
|
/* Possible flags for struct clockdomain._flags */
|
||||||
|
|
@ -137,9 +136,8 @@ struct clockdomain {
|
||||||
const u16 clkdm_offs;
|
const u16 clkdm_offs;
|
||||||
struct clkdm_dep *wkdep_srcs;
|
struct clkdm_dep *wkdep_srcs;
|
||||||
struct clkdm_dep *sleepdep_srcs;
|
struct clkdm_dep *sleepdep_srcs;
|
||||||
atomic_t usecount;
|
int usecount;
|
||||||
struct list_head node;
|
struct list_head node;
|
||||||
spinlock_t lock;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -196,12 +194,16 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
|
||||||
int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
|
int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
|
||||||
int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
|
int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
|
||||||
|
|
||||||
|
void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
|
||||||
void clkdm_allow_idle(struct clockdomain *clkdm);
|
void clkdm_allow_idle(struct clockdomain *clkdm);
|
||||||
|
void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
|
||||||
void clkdm_deny_idle(struct clockdomain *clkdm);
|
void clkdm_deny_idle(struct clockdomain *clkdm);
|
||||||
bool clkdm_in_hwsup(struct clockdomain *clkdm);
|
bool clkdm_in_hwsup(struct clockdomain *clkdm);
|
||||||
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
|
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
|
||||||
|
|
||||||
|
int clkdm_wakeup_nolock(struct clockdomain *clkdm);
|
||||||
int clkdm_wakeup(struct clockdomain *clkdm);
|
int clkdm_wakeup(struct clockdomain *clkdm);
|
||||||
|
int clkdm_sleep_nolock(struct clockdomain *clkdm);
|
||||||
int clkdm_sleep(struct clockdomain *clkdm);
|
int clkdm_sleep(struct clockdomain *clkdm);
|
||||||
|
|
||||||
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
|
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
|
||||||
|
|
@ -214,8 +216,9 @@ extern void __init omap243x_clockdomains_init(void);
|
||||||
extern void __init omap3xxx_clockdomains_init(void);
|
extern void __init omap3xxx_clockdomains_init(void);
|
||||||
extern void __init am33xx_clockdomains_init(void);
|
extern void __init am33xx_clockdomains_init(void);
|
||||||
extern void __init omap44xx_clockdomains_init(void);
|
extern void __init omap44xx_clockdomains_init(void);
|
||||||
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
|
|
||||||
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
|
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
|
||||||
|
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
|
||||||
|
|
||||||
extern struct clkdm_ops omap2_clkdm_operations;
|
extern struct clkdm_ops omap2_clkdm_operations;
|
||||||
extern struct clkdm_ops omap3_clkdm_operations;
|
extern struct clkdm_ops omap3_clkdm_operations;
|
||||||
|
|
|
||||||
|
|
@ -273,9 +273,6 @@ int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
|
||||||
|
|
||||||
static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
|
static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
|
||||||
_clkdm_add_autodeps(clkdm);
|
|
||||||
|
|
||||||
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
}
|
}
|
||||||
|
|
@ -284,9 +281,6 @@ static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
|
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
|
||||||
_clkdm_del_autodeps(clkdm);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
||||||
|
|
@ -298,18 +292,8 @@ static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
||||||
|
|
||||||
hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
|
if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
|
||||||
if (hwsup) {
|
omap2xxx_clkdm_wakeup(clkdm);
|
||||||
/* Disable HW transitions when we are changing deps */
|
|
||||||
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
|
||||||
clkdm->clktrctrl_mask);
|
|
||||||
_clkdm_add_autodeps(clkdm);
|
|
||||||
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
|
||||||
clkdm->clktrctrl_mask);
|
|
||||||
} else {
|
|
||||||
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
|
|
||||||
omap2xxx_clkdm_wakeup(clkdm);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -324,17 +308,8 @@ static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
|
||||||
hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
|
|
||||||
if (hwsup) {
|
if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
|
||||||
/* Disable HW transitions when we are changing deps */
|
omap2xxx_clkdm_sleep(clkdm);
|
||||||
omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
|
||||||
clkdm->clktrctrl_mask);
|
|
||||||
_clkdm_del_autodeps(clkdm);
|
|
||||||
omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
|
||||||
clkdm->clktrctrl_mask);
|
|
||||||
} else {
|
|
||||||
if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
|
|
||||||
omap2xxx_clkdm_sleep(clkdm);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -186,7 +186,7 @@ static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
|
||||||
continue; /* only happens if data is erroneous */
|
continue; /* only happens if data is erroneous */
|
||||||
|
|
||||||
mask |= 1 << cd->clkdm->dep_bit;
|
mask |= 1 << cd->clkdm->dep_bit;
|
||||||
atomic_set(&cd->sleepdep_usecount, 0);
|
cd->sleepdep_usecount = 0;
|
||||||
}
|
}
|
||||||
omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
|
omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
|
||||||
OMAP3430_CM_SLEEPDEP);
|
OMAP3430_CM_SLEEPDEP);
|
||||||
|
|
@ -209,8 +209,8 @@ static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
|
||||||
|
|
||||||
static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
|
static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
if (clkdm->usecount > 0)
|
||||||
_clkdm_add_autodeps(clkdm);
|
clkdm_add_autodeps(clkdm);
|
||||||
|
|
||||||
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
|
|
@ -221,8 +221,8 @@ static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
|
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
if (clkdm->usecount > 0)
|
||||||
_clkdm_del_autodeps(clkdm);
|
clkdm_del_autodeps(clkdm);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
||||||
|
|
@ -250,7 +250,7 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
||||||
/* Disable HW transitions when we are changing deps */
|
/* Disable HW transitions when we are changing deps */
|
||||||
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
_clkdm_add_autodeps(clkdm);
|
clkdm_add_autodeps(clkdm);
|
||||||
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -287,7 +287,7 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
|
||||||
/* Disable HW transitions when we are changing deps */
|
/* Disable HW transitions when we are changing deps */
|
||||||
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
_clkdm_del_autodeps(clkdm);
|
clkdm_del_autodeps(clkdm);
|
||||||
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||||
clkdm->clktrctrl_mask);
|
clkdm->clktrctrl_mask);
|
||||||
} else {
|
} else {
|
||||||
|
|
|
||||||
|
|
@ -393,7 +393,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
|
||||||
continue; /* only happens if data is erroneous */
|
continue; /* only happens if data is erroneous */
|
||||||
|
|
||||||
mask |= 1 << cd->clkdm->dep_bit;
|
mask |= 1 << cd->clkdm->dep_bit;
|
||||||
atomic_set(&cd->wkdep_usecount, 0);
|
cd->wkdep_usecount = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
|
omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
|
||||||
|
|
|
||||||
|
|
@ -36,40 +36,66 @@
|
||||||
|
|
||||||
/* Mach specific information to be recorded in the C-state driver_data */
|
/* Mach specific information to be recorded in the C-state driver_data */
|
||||||
struct omap3_idle_statedata {
|
struct omap3_idle_statedata {
|
||||||
u32 mpu_state;
|
u8 mpu_state;
|
||||||
u32 core_state;
|
u8 core_state;
|
||||||
|
u8 per_min_state;
|
||||||
|
u8 flags;
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
|
static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Possible flag bits for struct omap3_idle_statedata.flags:
|
||||||
|
*
|
||||||
|
* OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
|
||||||
|
* inactive. This in turn prevents the MPU DPLL from entering autoidle
|
||||||
|
* mode, so wakeup latency is greatly reduced, at the cost of additional
|
||||||
|
* energy consumption. This also prevents the CORE clockdomain from
|
||||||
|
* entering idle.
|
||||||
|
*/
|
||||||
|
#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Prevent PER OFF if CORE is not in RETention or OFF as this would
|
||||||
|
* disable PER wakeups completely.
|
||||||
|
*/
|
||||||
static struct omap3_idle_statedata omap3_idle_data[] = {
|
static struct omap3_idle_statedata omap3_idle_data[] = {
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_ON,
|
.mpu_state = PWRDM_POWER_ON,
|
||||||
.core_state = PWRDM_POWER_ON,
|
.core_state = PWRDM_POWER_ON,
|
||||||
|
/* In C1 do not allow PER state lower than CORE state */
|
||||||
|
.per_min_state = PWRDM_POWER_ON,
|
||||||
|
.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_ON,
|
.mpu_state = PWRDM_POWER_ON,
|
||||||
.core_state = PWRDM_POWER_ON,
|
.core_state = PWRDM_POWER_ON,
|
||||||
|
.per_min_state = PWRDM_POWER_RET,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_RET,
|
.mpu_state = PWRDM_POWER_RET,
|
||||||
.core_state = PWRDM_POWER_ON,
|
.core_state = PWRDM_POWER_ON,
|
||||||
|
.per_min_state = PWRDM_POWER_RET,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_OFF,
|
.mpu_state = PWRDM_POWER_OFF,
|
||||||
.core_state = PWRDM_POWER_ON,
|
.core_state = PWRDM_POWER_ON,
|
||||||
|
.per_min_state = PWRDM_POWER_RET,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_RET,
|
.mpu_state = PWRDM_POWER_RET,
|
||||||
.core_state = PWRDM_POWER_RET,
|
.core_state = PWRDM_POWER_RET,
|
||||||
|
.per_min_state = PWRDM_POWER_OFF,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_OFF,
|
.mpu_state = PWRDM_POWER_OFF,
|
||||||
.core_state = PWRDM_POWER_RET,
|
.core_state = PWRDM_POWER_RET,
|
||||||
|
.per_min_state = PWRDM_POWER_OFF,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.mpu_state = PWRDM_POWER_OFF,
|
.mpu_state = PWRDM_POWER_OFF,
|
||||||
.core_state = PWRDM_POWER_OFF,
|
.core_state = PWRDM_POWER_OFF,
|
||||||
|
.per_min_state = PWRDM_POWER_OFF,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -80,27 +106,25 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||||
int index)
|
int index)
|
||||||
{
|
{
|
||||||
struct omap3_idle_statedata *cx = &omap3_idle_data[index];
|
struct omap3_idle_statedata *cx = &omap3_idle_data[index];
|
||||||
u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
|
|
||||||
|
|
||||||
local_fiq_disable();
|
local_fiq_disable();
|
||||||
|
|
||||||
pwrdm_set_next_pwrst(mpu_pd, mpu_state);
|
|
||||||
pwrdm_set_next_pwrst(core_pd, core_state);
|
|
||||||
|
|
||||||
if (omap_irq_pending() || need_resched())
|
if (omap_irq_pending() || need_resched())
|
||||||
goto return_sleep_time;
|
goto return_sleep_time;
|
||||||
|
|
||||||
/* Deny idle for C1 */
|
/* Deny idle for C1 */
|
||||||
if (index == 0) {
|
if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
|
||||||
clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
|
clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
|
||||||
clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
|
} else {
|
||||||
|
pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
|
||||||
|
pwrdm_set_next_pwrst(core_pd, cx->core_state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Call idle CPU PM enter notifier chain so that
|
* Call idle CPU PM enter notifier chain so that
|
||||||
* VFP context is saved.
|
* VFP context is saved.
|
||||||
*/
|
*/
|
||||||
if (mpu_state == PWRDM_POWER_OFF)
|
if (cx->mpu_state == PWRDM_POWER_OFF)
|
||||||
cpu_pm_enter();
|
cpu_pm_enter();
|
||||||
|
|
||||||
/* Execute ARM wfi */
|
/* Execute ARM wfi */
|
||||||
|
|
@ -110,17 +134,15 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||||
* Call idle CPU PM enter notifier chain to restore
|
* Call idle CPU PM enter notifier chain to restore
|
||||||
* VFP context.
|
* VFP context.
|
||||||
*/
|
*/
|
||||||
if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
|
if (cx->mpu_state == PWRDM_POWER_OFF &&
|
||||||
|
pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
|
||||||
cpu_pm_exit();
|
cpu_pm_exit();
|
||||||
|
|
||||||
/* Re-allow idle for C1 */
|
/* Re-allow idle for C1 */
|
||||||
if (index == 0) {
|
if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
|
||||||
clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
|
clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
|
||||||
clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
|
|
||||||
}
|
|
||||||
|
|
||||||
return_sleep_time:
|
return_sleep_time:
|
||||||
|
|
||||||
local_fiq_enable();
|
local_fiq_enable();
|
||||||
|
|
||||||
return index;
|
return index;
|
||||||
|
|
@ -185,7 +207,7 @@ static int next_valid_state(struct cpuidle_device *dev,
|
||||||
* Start search from the next (lower) state.
|
* Start search from the next (lower) state.
|
||||||
*/
|
*/
|
||||||
for (idx = index - 1; idx >= 0; idx--) {
|
for (idx = index - 1; idx >= 0; idx--) {
|
||||||
cx = &omap3_idle_data[idx];
|
cx = &omap3_idle_data[idx];
|
||||||
if ((cx->mpu_state >= mpu_deepest_state) &&
|
if ((cx->mpu_state >= mpu_deepest_state) &&
|
||||||
(cx->core_state >= core_deepest_state)) {
|
(cx->core_state >= core_deepest_state)) {
|
||||||
next_index = idx;
|
next_index = idx;
|
||||||
|
|
@ -209,10 +231,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
||||||
struct cpuidle_driver *drv,
|
struct cpuidle_driver *drv,
|
||||||
int index)
|
int index)
|
||||||
{
|
{
|
||||||
int new_state_idx;
|
int new_state_idx, ret;
|
||||||
u32 core_next_state, per_next_state = 0, per_saved_state = 0;
|
u8 per_next_state, per_saved_state;
|
||||||
struct omap3_idle_statedata *cx;
|
struct omap3_idle_statedata *cx;
|
||||||
int ret;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Use only C1 if CAM is active.
|
* Use only C1 if CAM is active.
|
||||||
|
|
@ -233,25 +254,13 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
||||||
|
|
||||||
/* Program PER state */
|
/* Program PER state */
|
||||||
cx = &omap3_idle_data[new_state_idx];
|
cx = &omap3_idle_data[new_state_idx];
|
||||||
core_next_state = cx->core_state;
|
|
||||||
per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
|
|
||||||
if (new_state_idx == 0) {
|
|
||||||
/* In C1 do not allow PER state lower than CORE state */
|
|
||||||
if (per_next_state < core_next_state)
|
|
||||||
per_next_state = core_next_state;
|
|
||||||
} else {
|
|
||||||
/*
|
|
||||||
* Prevent PER OFF if CORE is not in RETention or OFF as this
|
|
||||||
* would disable PER wakeups completely.
|
|
||||||
*/
|
|
||||||
if ((per_next_state == PWRDM_POWER_OFF) &&
|
|
||||||
(core_next_state > PWRDM_POWER_RET))
|
|
||||||
per_next_state = PWRDM_POWER_RET;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Are we changing PER target state? */
|
per_next_state = pwrdm_read_next_pwrst(per_pd);
|
||||||
if (per_next_state != per_saved_state)
|
per_saved_state = per_next_state;
|
||||||
|
if (per_next_state < cx->per_min_state) {
|
||||||
|
per_next_state = cx->per_min_state;
|
||||||
pwrdm_set_next_pwrst(per_pd, per_next_state);
|
pwrdm_set_next_pwrst(per_pd, per_next_state);
|
||||||
|
}
|
||||||
|
|
||||||
ret = omap3_enter_idle(dev, drv, new_state_idx);
|
ret = omap3_enter_idle(dev, drv, new_state_idx);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -62,8 +62,7 @@ static int __init omap3_l3_init(void)
|
||||||
if (!oh)
|
if (!oh)
|
||||||
pr_err("could not look up %s\n", oh_name);
|
pr_err("could not look up %s\n", oh_name);
|
||||||
|
|
||||||
pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
|
pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0);
|
||||||
NULL, 0, 0);
|
|
||||||
|
|
||||||
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
||||||
|
|
||||||
|
|
@ -97,8 +96,7 @@ static int __init omap4_l3_init(void)
|
||||||
pr_err("could not look up %s\n", oh_name);
|
pr_err("could not look up %s\n", oh_name);
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
|
pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0);
|
||||||
0, NULL, 0, 0);
|
|
||||||
|
|
||||||
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
||||||
|
|
||||||
|
|
@ -317,7 +315,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
|
||||||
keypad_data = sdp4430_keypad_data;
|
keypad_data = sdp4430_keypad_data;
|
||||||
|
|
||||||
pdev = omap_device_build(name, id, oh, keypad_data,
|
pdev = omap_device_build(name, id, oh, keypad_data,
|
||||||
sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
|
sizeof(struct omap4_keypad_platform_data));
|
||||||
|
|
||||||
if (IS_ERR(pdev)) {
|
if (IS_ERR(pdev)) {
|
||||||
WARN(1, "Can't build omap_device for %s:%s.\n",
|
WARN(1, "Can't build omap_device for %s:%s.\n",
|
||||||
|
|
@ -341,7 +339,7 @@ static inline void __init omap_init_mbox(void)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
|
pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
|
||||||
WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
|
WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
|
||||||
__func__, PTR_ERR(pdev));
|
__func__, PTR_ERR(pdev));
|
||||||
}
|
}
|
||||||
|
|
@ -381,7 +379,7 @@ static void __init omap_init_mcpdm(void)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
|
pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
|
||||||
WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
|
WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
@ -402,7 +400,7 @@ static void __init omap_init_dmic(void)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
|
pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
|
||||||
WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
|
WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
@ -428,8 +426,7 @@ static void __init omap_init_hdmi_audio(void)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev = omap_device_build("omap-hdmi-audio-dai",
|
pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0, 0);
|
||||||
-1, oh, NULL, 0, NULL, 0, 0);
|
|
||||||
WARN(IS_ERR(pdev),
|
WARN(IS_ERR(pdev),
|
||||||
"Can't build omap_device for omap-hdmi-audio-dai.\n");
|
"Can't build omap_device for omap-hdmi-audio-dai.\n");
|
||||||
|
|
||||||
|
|
@ -473,8 +470,7 @@ static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
|
||||||
}
|
}
|
||||||
|
|
||||||
spi_num++;
|
spi_num++;
|
||||||
pdev = omap_device_build(name, spi_num, oh, pdata,
|
pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata));
|
||||||
sizeof(*pdata), NULL, 0, 0);
|
|
||||||
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
|
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
|
||||||
name, oh->name);
|
name, oh->name);
|
||||||
kfree(pdata);
|
kfree(pdata);
|
||||||
|
|
@ -504,7 +500,7 @@ static void omap_init_rng(void)
|
||||||
if (!oh)
|
if (!oh)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
|
pdev = omap_device_build("omap_rng", -1, oh, NULL, 0);
|
||||||
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
|
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -733,8 +729,7 @@ static void __init omap_init_ocp2scp(void)
|
||||||
|
|
||||||
pdata->dev_cnt = dev_cnt;
|
pdata->dev_cnt = dev_cnt;
|
||||||
|
|
||||||
pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL,
|
pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
|
||||||
0, false);
|
|
||||||
if (IS_ERR(pdev)) {
|
if (IS_ERR(pdev)) {
|
||||||
pr_err("Could not build omap_device for %s %s\n",
|
pr_err("Could not build omap_device for %s %s\n",
|
||||||
name, oh_name);
|
name, oh_name);
|
||||||
|
|
|
||||||
|
|
@ -226,7 +226,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name,
|
||||||
dev_set_name(&pdev->dev, "%s", pdev->name);
|
dev_set_name(&pdev->dev, "%s", pdev->name);
|
||||||
|
|
||||||
ohs[0] = oh;
|
ohs[0] = oh;
|
||||||
od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
|
od = omap_device_alloc(pdev, ohs, 1);
|
||||||
if (IS_ERR(od)) {
|
if (IS_ERR(od)) {
|
||||||
pr_err("Could not alloc omap_device for %s\n", pdev_name);
|
pr_err("Could not alloc omap_device for %s\n", pdev_name);
|
||||||
r = -ENOMEM;
|
r = -ENOMEM;
|
||||||
|
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue