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Pin control fixes for v3.15: 

- Signedness bug in the TB10x
 
 - GPIO inversion fix for the AS3722
 
 - Clear pending pin interrups enabled in the bootloader in the
   pinctrl-single driver
 
 - Minor pin definition fixes for the PFC/Renesas driver
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Merge tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Here is a small set of pin control fixes for the v3.15 series.  All
  are individual driver fixes and quite self-contained.  One of them
  tagged for stable.

   - Signedness bug in the TB10x

   - GPIO inversion fix for the AS3722

   - Clear pending pin interrups enabled in the bootloader in the
     pinctrl-single driver

   - Minor pin definition fixes for the PFC/Renesas driver"

* tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  sh-pfc: r8a7791: Fix definition of MOD_SEL3
  sh-pfc: r8a7790: Fix definition of IPSR5
  pinctrl: single: Clear pin interrupts enabled by bootloader
  pinctrl: as3722: fix handling of GPIO invert bit
  pinctrl/TB10x: Fix signedness bug
This commit is contained in:
Linus Torvalds 2014-05-01 11:28:03 -07:00
parent 60b88f3941 0c66c5628b
commit ba6728f596
5 changed files with 27 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/pinctrl/pinctrl-as3722.c
View File

@ -64,7 +64,6 @@ struct as3722_pin_function {
};
struct as3722_gpio_pin_control {
bool enable_gpio_invert;
unsigned mode_prop;
int io_function;
};
@ -320,10 +319,8 @@ static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
return mode;
}
if (as_pci->gpio_control[offset].enable_gpio_invert)
mode |= AS3722_GPIO_INV;
return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode);
return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
AS3722_GPIO_MODE_MASK, mode);
}
static const struct pinmux_ops as3722_pinmux_ops = {
@ -496,10 +493,18 @@ static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
{
struct as3722_pctrl_info *as_pci = to_as_pci(chip);
struct as3722 *as3722 = as_pci->as3722;
int en_invert = as_pci->gpio_control[offset].enable_gpio_invert;
int en_invert;
u32 val;
int ret;
ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
if (ret < 0) {
dev_err(as_pci->dev,
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
return;
}
en_invert = !!(val & AS3722_GPIO_INV);
if (value)
val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
else

13
drivers/pinctrl/pinctrl-single.c
View File

@ -810,6 +810,7 @@ static const struct pinconf_ops pcs_pinconf_ops = {
static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
unsigned pin_pos)
{
struct pcs_soc_data *pcs_soc = &pcs->socdata;
struct pinctrl_pin_desc *pin;
struct pcs_name *pn;
int i;
@ -821,6 +822,18 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
return -ENOMEM;
}
if (pcs_soc->irq_enable_mask) {
unsigned val;
val = pcs->read(pcs->base + offset);
if (val & pcs_soc->irq_enable_mask) {
dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
(unsigned long)pcs->res->start + offset, val);
val &= ~pcs_soc->irq_enable_mask;
pcs->write(val, pcs->base + offset);
}
}
pin = &pcs->pins.pa[i];
pn = &pcs->names[i];
sprintf(pn->name, "%lx.%d",

3
drivers/pinctrl/pinctrl-tb10x.c
View File

@ -629,9 +629,8 @@ static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
*/
for (i = 0; i < state->pinfuncgrpcnt; i++) {
const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
unsigned int port = pfg->port;
unsigned int mode = pfg->mode;
int j;
int j, port = pfg->port;
/*
* Skip pin groups which are always mapped and don't need

3
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -4794,8 +4794,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MSIOF0_SCK_B, 0,
/* IP5_23_21 [3] */
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
FN_IERX_C, 0,
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
/* IP5_20_18 [3] */
FN_WE0_N, FN_IECLK, FN_CAN_CLK,
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,

2
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -5288,7 +5288,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIF3 [2] */
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_MMC [1] */
FN_SEL_MMC_0, FN_SEL_MMC_1,
/* SEL_SCIF5 [1] */