powerpc/32: replace LOAD_MSR_KERNEL() by LOAD_REG_IMMEDIATE()
LOAD_MSR_KERNEL() and LOAD_REG_IMMEDIATE() are doing the same thing in the same way. Drop LOAD_MSR_KERNEL() Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/8f04a6df0bc8949517fd8236d50c15008ccf9231.1566311636.git.christophe.leroy@c-s.fr
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
c691b4b83b
commit
ba18025fb0
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@ -230,7 +230,7 @@ transfer_to_handler_cont:
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*/
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lis r12,reenable_mmu@h
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ori r12,r12,reenable_mmu@l
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LOAD_MSR_KERNEL(r0, MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r0, MSR_KERNEL)
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mtspr SPRN_SRR0,r12
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mtspr SPRN_SRR1,r0
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SYNC
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@ -304,7 +304,7 @@ stack_ovf:
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addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
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lis r9,StackOverflow@ha
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addi r9,r9,StackOverflow@l
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LOAD_MSR_KERNEL(r10,MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
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#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
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mtspr SPRN_NRI, r0
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#endif
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@ -324,7 +324,7 @@ trace_syscall_entry_irq_off:
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bl trace_hardirqs_on
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/* Now enable for real */
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LOAD_MSR_KERNEL(r10, MSR_KERNEL | MSR_EE)
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LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
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mtmsr r10
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REST_GPR(0, r1)
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@ -394,7 +394,7 @@ ret_from_syscall:
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#endif
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mr r6,r3
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/* disable interrupts so current_thread_info()->flags can't change */
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LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
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/* Note: We don't bother telling lockdep about it */
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SYNC
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MTMSRD(r10)
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@ -824,7 +824,7 @@ ret_from_except:
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* can't change between when we test it and when we return
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* from the interrupt. */
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/* Note: We don't bother telling lockdep about it */
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LOAD_MSR_KERNEL(r10,MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
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SYNC /* Some chip revs have problems here... */
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MTMSRD(r10) /* disable interrupts */
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@ -991,7 +991,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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* can restart the exception exit path at the label
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* exc_exit_restart below. -- paulus
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*/
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LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
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SYNC
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MTMSRD(r10) /* clear the RI bit */
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.globl exc_exit_restart
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@ -1066,7 +1066,7 @@ exc_exit_restart_end:
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REST_NVGPRS(r1); \
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lwz r3,_MSR(r1); \
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andi. r3,r3,MSR_PR; \
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LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
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bne user_exc_return; \
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lwz r0,GPR0(r1); \
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lwz r2,GPR2(r1); \
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@ -1236,7 +1236,7 @@ recheck:
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* neither. Those disable/enable cycles used to peek at
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* TI_FLAGS aren't advertised.
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*/
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LOAD_MSR_KERNEL(r10,MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
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SYNC
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MTMSRD(r10) /* disable interrupts */
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lwz r9,TI_FLAGS(r2)
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@ -1329,7 +1329,7 @@ _GLOBAL(enter_rtas)
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lwz r4,RTASBASE(r4)
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mfmsr r9
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stw r9,8(r1)
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LOAD_MSR_KERNEL(r0,MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
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SYNC /* disable interrupts so SRR0/1 */
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MTMSRD(r0) /* don't get trashed */
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li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
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@ -4,19 +4,6 @@
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#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
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/*
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* MSR_KERNEL is > 0x8000 on 4xx/Book-E since it include MSR_CE.
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*/
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.macro __LOAD_MSR_KERNEL r, x
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.if \x >= 0x8000
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lis \r, (\x)@h
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ori \r, \r, (\x)@l
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.else
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li \r, (\x)
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.endif
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.endm
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#define LOAD_MSR_KERNEL(r, x) __LOAD_MSR_KERNEL r, x
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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@ -92,7 +79,7 @@
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#ifdef CONFIG_40x
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rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
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#else
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LOAD_MSR_KERNEL(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */
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LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */
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MTMSRD(r10) /* (except for mach check in rtas) */
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#endif
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lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
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@ -140,10 +127,10 @@
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* otherwise we might risk taking an interrupt before we tell lockdep
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* they are enabled.
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*/
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LOAD_MSR_KERNEL(r10, MSR_KERNEL)
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LOAD_REG_IMMEDIATE(r10, MSR_KERNEL)
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rlwimi r10, r9, 0, MSR_EE
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#else
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LOAD_MSR_KERNEL(r10, MSR_KERNEL | MSR_EE)
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LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
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#endif
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#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
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mtspr SPRN_NRI, r0
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@ -187,7 +174,7 @@ label:
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#define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \
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li r10,trap; \
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stw r10,_TRAP(r11); \
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LOAD_MSR_KERNEL(r10, msr); \
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LOAD_REG_IMMEDIATE(r10, msr); \
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bl tfer; \
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.long hdlr; \
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.long ret
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