iommu/arm-smmu-v3: Clean up table definitions
As with registers, use GENMASK and the bitfield accessors consistently for table fields, to save some lines and ease maintenance a little. This also catches a subtle off-by-one wherein bit 5 of CD.T0SZ was missing. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
cbcee19ac4
commit
ba08bdcbf7
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@ -207,54 +207,46 @@
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#define STRTAB_SPLIT 8
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#define STRTAB_L1_DESC_DWORDS 1
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#define STRTAB_L1_DESC_SPAN_SHIFT 0
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#define STRTAB_L1_DESC_SPAN_MASK 0x1fUL
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#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
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#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(47, 6)
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#define STRTAB_STE_DWORDS 8
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#define STRTAB_STE_0_V (1UL << 0)
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#define STRTAB_STE_0_CFG_SHIFT 1
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#define STRTAB_STE_0_CFG_MASK 0x7UL
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#define STRTAB_STE_0_CFG_ABORT (0UL << STRTAB_STE_0_CFG_SHIFT)
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#define STRTAB_STE_0_CFG_BYPASS (4UL << STRTAB_STE_0_CFG_SHIFT)
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#define STRTAB_STE_0_CFG_S1_TRANS (5UL << STRTAB_STE_0_CFG_SHIFT)
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#define STRTAB_STE_0_CFG_S2_TRANS (6UL << STRTAB_STE_0_CFG_SHIFT)
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#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
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#define STRTAB_STE_0_CFG_ABORT 0
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#define STRTAB_STE_0_CFG_BYPASS 4
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#define STRTAB_STE_0_CFG_S1_TRANS 5
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#define STRTAB_STE_0_CFG_S2_TRANS 6
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#define STRTAB_STE_0_S1FMT_SHIFT 4
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#define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT)
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#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
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#define STRTAB_STE_0_S1FMT_LINEAR 0
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#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(47, 6)
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#define STRTAB_STE_0_S1CDMAX_SHIFT 59
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#define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL
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#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
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#define STRTAB_STE_1_S1C_CACHE_NC 0UL
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#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
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#define STRTAB_STE_1_S1C_CACHE_WT 2UL
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#define STRTAB_STE_1_S1C_CACHE_WB 3UL
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#define STRTAB_STE_1_S1C_SH_NSH 0UL
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#define STRTAB_STE_1_S1C_SH_OSH 2UL
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#define STRTAB_STE_1_S1C_SH_ISH 3UL
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#define STRTAB_STE_1_S1CIR_SHIFT 2
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#define STRTAB_STE_1_S1COR_SHIFT 4
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#define STRTAB_STE_1_S1CSH_SHIFT 6
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#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2)
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#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4)
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#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6)
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#define STRTAB_STE_1_S1STALLD (1UL << 27)
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#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28)
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#define STRTAB_STE_1_EATS_ABT 0UL
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#define STRTAB_STE_1_EATS_TRANS 1UL
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#define STRTAB_STE_1_EATS_S1CHK 2UL
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#define STRTAB_STE_1_EATS_SHIFT 28
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#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30)
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#define STRTAB_STE_1_STRW_NSEL1 0UL
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#define STRTAB_STE_1_STRW_EL2 2UL
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#define STRTAB_STE_1_STRW_SHIFT 30
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#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44)
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#define STRTAB_STE_1_SHCFG_INCOMING 1UL
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#define STRTAB_STE_1_SHCFG_SHIFT 44
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#define STRTAB_STE_2_S2VMID_SHIFT 0
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#define STRTAB_STE_2_S2VMID_MASK 0xffffUL
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#define STRTAB_STE_2_VTCR_SHIFT 32
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#define STRTAB_STE_2_VTCR_MASK 0x7ffffUL
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#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0)
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#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)
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#define STRTAB_STE_2_S2AA64 (1UL << 51)
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#define STRTAB_STE_2_S2ENDI (1UL << 52)
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#define STRTAB_STE_2_S2PTW (1UL << 54)
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@ -264,56 +256,41 @@
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/* Context descriptor (stage-1 only) */
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#define CTXDESC_CD_DWORDS 8
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#define CTXDESC_CD_0_TCR_T0SZ_SHIFT 0
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#define ARM64_TCR_T0SZ_SHIFT 0
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#define ARM64_TCR_T0SZ_MASK 0x1fUL
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#define CTXDESC_CD_0_TCR_TG0_SHIFT 6
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#define ARM64_TCR_TG0_SHIFT 14
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#define ARM64_TCR_TG0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
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#define ARM64_TCR_IRGN0_SHIFT 8
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#define ARM64_TCR_IRGN0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
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#define ARM64_TCR_ORGN0_SHIFT 10
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#define ARM64_TCR_ORGN0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_SH0_SHIFT 12
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#define ARM64_TCR_SH0_SHIFT 12
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#define ARM64_TCR_SH0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_EPD0_SHIFT 14
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#define ARM64_TCR_EPD0_SHIFT 7
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#define ARM64_TCR_EPD0_MASK 0x1UL
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#define CTXDESC_CD_0_TCR_EPD1_SHIFT 30
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#define ARM64_TCR_EPD1_SHIFT 23
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#define ARM64_TCR_EPD1_MASK 0x1UL
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#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
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#define ARM64_TCR_T0SZ GENMASK_ULL(5, 0)
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#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
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#define ARM64_TCR_TG0 GENMASK_ULL(15, 14)
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#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
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#define ARM64_TCR_IRGN0 GENMASK_ULL(9, 8)
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#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
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#define ARM64_TCR_ORGN0 GENMASK_ULL(11, 10)
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#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12)
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#define ARM64_TCR_SH0 GENMASK_ULL(13, 12)
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#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14)
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#define ARM64_TCR_EPD0 (1ULL << 7)
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#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30)
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#define ARM64_TCR_EPD1 (1ULL << 23)
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#define CTXDESC_CD_0_ENDI (1UL << 15)
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#define CTXDESC_CD_0_V (1UL << 31)
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#define CTXDESC_CD_0_TCR_IPS_SHIFT 32
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#define ARM64_TCR_IPS_SHIFT 32
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#define ARM64_TCR_IPS_MASK 0x7UL
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#define CTXDESC_CD_0_TCR_TBI0_SHIFT 38
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#define ARM64_TCR_TBI0_SHIFT 37
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#define ARM64_TCR_TBI0_MASK 0x1UL
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#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)
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#define ARM64_TCR_IPS GENMASK_ULL(34, 32)
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#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38)
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#define ARM64_TCR_TBI0 (1ULL << 37)
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#define CTXDESC_CD_0_AA64 (1UL << 41)
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#define CTXDESC_CD_0_S (1UL << 44)
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#define CTXDESC_CD_0_R (1UL << 45)
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#define CTXDESC_CD_0_A (1UL << 46)
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#define CTXDESC_CD_0_ASET_SHIFT 47
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#define CTXDESC_CD_0_ASET_SHARED (0UL << CTXDESC_CD_0_ASET_SHIFT)
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#define CTXDESC_CD_0_ASET_PRIVATE (1UL << CTXDESC_CD_0_ASET_SHIFT)
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#define CTXDESC_CD_0_ASID_SHIFT 48
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#define CTXDESC_CD_0_ASID_MASK 0xffffUL
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#define CTXDESC_CD_0_ASET (1UL << 47)
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#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
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#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(47, 4)
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#define CTXDESC_CD_3_MAIR_SHIFT 0
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/* Convert between AArch64 (CPU) TCR format and SMMU CD format */
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#define ARM_SMMU_TCR2CD(tcr, fld) \
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(((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK) \
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<< CTXDESC_CD_0_TCR_##fld##_SHIFT)
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#define ARM_SMMU_TCR2CD(tcr, fld) FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \
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FIELD_GET(ARM64_TCR_##fld, tcr))
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/* Command queue */
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#define CMDQ_ENT_DWORDS 2
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@ -1060,8 +1037,8 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
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#ifdef __BIG_ENDIAN
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CTXDESC_CD_0_ENDI |
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#endif
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CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
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CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
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CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
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CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cfg->cd.asid) |
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CTXDESC_CD_0_V;
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/* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */
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@ -1073,7 +1050,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
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val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK;
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cfg->cdptr[1] = cpu_to_le64(val);
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cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);
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cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair);
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}
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/* Stream table manipulation functions */
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@ -1082,8 +1059,7 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
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{
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u64 val = 0;
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val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK)
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<< STRTAB_L1_DESC_SPAN_SHIFT;
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val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span);
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val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
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*dst = cpu_to_le64(val);
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@ -1132,10 +1108,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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};
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if (val & STRTAB_STE_0_V) {
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u64 cfg;
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cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT;
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switch (cfg) {
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switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {
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case STRTAB_STE_0_CFG_BYPASS:
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break;
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case STRTAB_STE_0_CFG_S1_TRANS:
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@ -1156,13 +1129,13 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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/* Bypass/fault */
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if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) {
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if (!ste->assigned && disable_bypass)
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val |= STRTAB_STE_0_CFG_ABORT;
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
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else
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val |= STRTAB_STE_0_CFG_BYPASS;
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
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dst[0] = cpu_to_le64(val);
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dst[1] = cpu_to_le64(STRTAB_STE_1_SHCFG_INCOMING
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<< STRTAB_STE_1_SHCFG_SHIFT);
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dst[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
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STRTAB_STE_1_SHCFG_INCOMING));
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dst[2] = 0; /* Nuke the VMID */
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/*
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* The SMMU can perform negative caching, so we must sync
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@ -1176,40 +1149,36 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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if (ste->s1_cfg) {
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BUG_ON(ste_live);
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dst[1] = cpu_to_le64(
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STRTAB_STE_1_S1C_CACHE_WBRA
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<< STRTAB_STE_1_S1CIR_SHIFT |
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STRTAB_STE_1_S1C_CACHE_WBRA
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<< STRTAB_STE_1_S1COR_SHIFT |
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STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
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FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
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#ifdef CONFIG_PCI_ATS
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STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
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FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_TRANS) |
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#endif
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STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
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FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1));
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if (smmu->features & ARM_SMMU_FEAT_STALLS &&
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!(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
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dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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STRTAB_STE_0_CFG_S1_TRANS;
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FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS);
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}
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if (ste->s2_cfg) {
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BUG_ON(ste_live);
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dst[2] = cpu_to_le64(
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ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT |
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(ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK)
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<< STRTAB_STE_2_VTCR_SHIFT |
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FIELD_PREP(STRTAB_STE_2_S2VMID, ste->s2_cfg->vmid) |
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FIELD_PREP(STRTAB_STE_2_VTCR, ste->s2_cfg->vtcr) |
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#ifdef __BIG_ENDIAN
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STRTAB_STE_2_S2ENDI |
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#endif
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STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
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STRTAB_STE_2_S2R);
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dst[3] = cpu_to_le64(ste->s2_cfg->vttbr &
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STRTAB_STE_3_S2TTB_MASK);
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dst[3] = cpu_to_le64(ste->s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
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val |= STRTAB_STE_0_CFG_S2_TRANS;
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val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
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}
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arm_smmu_sync_ste_for_sid(smmu, sid);
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