MTD: Nand: Add JZ4740 NAND driver
Add support for the NAND controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1470/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Lars-Peter Clausen
Ralf Baechle
parent
7a92d54521
commit
ba01d6ec04
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC NAND controller driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
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#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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struct jz_nand_platform_data {
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int num_partitions;
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struct mtd_partition *partitions;
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struct nand_ecclayout *ecc_layout;
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unsigned int busy_gpio;
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void (*ident_callback)(struct platform_device *, struct nand_chip *,
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struct mtd_partition **, int *num_partitions);
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};
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#endif
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@ -526,4 +526,10 @@ config MTD_NAND_NUC900
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This enables the driver for the NAND Flash on evaluation board based
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on w90p910 / NUC9xx.
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config MTD_NAND_JZ4740
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tristate "Support for JZ4740 SoC NAND controller"
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depends on MACH_JZ4740
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help
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Enables support for NAND Flash on JZ4740 SoC based boards.
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endif # MTD_NAND
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@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
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obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
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obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
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obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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nand-objs := nand_base.o nand_bbt.o
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@ -0,0 +1,516 @@
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC NAND controller driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/gpio.h>
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#include <asm/mach-jz4740/jz4740_nand.h>
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#define JZ_REG_NAND_CTRL 0x50
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#define JZ_REG_NAND_ECC_CTRL 0x100
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#define JZ_REG_NAND_DATA 0x104
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#define JZ_REG_NAND_PAR0 0x108
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#define JZ_REG_NAND_PAR1 0x10C
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#define JZ_REG_NAND_PAR2 0x110
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#define JZ_REG_NAND_IRQ_STAT 0x114
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#define JZ_REG_NAND_IRQ_CTRL 0x118
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#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
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#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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#define JZ_NAND_ECC_CTRL_RS BIT(2)
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#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
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#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
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#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
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#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
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#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
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#define JZ_NAND_STATUS_ERROR BIT(0)
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#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
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#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
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#define JZ_NAND_MEM_CMD_OFFSET 0x08000
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struct jz_nand {
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struct mtd_info mtd;
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struct nand_chip chip;
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void __iomem *base;
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struct resource *mem;
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void __iomem *bank_base;
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struct resource *bank_mem;
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struct jz_nand_platform_data *pdata;
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bool is_reading;
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};
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static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
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{
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return container_of(mtd, struct jz_nand, mtd);
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}
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static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t reg;
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if (ctrl & NAND_CTRL_CHANGE) {
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BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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if (ctrl & NAND_ALE)
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chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
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else if (ctrl & NAND_CLE)
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chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
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else
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chip->IO_ADDR_W = nand->bank_base;
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reg = readl(nand->base + JZ_REG_NAND_CTRL);
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if (ctrl & NAND_NCE)
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reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
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else
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reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
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writel(reg, nand->base + JZ_REG_NAND_CTRL);
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat, chip->IO_ADDR_W);
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}
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static int jz_nand_dev_ready(struct mtd_info *mtd)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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return gpio_get_value_cansleep(nand->pdata->busy_gpio);
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}
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static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg;
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writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_RESET;
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reg |= JZ_NAND_ECC_CTRL_ENABLE;
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reg |= JZ_NAND_ECC_CTRL_RS;
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switch (mode) {
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case NAND_ECC_READ:
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = true;
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break;
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case NAND_ECC_WRITE:
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reg |= JZ_NAND_ECC_CTRL_ENCODING;
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nand->is_reading = false;
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break;
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default:
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break;
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}
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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}
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static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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uint32_t reg, status;
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int i;
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unsigned int timeout = 1000;
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static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
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0x8b, 0xff, 0xb7, 0x6f};
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if (nand->is_reading)
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return 0;
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
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if (timeout == 0)
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return -1;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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for (i = 0; i < 9; ++i)
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ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
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/* If the written data is completly 0xff, we also want to write 0xff as
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* ecc, otherwise we will get in trouble when doing subpage writes. */
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if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
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memset(ecc_code, 0xff, 9);
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return 0;
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}
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static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
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{
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int offset = index & 0x7;
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uint16_t data;
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index += (index >> 3);
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data = dat[index];
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data |= dat[index+1] << 8;
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mask ^= (data >> offset) & 0x1ff;
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data &= ~(0x1ff << offset);
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data |= (mask << offset);
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dat[index] = data & 0xff;
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dat[index+1] = (data >> 8) & 0xff;
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}
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static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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int i, error_count, index;
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uint32_t reg, status, error;
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uint32_t t;
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unsigned int timeout = 1000;
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t = read_ecc[0];
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if (t == 0xff) {
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for (i = 1; i < 9; ++i)
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t &= read_ecc[i];
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t &= dat[0];
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t &= dat[nand->chip.ecc.size / 2];
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t &= dat[nand->chip.ecc.size - 1];
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if (t == 0xff) {
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for (i = 1; i < nand->chip.ecc.size - 1; ++i)
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t &= dat[i];
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if (t == 0xff)
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return 0;
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}
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}
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for (i = 0; i < 9; ++i)
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writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg |= JZ_NAND_ECC_CTRL_PAR_READY;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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do {
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status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
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if (timeout == 0)
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return -1;
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reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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if (status & JZ_NAND_STATUS_ERROR) {
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if (status & JZ_NAND_STATUS_UNCOR_ERROR)
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return -1;
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error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
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for (i = 0; i < error_count; ++i) {
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error = readl(nand->base + JZ_REG_NAND_ERR(i));
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index = ((error >> 16) & 0x1ff) - 1;
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if (index >= 0 && index < 512)
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jz_nand_correct_data(dat, index, error & 0x1ff);
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}
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return error_count;
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}
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return 0;
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}
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/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos
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* handling. The ecc area is for 4k chips 72 bytes long and thus does not fit
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* into the eccpos array. */
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static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
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struct nand_chip *chip, uint8_t *buf, int page)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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unsigned int ecc_offset = chip->page_shift;
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/* Read the OOB area first */
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chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
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for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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int stat;
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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chip->read_buf(mtd, p, eccsize);
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stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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}
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return 0;
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}
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/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */
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static void jz_nand_write_page_hwecc(struct mtd_info *mtd,
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struct nand_chip *chip, const uint8_t *buf)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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const uint8_t *p = buf;
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unsigned int ecc_offset = chip->page_shift;
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for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
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chip->write_buf(mtd, p, eccsize);
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chip->ecc.calculate(mtd, p, &chip->oob_poi[i]);
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}
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chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
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}
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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static const char *part_probes[] = {"cmdline", NULL};
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#endif
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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const char *name, struct resource **res, void __iomem **base)
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{
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int ret;
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*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
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ret = -ENXIO;
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goto err;
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}
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*res = request_mem_region((*res)->start, resource_size(*res),
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pdev->name);
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if (!*res) {
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dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
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ret = -EBUSY;
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goto err;
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}
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*base = ioremap((*res)->start, resource_size(*res));
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if (!*base) {
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dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
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ret = -EBUSY;
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goto err_release_mem;
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}
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return 0;
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err_release_mem:
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release_mem_region((*res)->start, resource_size(*res));
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err:
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*res = NULL;
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*base = NULL;
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return ret;
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}
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static int __devinit jz_nand_probe(struct platform_device *pdev)
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{
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int ret;
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struct jz_nand *nand;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
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#ifdef CONFIG_MTD_PARTITIONS
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struct mtd_partition *partition_info;
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int num_partitions = 0;
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#endif
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nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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if (!nand) {
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dev_err(&pdev->dev, "Failed to allocate device structure.\n");
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return -ENOMEM;
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}
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ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
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if (ret)
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goto err_free;
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ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
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&nand->bank_base);
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if (ret)
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goto err_iounmap_mmio;
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|
||||
if (pdata && gpio_is_valid(pdata->busy_gpio)) {
|
||||
ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to request busy gpio %d: %d\n",
|
||||
pdata->busy_gpio, ret);
|
||||
goto err_iounmap_mem;
|
||||
}
|
||||
}
|
||||
|
||||
mtd = &nand->mtd;
|
||||
chip = &nand->chip;
|
||||
mtd->priv = chip;
|
||||
mtd->owner = THIS_MODULE;
|
||||
mtd->name = "jz4740-nand";
|
||||
|
||||
chip->ecc.hwctl = jz_nand_hwctl;
|
||||
chip->ecc.calculate = jz_nand_calculate_ecc_rs;
|
||||
chip->ecc.correct = jz_nand_correct_ecc_rs;
|
||||
chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
||||
chip->ecc.size = 512;
|
||||
chip->ecc.bytes = 9;
|
||||
|
||||
chip->ecc.read_page = jz_nand_read_page_hwecc_oob_first;
|
||||
chip->ecc.write_page = jz_nand_write_page_hwecc;
|
||||
|
||||
if (pdata)
|
||||
chip->ecc.layout = pdata->ecc_layout;
|
||||
|
||||
chip->chip_delay = 50;
|
||||
chip->cmd_ctrl = jz_nand_cmd_ctrl;
|
||||
|
||||
if (pdata && gpio_is_valid(pdata->busy_gpio))
|
||||
chip->dev_ready = jz_nand_dev_ready;
|
||||
|
||||
chip->IO_ADDR_R = nand->bank_base;
|
||||
chip->IO_ADDR_W = nand->bank_base;
|
||||
|
||||
nand->pdata = pdata;
|
||||
platform_set_drvdata(pdev, nand);
|
||||
|
||||
writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
|
||||
|
||||
ret = nand_scan_ident(mtd, 1, NULL);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to scan nand\n");
|
||||
goto err_gpio_free;
|
||||
}
|
||||
|
||||
if (pdata && pdata->ident_callback) {
|
||||
pdata->ident_callback(pdev, chip, &pdata->partitions,
|
||||
&pdata->num_partitions);
|
||||
}
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to scan nand\n");
|
||||
goto err_gpio_free;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
#ifdef CONFIG_MTD_CMDLINE_PARTS
|
||||
num_partitions = parse_mtd_partitions(mtd, part_probes,
|
||||
&partition_info, 0);
|
||||
#endif
|
||||
if (num_partitions <= 0 && pdata) {
|
||||
num_partitions = pdata->num_partitions;
|
||||
partition_info = pdata->partitions;
|
||||
}
|
||||
|
||||
if (num_partitions > 0)
|
||||
ret = add_mtd_partitions(mtd, partition_info, num_partitions);
|
||||
else
|
||||
#endif
|
||||
ret = add_mtd_device(mtd);
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to add mtd device\n");
|
||||
goto err_nand_release;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_nand_release:
|
||||
nand_release(&nand->mtd);
|
||||
err_gpio_free:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
gpio_free(pdata->busy_gpio);
|
||||
err_iounmap_mem:
|
||||
iounmap(nand->bank_base);
|
||||
err_iounmap_mmio:
|
||||
iounmap(nand->base);
|
||||
err_free:
|
||||
kfree(nand);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit jz_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz_nand *nand = platform_get_drvdata(pdev);
|
||||
|
||||
nand_release(&nand->mtd);
|
||||
|
||||
/* Deassert and disable all chips */
|
||||
writel(0, nand->base + JZ_REG_NAND_CTRL);
|
||||
|
||||
iounmap(nand->bank_base);
|
||||
release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
|
||||
iounmap(nand->base);
|
||||
release_mem_region(nand->mem->start, resource_size(nand->mem));
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
kfree(nand);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver jz_nand_driver = {
|
||||
.probe = jz_nand_probe,
|
||||
.remove = __devexit_p(jz_nand_remove),
|
||||
.driver = {
|
||||
.name = "jz4740-nand",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init jz_nand_init(void)
|
||||
{
|
||||
return platform_driver_register(&jz_nand_driver);
|
||||
}
|
||||
module_init(jz_nand_init);
|
||||
|
||||
static void __exit jz_nand_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&jz_nand_driver);
|
||||
}
|
||||
module_exit(jz_nand_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
||||
MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
|
||||
MODULE_ALIAS("platform:jz4740-nand");
|
||||
Loading…
Reference in New Issue