drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylake
Skylake doesn't use the pre-charge field now, but, instead, we need to specify the total number of SYNC pulses for the SYNC phase (pre-charge + SYNC pattern pules). Let's use the default value (32) for that. v3: increase DP AUX TX timeout as 400us is not to be used on SKL apparently (Jesse). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3634,6 +3634,7 @@ enum punit_power_well {
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#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
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#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
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#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
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#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
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/*
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* Computing GMCH M and N values for the Display Port link
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@ -701,6 +701,21 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}
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static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
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bool has_aux_irq,
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int send_bytes,
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uint32_t unused)
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{
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return DP_AUX_CH_CTL_SEND_BUSY |
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DP_AUX_CH_CTL_DONE |
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(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_TIME_OUT_1600us |
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DP_AUX_CH_CTL_RECEIVE_ERROR |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
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}
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static int
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intel_dp_aux_ch(struct intel_dp *intel_dp,
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uint8_t *send, int send_bytes,
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@ -5104,7 +5119,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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else
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intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
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intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
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if (INTEL_INFO(dev)->gen >= 9)
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intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
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else
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intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
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/* Preserve the current hw state. */
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intel_dp->DP = I915_READ(intel_dp->output_reg);
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