hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6

This commit is contained in:
Anton Altaparmakov 2005-09-12 09:05:41 -07:00
parent c324229138 f24ec7f6c6
commit b9791184e7
30 changed files with 800 additions and 288 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/ppc64/kernel/iSeries_pci.c
View File

@ -252,7 +252,7 @@ unsigned long __init find_and_init_phbs(void)
phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
if (phb == NULL)
return -ENOMEM;
pci_setup_pci_controller(phb);
pci_setup_pci_controller(phb);
phb->pci_mem_offset = phb->local_number = bus;
phb->first_busno = bus;

54
arch/ppc64/kernel/maple_pci.c
View File

@ -283,7 +283,7 @@ static void __init setup_u3_agp(struct pci_controller* hose)
* the reg address cell, we shall fix that by killing struct
* reg_property and using some accessor functions instead
*/
hose->first_busno = 0xf0;
hose->first_busno = 0xf0;
hose->last_busno = 0xff;
hose->ops = &u3_agp_pci_ops;
hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
@ -315,24 +315,24 @@ static int __init add_bridge(struct device_node *dev)
char* disp_name;
int *bus_range;
int primary = 1;
struct property *of_prop;
struct property *of_prop;
DBG("Adding PCI host bridge %s\n", dev->full_name);
bus_range = (int *) get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
dev->full_name);
}
bus_range = (int *) get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
dev->full_name);
}
hose = alloc_bootmem(sizeof(struct pci_controller));
if (hose == NULL)
return -ENOMEM;
pci_setup_pci_controller(hose);
pci_setup_pci_controller(hose);
hose->arch_data = dev;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
hose->arch_data = dev;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
of_prop = alloc_bootmem(sizeof(struct property) +
sizeof(hose->global_number));
@ -346,25 +346,25 @@ static int __init add_bridge(struct device_node *dev)
}
disp_name = NULL;
if (device_is_compatible(dev, "u3-agp")) {
setup_u3_agp(hose);
disp_name = "U3-AGP";
primary = 0;
} else if (device_is_compatible(dev, "u3-ht")) {
setup_u3_ht(hose);
disp_name = "U3-HT";
primary = 1;
}
printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
disp_name, hose->first_busno, hose->last_busno);
if (device_is_compatible(dev, "u3-agp")) {
setup_u3_agp(hose);
disp_name = "U3-AGP";
primary = 0;
} else if (device_is_compatible(dev, "u3-ht")) {
setup_u3_ht(hose);
disp_name = "U3-HT";
primary = 1;
}
printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
disp_name, hose->first_busno, hose->last_busno);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev);
pci_setup_phb_io(hose, primary);
/* Fixup "bus-range" OF property */
fixup_bus_range(dev);
/* Fixup "bus-range" OF property */
fixup_bus_range(dev);
return 0;
}

8
arch/ppc64/kernel/pSeries_setup.c
View File

@ -590,6 +590,13 @@ static int pseries_shared_idle(void)
return 0;
}
static int pSeries_pci_probe_mode(struct pci_bus *bus)
{
if (systemcfg->platform & PLATFORM_LPAR)
return PCI_PROBE_DEVTREE;
return PCI_PROBE_NORMAL;
}
struct machdep_calls __initdata pSeries_md = {
.probe = pSeries_probe,
.setup_arch = pSeries_setup_arch,
@ -597,6 +604,7 @@ struct machdep_calls __initdata pSeries_md = {
.get_cpuinfo = pSeries_get_cpuinfo,
.log_error = pSeries_log_error,
.pcibios_fixup = pSeries_final_fixup,
.pci_probe_mode = pSeries_pci_probe_mode,
.irq_bus_setup = pSeries_irq_bus_setup,
.restart = rtas_restart,
.power_off = rtas_power_off,

13
arch/ppc64/kernel/pSeries_smp.c
View File

@ -272,6 +272,7 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu)
unsigned long start_here = __pa((u32)*((unsigned long *)
pSeries_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
if (cpu_isset(lcpu, of_spin_map))
/* Already started by OF and sitting in spin loop */
@ -282,12 +283,20 @@ static inline int __devinit smp_startup_cpu(unsigned int lcpu)
/* Fixup atomic count: it exited inside IRQ handler. */
paca[lcpu].__current->thread_info->preempt_count = 0;
status = rtas_call(rtas_token("start-cpu"), 3, 1, NULL,
pcpu, start_here, lcpu);
/*
* If the RTAS start-cpu token does not exist then presume the
* cpu is already spinning.
*/
start_cpu = rtas_token("start-cpu");
if (start_cpu == RTAS_UNKNOWN_SERVICE)
return 1;
status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, lcpu);
if (status != 0) {
printk(KERN_ERR "start-cpu failed: %i\n", status);
return 0;
}
return 1;
}

429
arch/ppc64/kernel/pci.c
View File

@ -51,6 +51,10 @@ unsigned long io_page_mask;
EXPORT_SYMBOL(io_page_mask);
#ifdef CONFIG_PPC_MULTIPLATFORM
static void fixup_resource(struct resource *res, struct pci_dev *dev);
static void do_bus_setup(struct pci_bus *bus);
#endif
unsigned int pcibios_assign_all_busses(void)
{
@ -225,10 +229,287 @@ static void __init pcibios_claim_of_setup(void)
}
#endif
#ifdef CONFIG_PPC_MULTIPLATFORM
static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
{
u32 *prop;
int len;
prop = (u32 *) get_property(np, name, &len);
if (prop && len >= 4)
return *prop;
return def;
}
static unsigned int pci_parse_of_flags(u32 addr0)
{
unsigned int flags = 0;
if (addr0 & 0x02000000) {
flags |= IORESOURCE_MEM;
if (addr0 & 0x40000000)
flags |= IORESOURCE_PREFETCH;
} else if (addr0 & 0x01000000)
flags |= IORESOURCE_IO;
return flags;
}
#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
{
u64 base, size;
unsigned int flags;
struct resource *res;
u32 *addrs, i;
int proplen;
addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
if (!addrs)
return;
for (; proplen >= 20; proplen -= 20, addrs += 5) {
flags = pci_parse_of_flags(addrs[0]);
if (!flags)
continue;
base = GET_64BIT(addrs, 1);
size = GET_64BIT(addrs, 3);
if (!size)
continue;
i = addrs[0] & 0xff;
if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
} else if (i == dev->rom_base_reg) {
res = &dev->resource[PCI_ROM_RESOURCE];
flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
} else {
printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
continue;
}
res->start = base;
res->end = base + size - 1;
res->flags = flags;
res->name = pci_name(dev);
fixup_resource(res, dev);
}
}
static struct pci_dev *of_create_pci_dev(struct device_node *node,
struct pci_bus *bus, int devfn)
{
struct pci_dev *dev;
const char *type;
dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
if (!dev)
return NULL;
type = get_property(node, "device_type", NULL);
if (type == NULL)
type = "";
memset(dev, 0, sizeof(struct pci_dev));
dev->bus = bus;
dev->sysdata = node;
dev->dev.parent = bus->bridge;
dev->dev.bus = &pci_bus_type;
dev->devfn = devfn;
dev->multifunction = 0; /* maybe a lie? */
dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
dev->device = get_int_prop(node, "device-id", 0xffff);
dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
dev->class = get_int_prop(node, "class-code", 0);
dev->current_state = 4; /* unknown power state */
if (!strcmp(type, "pci")) {
/* a PCI-PCI bridge */
dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
dev->rom_base_reg = PCI_ROM_ADDRESS1;
} else if (!strcmp(type, "cardbus")) {
dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
} else {
dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
dev->rom_base_reg = PCI_ROM_ADDRESS;
dev->irq = NO_IRQ;
if (node->n_intrs > 0) {
dev->irq = node->intrs[0].line;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
dev->irq);
}
}
pci_parse_of_addrs(node, dev);
pci_device_add(dev, bus);
/* XXX pci_scan_msi_device(dev); */
return dev;
}
static void of_scan_pci_bridge(struct device_node *node, struct pci_dev *dev);
static void __devinit of_scan_bus(struct device_node *node,
struct pci_bus *bus)
{
struct device_node *child = NULL;
u32 *reg;
int reglen, devfn;
struct pci_dev *dev;
while ((child = of_get_next_child(node, child)) != NULL) {
reg = (u32 *) get_property(child, "reg", &reglen);
if (reg == NULL || reglen < 20)
continue;
devfn = (reg[0] >> 8) & 0xff;
/* create a new pci_dev for this device */
dev = of_create_pci_dev(child, bus, devfn);
if (!dev)
continue;
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
of_scan_pci_bridge(child, dev);
}
do_bus_setup(bus);
}
static void __devinit of_scan_pci_bridge(struct device_node *node,
struct pci_dev *dev)
{
struct pci_bus *bus;
u32 *busrange, *ranges;
int len, i, mode;
struct resource *res;
unsigned int flags;
u64 size;
/* parse bus-range property */
busrange = (u32 *) get_property(node, "bus-range", &len);
if (busrange == NULL || len != 8) {
printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
node->full_name);
return;
}
ranges = (u32 *) get_property(node, "ranges", &len);
if (ranges == NULL) {
printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
node->full_name);
return;
}
bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
if (!bus) {
printk(KERN_ERR "Failed to create pci bus for %s\n",
node->full_name);
return;
}
bus->primary = dev->bus->number;
bus->subordinate = busrange[1];
bus->bridge_ctl = 0;
bus->sysdata = node;
/* parse ranges property */
/* PCI #address-cells == 3 and #size-cells == 2 always */
res = &dev->resource[PCI_BRIDGE_RESOURCES];
for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
res->flags = 0;
bus->resource[i] = res;
++res;
}
i = 1;
for (; len >= 32; len -= 32, ranges += 8) {
flags = pci_parse_of_flags(ranges[0]);
size = GET_64BIT(ranges, 6);
if (flags == 0 || size == 0)
continue;
if (flags & IORESOURCE_IO) {
res = bus->resource[0];
if (res->flags) {
printk(KERN_ERR "PCI: ignoring extra I/O range"
" for bridge %s\n", node->full_name);
continue;
}
} else {
if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
printk(KERN_ERR "PCI: too many memory ranges"
" for bridge %s\n", node->full_name);
continue;
}
res = bus->resource[i];
++i;
}
res->start = GET_64BIT(ranges, 1);
res->end = res->start + size - 1;
res->flags = flags;
fixup_resource(res, dev);
}
sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
bus->number);
mode = PCI_PROBE_NORMAL;
if (ppc_md.pci_probe_mode)
mode = ppc_md.pci_probe_mode(bus);
if (mode == PCI_PROBE_DEVTREE)
of_scan_bus(node, bus);
else if (mode == PCI_PROBE_NORMAL)
pci_scan_child_bus(bus);
}
#endif /* CONFIG_PPC_MULTIPLATFORM */
static void __devinit scan_phb(struct pci_controller *hose)
{
struct pci_bus *bus;
struct device_node *node = hose->arch_data;
int i, mode;
struct resource *res;
bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
if (bus == NULL) {
printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
hose->global_number);
return;
}
bus->secondary = hose->first_busno;
hose->bus = bus;
bus->resource[0] = res = &hose->io_resource;
if (res->flags && request_resource(&ioport_resource, res))
printk(KERN_ERR "Failed to request PCI IO region "
"on PCI domain %04x\n", hose->global_number);
for (i = 0; i < 3; ++i) {
res = &hose->mem_resources[i];
bus->resource[i+1] = res;
if (res->flags && request_resource(&iomem_resource, res))
printk(KERN_ERR "Failed to request PCI memory region "
"on PCI domain %04x\n", hose->global_number);
}
mode = PCI_PROBE_NORMAL;
#ifdef CONFIG_PPC_MULTIPLATFORM
if (ppc_md.pci_probe_mode)
mode = ppc_md.pci_probe_mode(bus);
if (mode == PCI_PROBE_DEVTREE) {
bus->subordinate = hose->last_busno;
of_scan_bus(node, bus);
}
#endif /* CONFIG_PPC_MULTIPLATFORM */
if (mode == PCI_PROBE_NORMAL)
hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
pci_bus_add_devices(bus);
}
static int __init pcibios_init(void)
{
struct pci_controller *hose, *tmp;
struct pci_bus *bus;
/* For now, override phys_mem_access_prot. If we need it,
* later, we may move that initialization to each ppc_md
@ -242,13 +523,8 @@ static int __init pcibios_init(void)
printk("PCI: Probing PCI hardware\n");
/* Scan all of the recorded PCI controllers. */
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
hose->last_busno = 0xff;
bus = pci_scan_bus(hose->first_busno, hose->ops,
hose->arch_data);
hose->bus = bus;
hose->last_busno = bus->subordinate;
}
list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
scan_phb(hose);
#ifndef CONFIG_PPC_ISERIES
if (pci_probe_only)
@ -820,104 +1096,59 @@ void phbs_remap_io(void)
/*
* ppc64 can have multifunction devices that do not respond to function 0.
* In this case we must scan all functions.
* XXX this can go now, we use the OF device tree in all the
* cases that caused problems. -- paulus
*/
int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
{
struct device_node *busdn, *dn;
if (bus->self)
busdn = pci_device_to_OF_node(bus->self);
else
busdn = bus->sysdata; /* must be a phb */
if (busdn == NULL)
return 0;
/*
* Check to see if there is any of the 8 functions are in the
* device tree. If they are then we need to scan all the
* functions of this slot.
*/
for (dn = busdn->child; dn; dn = dn->sibling) {
struct pci_dn *pdn = dn->data;
if (pdn && (pdn->devfn >> 3) == (devfn >> 3))
return 1;
}
return 0;
}
static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
{
struct pci_controller *hose = pci_bus_to_host(dev->bus);
unsigned long start, end, mask, offset;
if (res->flags & IORESOURCE_IO) {
offset = (unsigned long)hose->io_base_virt - pci_io_base;
start = res->start += offset;
end = res->end += offset;
/* Need to allow IO access to pages that are in the
ISA range */
if (start < MAX_ISA_PORT) {
if (end > MAX_ISA_PORT)
end = MAX_ISA_PORT;
start >>= PAGE_SHIFT;
end >>= PAGE_SHIFT;
/* get the range of pages for the map */
mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
io_page_mask |= mask;
}
} else if (res->flags & IORESOURCE_MEM) {
res->start += hose->pci_mem_offset;
res->end += hose->pci_mem_offset;
}
}
void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
struct pci_bus *bus)
struct pci_bus *bus)
{
/* Update device resources. */
struct pci_controller *hose = pci_bus_to_host(bus);
int i;
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
if (dev->resource[i].flags & IORESOURCE_IO) {
unsigned long offset = (unsigned long)hose->io_base_virt
- pci_io_base;
unsigned long start, end, mask;
start = dev->resource[i].start += offset;
end = dev->resource[i].end += offset;
/* Need to allow IO access to pages that are in the
ISA range */
if (start < MAX_ISA_PORT) {
if (end > MAX_ISA_PORT)
end = MAX_ISA_PORT;
start >>= PAGE_SHIFT;
end >>= PAGE_SHIFT;
/* get the range of pages for the map */
mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
io_page_mask |= mask;
}
}
else if (dev->resource[i].flags & IORESOURCE_MEM) {
dev->resource[i].start += hose->pci_mem_offset;
dev->resource[i].end += hose->pci_mem_offset;
}
}
for (i = 0; i < PCI_NUM_RESOURCES; i++)
if (dev->resource[i].flags)
fixup_resource(&dev->resource[i], dev);
}
EXPORT_SYMBOL(pcibios_fixup_device_resources);
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
static void __devinit do_bus_setup(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
struct pci_dev *dev = bus->self;
struct resource *res;
int i;
if (!dev) {
/* Root bus. */
hose->bus = bus;
bus->resource[0] = res = &hose->io_resource;
if (res->flags && request_resource(&ioport_resource, res))
printk(KERN_ERR "Failed to request IO on "
"PCI domain %d\n", pci_domain_nr(bus));
for (i = 0; i < 3; ++i) {
res = &hose->mem_resources[i];
bus->resource[i+1] = res;
if (res->flags && request_resource(&iomem_resource, res))
printk(KERN_ERR "Failed to request MEM on "
"PCI domain %d\n",
pci_domain_nr(bus));
}
} else if (pci_probe_only &&
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
/* This is a subordinate bridge */
pci_read_bridge_bases(bus);
pcibios_fixup_device_resources(dev, bus);
}
struct pci_dev *dev;
ppc_md.iommu_bus_setup(bus);
@ -926,14 +1157,28 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
if (ppc_md.irq_bus_setup)
ppc_md.irq_bus_setup(bus);
}
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev = bus->self;
if (dev && pci_probe_only &&
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
/* This is a subordinate bridge */
pci_read_bridge_bases(bus);
pcibios_fixup_device_resources(dev, bus);
}
do_bus_setup(bus);
if (!pci_probe_only)
return;
list_for_each_entry(dev, &bus->devices, bus_list) {
list_for_each_entry(dev, &bus->devices, bus_list)
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
pcibios_fixup_device_resources(dev, bus);
}
}
EXPORT_SYMBOL(pcibios_fixup_bus);

56
arch/ppc64/kernel/pmac_pci.c
View File

@ -388,7 +388,7 @@ static void __init setup_u3_agp(struct pci_controller* hose)
* the reg address cell, we shall fix that by killing struct
* reg_property and using some accessor functions instead
*/
hose->first_busno = 0xf0;
hose->first_busno = 0xf0;
hose->last_busno = 0xff;
has_uninorth = 1;
hose->ops = &macrisc_pci_ops;
@ -473,7 +473,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
continue;
}
cur++;
DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
cur-1, res->start - 1, cur, res->end + 1);
hose->mem_resources[cur].name = np->full_name;
hose->mem_resources[cur].flags = IORESOURCE_MEM;
@ -603,24 +603,24 @@ static int __init add_bridge(struct device_node *dev)
char* disp_name;
int *bus_range;
int primary = 1;
struct property *of_prop;
struct property *of_prop;
DBG("Adding PCI host bridge %s\n", dev->full_name);
bus_range = (int *) get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
dev->full_name);
}
bus_range = (int *) get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
dev->full_name);
}
hose = alloc_bootmem(sizeof(struct pci_controller));
if (hose == NULL)
return -ENOMEM;
pci_setup_pci_controller(hose);
pci_setup_pci_controller(hose);
hose->arch_data = dev;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
hose->arch_data = dev;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
of_prop = alloc_bootmem(sizeof(struct property) +
sizeof(hose->global_number));
@ -634,24 +634,24 @@ static int __init add_bridge(struct device_node *dev)
}
disp_name = NULL;
if (device_is_compatible(dev, "u3-agp")) {
setup_u3_agp(hose);
disp_name = "U3-AGP";
primary = 0;
} else if (device_is_compatible(dev, "u3-ht")) {
setup_u3_ht(hose);
disp_name = "U3-HT";
primary = 1;
}
printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
disp_name, hose->first_busno, hose->last_busno);
if (device_is_compatible(dev, "u3-agp")) {
setup_u3_agp(hose);
disp_name = "U3-AGP";
primary = 0;
} else if (device_is_compatible(dev, "u3-ht")) {
setup_u3_ht(hose);
disp_name = "U3-HT";
primary = 1;
}
printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
disp_name, hose->first_busno, hose->last_busno);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pmac_process_bridge_OF_ranges(hose, dev, primary);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pmac_process_bridge_OF_ranges(hose, dev, primary);
/* Fixup "bus-range" OF property */
fixup_bus_range(dev);
/* Fixup "bus-range" OF property */
fixup_bus_range(dev);
return 0;
}

13
arch/ppc64/kernel/pmac_setup.c
View File

@ -477,6 +477,18 @@ static int __init pmac_probe(int platform)
return 1;
}
static int pmac_probe_mode(struct pci_bus *bus)
{
struct device_node *node = bus->sysdata;
/* We need to use normal PCI probing for the AGP bus,
since the device for the AGP bridge isn't in the tree. */
if (bus->self == NULL && device_is_compatible(node, "u3-agp"))
return PCI_PROBE_NORMAL;
return PCI_PROBE_DEVTREE;
}
struct machdep_calls __initdata pmac_md = {
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = generic_mach_cpu_die,
@ -488,6 +500,7 @@ struct machdep_calls __initdata pmac_md = {
.init_IRQ = pmac_init_IRQ,
.get_irq = mpic_get_irq,
.pcibios_fixup = pmac_pcibios_fixup,
.pci_probe_mode = pmac_probe_mode,
.restart = pmac_restart,
.power_off = pmac_power_off,
.halt = pmac_halt,

34
arch/ppc64/kernel/process.c
View File

@ -54,6 +54,7 @@
#include <asm/sections.h>
#include <asm/tlbflush.h>
#include <asm/time.h>
#include <asm/plpar_wrappers.h>
#ifndef CONFIG_SMP
struct task_struct *last_task_used_math = NULL;
@ -163,7 +164,30 @@ int dump_task_altivec(struct pt_regs *regs, elf_vrregset_t *vrregs)
#endif /* CONFIG_ALTIVEC */
static void set_dabr_spr(unsigned long val)
{
mtspr(SPRN_DABR, val);
}
int set_dabr(unsigned long dabr)
{
int ret = 0;
if (firmware_has_feature(FW_FEATURE_XDABR)) {
/* We want to catch accesses from kernel and userspace */
unsigned long flags = H_DABRX_KERNEL|H_DABRX_USER;
ret = plpar_set_xdabr(dabr, flags);
} else if (firmware_has_feature(FW_FEATURE_DABR)) {
ret = plpar_set_dabr(dabr);
} else {
set_dabr_spr(dabr);
}
return ret;
}
DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
static DEFINE_PER_CPU(unsigned long, current_dabr);
struct task_struct *__switch_to(struct task_struct *prev,
struct task_struct *new)
@ -198,6 +222,11 @@ struct task_struct *__switch_to(struct task_struct *prev,
new->thread.regs->msr |= MSR_VEC;
#endif /* CONFIG_ALTIVEC */
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr)) {
set_dabr(new->thread.dabr);
__get_cpu_var(current_dabr) = new->thread.dabr;
}
flush_tlb_pending();
new_thread = &new->thread;
@ -334,6 +363,11 @@ void flush_thread(void)
last_task_used_altivec = NULL;
#endif /* CONFIG_ALTIVEC */
#endif /* CONFIG_SMP */
if (current->thread.dabr) {
current->thread.dabr = 0;
set_dabr(0);
}
}
void

28
arch/ppc64/kernel/ptrace.c
View File

@ -17,6 +17,7 @@
* this archive for more details.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
@ -206,6 +207,19 @@ int sys_ptrace(long request, long pid, long addr, long data)
break;
}
case PTRACE_GET_DEBUGREG: {
ret = -EINVAL;
/* We only support one DABR and no IABRS at the moment */
if (addr > 0)
break;
ret = put_user(child->thread.dabr,
(unsigned long __user *)data);
break;
}
case PTRACE_SET_DEBUGREG:
ret = ptrace_set_debugreg(child, addr, data);
case PTRACE_DETACH:
ret = ptrace_detach(child, data);
break;
@ -274,6 +288,20 @@ int sys_ptrace(long request, long pid, long addr, long data)
break;
}
#ifdef CONFIG_ALTIVEC
case PTRACE_GETVRREGS:
/* Get the child altivec register state. */
flush_altivec_to_thread(child);
ret = get_vrregs((unsigned long __user *)data, child);
break;
case PTRACE_SETVRREGS:
/* Set the child altivec register state. */
flush_altivec_to_thread(child);
ret = set_vrregs(child, (unsigned long __user *)data);
break;
#endif
default:
ret = ptrace_request(child, request, addr, data);
break;

34
arch/ppc64/kernel/ptrace32.c
View File

@ -17,6 +17,7 @@
* this archive for more details.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
@ -337,6 +338,19 @@ int sys32_ptrace(long request, long pid, unsigned long addr, unsigned long data)
break;
}
case PTRACE_GET_DEBUGREG: {
ret = -EINVAL;
/* We only support one DABR and no IABRS at the moment */
if (addr > 0)
break;
ret = put_user(child->thread.dabr, (u32 __user *)data);
break;
}
case PTRACE_SET_DEBUGREG:
ret = ptrace_set_debugreg(child, addr, data);
break;
case PTRACE_DETACH:
ret = ptrace_detach(child, data);
break;
@ -405,9 +419,23 @@ int sys32_ptrace(long request, long pid, unsigned long addr, unsigned long data)
break;
}
case PTRACE_GETEVENTMSG:
ret = put_user(child->ptrace_message, (unsigned int __user *) data);
break;
case PTRACE_GETEVENTMSG:
ret = put_user(child->ptrace_message, (unsigned int __user *) data);
break;
#ifdef CONFIG_ALTIVEC
case PTRACE_GETVRREGS:
/* Get the child altivec register state. */
flush_altivec_to_thread(child);
ret = get_vrregs((unsigned long __user *)data, child);
break;
case PTRACE_SETVRREGS:
/* Set the child altivec register state. */
flush_altivec_to_thread(child);
ret = set_vrregs(child, (unsigned long __user *)data);
break;
#endif
default:
ret = ptrace_request(child, request, addr, data);

2
arch/ppc64/kernel/ras.c
View File

@ -59,8 +59,6 @@ char mce_data_buf[RTAS_ERROR_LOG_MAX]
/* This is true if we are using the firmware NMI handler (typically LPAR) */
extern int fwnmi_active;
extern void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr);
static int ras_get_sensor_state_token;
static int ras_check_exception_token;

16
arch/ppc64/kernel/setup.c
View File

@ -1064,8 +1064,6 @@ void __init setup_arch(char **cmdline_p)
#define PPC64_LINUX_FUNCTION 0x0f000000
#define PPC64_IPL_MESSAGE 0xc0000000
#define PPC64_TERM_MESSAGE 0xb0000000
#define PPC64_ATTN_MESSAGE 0xa0000000
#define PPC64_DUMP_MESSAGE 0xd0000000
static void ppc64_do_msg(unsigned int src, const char *msg)
{
@ -1093,20 +1091,6 @@ void ppc64_terminate_msg(unsigned int src, const char *msg)
printk("[terminate]%04x %s\n", src, msg);
}
/* Print something that needs attention (device error, etc) */
void ppc64_attention_msg(unsigned int src, const char *msg)
{
ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_ATTN_MESSAGE|src, msg);
printk("[attention]%04x %s\n", src, msg);
}
/* Print a dump progress message. */
void ppc64_dump_msg(unsigned int src, const char *msg)
{
ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_DUMP_MESSAGE|src, msg);
printk("[dump]%04x %s\n", src, msg);
}
/* This should only be called on processor 0 during calibrate decr */
void __init setup_default_decr(void)
{

9
arch/ppc64/kernel/signal.c
View File

@ -550,6 +550,15 @@ int do_signal(sigset_t *oldset, struct pt_regs *regs)
/* Whee! Actually deliver the signal. */
if (TRAP(regs) == 0x0C00)
syscall_restart(regs, &ka);
/*
* Reenable the DABR before delivering the signal to
* user space. The DABR will have been cleared if it
* triggered inside the kernel.
*/
if (current->thread.dabr)
set_dabr(current->thread.dabr);
return handle_signal(signr, &ka, &info, oldset, regs);
}

8
arch/ppc64/kernel/signal32.c
View File

@ -970,6 +970,14 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs)
newsp = regs->gpr[1];
newsp &= ~0xfUL;
/*
* Reenable the DABR before delivering the signal to
* user space. The DABR will have been cleared if it
* triggered inside the kernel.
*/
if (current->thread.dabr)
set_dabr(current->thread.dabr);
/* Whee! Actually deliver the signal. */
if (ka.sa.sa_flags & SA_SIGINFO)
ret = handle_rt_signal32(signr, &ka, &info, oldset, regs, newsp);

44
arch/ppc64/kernel/xics.c
View File

@ -38,7 +38,7 @@ static void xics_mask_and_ack_irq(unsigned int irq);
static void xics_end_irq(unsigned int irq);
static void xics_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
struct hw_interrupt_type xics_pic = {
static struct hw_interrupt_type xics_pic = {
.typename = " XICS ",
.startup = xics_startup,
.enable = xics_enable_irq,
@ -48,7 +48,7 @@ struct hw_interrupt_type xics_pic = {
.set_affinity = xics_set_affinity
};
struct hw_interrupt_type xics_8259_pic = {
static struct hw_interrupt_type xics_8259_pic = {
.typename = " XICS/8259",
.ack = xics_mask_and_ack_irq,
};
@ -89,9 +89,8 @@ static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
static int xics_irq_8259_cascade = 0;
static int xics_irq_8259_cascade_real = 0;
static unsigned int default_server = 0xFF;
/* also referenced in smp.c... */
unsigned int default_distrib_server = 0;
unsigned int interrupt_server_size = 8;
static unsigned int default_distrib_server = 0;
static unsigned int interrupt_server_size = 8;
/*
* XICS only has a single IPI, so encode the messages per CPU
@ -99,10 +98,10 @@ unsigned int interrupt_server_size = 8;
struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
/* RTAS service tokens */
int ibm_get_xive;
int ibm_set_xive;
int ibm_int_on;
int ibm_int_off;
static int ibm_get_xive;
static int ibm_set_xive;
static int ibm_int_on;
static int ibm_int_off;
typedef struct {
int (*xirr_info_get)(int cpu);
@ -284,16 +283,17 @@ static void xics_enable_irq(unsigned int virq)
call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
DEFAULT_PRIORITY);
if (call_status != 0) {
printk(KERN_ERR "xics_enable_irq: irq=%d: ibm_set_xive "
"returned %x\n", irq, call_status);
printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
"returned %d\n", irq, call_status);
printk("set_xive %x, server %x\n", ibm_set_xive, server);
return;
}
/* Now unmask the interrupt (often a no-op) */
call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
if (call_status != 0) {
printk(KERN_ERR "xics_enable_irq: irq=%d: ibm_int_on "
"returned %x\n", irq, call_status);
printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
"returned %d\n", irq, call_status);
return;
}
}
@ -308,8 +308,8 @@ static void xics_disable_real_irq(unsigned int irq)
call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
if (call_status != 0) {
printk(KERN_ERR "xics_disable_real_irq: irq=%d: "
"ibm_int_off returned %x\n", irq, call_status);
printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
"ibm_int_off returned %d\n", irq, call_status);
return;
}
@ -317,8 +317,8 @@ static void xics_disable_real_irq(unsigned int irq)
/* Have to set XIVE to 0xff to be able to remove a slot */
call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, 0xff);
if (call_status != 0) {
printk(KERN_ERR "xics_disable_irq: irq=%d: ibm_set_xive(0xff)"
" returned %x\n", irq, call_status);
printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
" returned %d\n", irq, call_status);
return;
}
}
@ -380,7 +380,7 @@ int xics_get_irq(struct pt_regs *regs)
if (irq == NO_IRQ)
irq = real_irq_to_virt_slowpath(vec);
if (irq == NO_IRQ) {
printk(KERN_ERR "Interrupt %d (real) is invalid,"
printk(KERN_ERR "Interrupt %u (real) is invalid,"
" disabling it.\n", vec);
xics_disable_real_irq(vec);
} else
@ -622,7 +622,7 @@ static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
if (status) {
printk(KERN_ERR "xics_set_affinity: irq=%d ibm,get-xive "
printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
"returns %d\n", irq, status);
return;
}
@ -641,7 +641,7 @@ static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
irq, newmask, xics_status[1]);
if (status) {
printk(KERN_ERR "xics_set_affinity: irq=%d ibm,set-xive "
printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
"returns %d\n", irq, status);
return;
}
@ -720,7 +720,7 @@ void xics_migrate_irqs_away(void)
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
if (status) {
printk(KERN_ERR "migrate_irqs_away: irq=%d "
printk(KERN_ERR "migrate_irqs_away: irq=%u "
"ibm,get-xive returns %d\n",
virq, status);
goto unlock;
@ -734,7 +734,7 @@ void xics_migrate_irqs_away(void)
if (xics_status[0] != get_hard_smp_processor_id(cpu))
goto unlock;
printk(KERN_WARNING "IRQ %d affinity broken off cpu %u\n",
printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
virq, cpu);
/* Reset affinity to all cpus */

31
arch/ppc64/mm/fault.c
View File

@ -77,6 +77,28 @@ static int store_updates_sp(struct pt_regs *regs)
return 0;
}
static void do_dabr(struct pt_regs *regs, unsigned long error_code)
{
siginfo_t info;
if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
11, SIGSEGV) == NOTIFY_STOP)
return;
if (debugger_dabr_match(regs))
return;
/* Clear the DABR */
set_dabr(0);
/* Deliver the signal to userspace */
info.si_signo = SIGTRAP;
info.si_errno = 0;
info.si_code = TRAP_HWBKPT;
info.si_addr = (void __user *)regs->nip;
force_sig_info(SIGTRAP, &info, current);
}
/*
* The error_code parameter is
* - DSISR for a non-SLB data access fault,
@ -111,12 +133,9 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
if (!user_mode(regs) && (address >= TASK_SIZE))
return SIGSEGV;
if (error_code & DSISR_DABRMATCH) {
if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
11, SIGSEGV) == NOTIFY_STOP)
return 0;
if (debugger_dabr_match(regs))
return 0;
if (error_code & DSISR_DABRMATCH) {
do_dabr(regs, error_code);
return 0;
}
if (in_atomic() || mm == NULL) {

1
arch/ppc64/xmon/privinst.h
View File

@ -46,7 +46,6 @@ GSETSPR(287, pvr)
GSETSPR(1008, hid0)
GSETSPR(1009, hid1)
GSETSPR(1010, iabr)
GSETSPR(1013, dabr)
GSETSPR(1023, pir)
static inline void store_inst(void *p)

20
arch/ppc64/xmon/xmon.c
View File

@ -586,6 +586,8 @@ int xmon_dabr_match(struct pt_regs *regs)
{
if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
return 0;
if (dabr.enabled == 0)
return 0;
xmon_core(regs, 0);
return 1;
}
@ -628,20 +630,6 @@ int xmon_fault_handler(struct pt_regs *regs)
return 0;
}
/* On systems with a hypervisor, we can't set the DABR
(data address breakpoint register) directly. */
static void set_controlled_dabr(unsigned long val)
{
#ifdef CONFIG_PPC_PSERIES
if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
int rc = plpar_hcall_norets(H_SET_DABR, val);
if (rc != H_Success)
xmon_printf("Warning: setting DABR failed (%d)\n", rc);
} else
#endif
set_dabr(val);
}
static struct bpt *at_breakpoint(unsigned long pc)
{
int i;
@ -728,7 +716,7 @@ static void insert_bpts(void)
static void insert_cpu_bpts(void)
{
if (dabr.enabled)
set_controlled_dabr(dabr.address | (dabr.enabled & 7));
set_dabr(dabr.address | (dabr.enabled & 7));
if (iabr && cpu_has_feature(CPU_FTR_IABR))
set_iabr(iabr->address
| (iabr->enabled & (BP_IABR|BP_IABR_TE)));
@ -756,7 +744,7 @@ static void remove_bpts(void)
static void remove_cpu_bpts(void)
{
set_controlled_dabr(0);
set_dabr(0);
if (cpu_has_feature(CPU_FTR_IABR))
set_iabr(0);
}

6
drivers/w1/w1_ds2433.c
View File

@ -15,6 +15,10 @@
#include <linux/delay.h>
#ifdef CONFIG_W1_F23_CRC
#include <linux/crc16.h>
#define CRC16_INIT 0
#define CRC16_VALID 0xb001
#endif
#include "w1.h"
@ -214,7 +218,7 @@ static ssize_t w1_f23_write_bin(struct kobject *kobj, char *buf, loff_t off,
#ifdef CONFIG_W1_F23_CRC
/* can only write full blocks in cached mode */
if ((off & W1_PAGE_MASK) || (count & W1_PAGE_MASK)) {
dev_err(&sl->dev, "invalid offset/count off=%d cnt=%d\n",
dev_err(&sl->dev, "invalid offset/count off=%d cnt=%zd\n",
(int)off, count);
return -EINVAL;
}

8
include/asm-powerpc/siginfo.h
View File

@ -15,4 +15,12 @@
#include <asm-generic/siginfo.h>
/*
* SIGTRAP si_codes
*/
#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint or watchpoint */
#undef NSIGTRAP
#define NSIGTRAP 4
#endif /* _ASM_POWERPC_SIGINFO_H */

7
include/asm-ppc/ptrace.h
View File

@ -142,4 +142,11 @@ do { \
#define PTRACE_GETEVRREGS 20
#define PTRACE_SETEVRREGS 21
/*
* Get or set a debug register. The first 16 are DABR registers and the
* second 16 are IABR registers.
*/
#define PTRACE_GET_DEBUGREG 25
#define PTRACE_SET_DEBUGREG 26
#endif

6
include/asm-ppc64/hvcall.h
View File

@ -56,6 +56,11 @@
#define H_PP1 (1UL<<(63-62))
#define H_PP2 (1UL<<(63-63))
/* DABRX flags */
#define H_DABRX_HYPERVISOR (1UL<<(63-61))
#define H_DABRX_KERNEL (1UL<<(63-62))
#define H_DABRX_USER (1UL<<(63-63))
/* pSeries hypervisor opcodes */
#define H_REMOVE 0x04
#define H_ENTER 0x08
@ -101,6 +106,7 @@
#define H_VIO_SIGNAL 0x104
#define H_SEND_CRQ 0x108
#define H_COPY_RDMA 0x110
#define H_SET_XDABR 0x134
#define H_STUFF_TCE 0x138
#define H_PUT_TCE_INDIRECT 0x13C
#define H_VTERM_PARTNER_INFO 0x150

5
include/asm-ppc64/machdep.h
View File

@ -88,6 +88,7 @@ struct machdep_calls {
/* PCI stuff */
void (*pcibios_fixup)(void);
int (*pci_probe_mode)(struct pci_bus *);
void (*restart)(char *cmd);
void (*power_off)(void);
@ -173,10 +174,6 @@ extern sys_ctrler_t sys_ctrler;
void ppc64_boot_msg(unsigned int src, const char *msg);
/* Print a termination message (print only -- does not stop the kernel) */
void ppc64_terminate_msg(unsigned int src, const char *msg);
/* Print something that needs attention (device error, etc) */
void ppc64_attention_msg(unsigned int src, const char *msg);
/* Print a dump progress message. */
void ppc64_dump_msg(unsigned int src, const char *msg);
static inline void log_error(char *buf, unsigned int err_type, int fatal)
{

5
include/asm-ppc64/pci-bridge.h
View File

@ -119,5 +119,10 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
return PCI_DN(busdn)->phb;
}
/* Return values for ppc_md.pci_probe_mode function */
#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
#endif
#endif /* __KERNEL__ */

9
include/asm-ppc64/plpar_wrappers.h
View File

@ -107,5 +107,14 @@ static inline long plpar_put_term_char(unsigned long termno,
lbuf[1]);
}
static inline long plpar_set_xdabr(unsigned long address, unsigned long flags)
{
return plpar_hcall_norets(H_SET_XDABR, address, flags);
}
static inline long plpar_set_dabr(unsigned long val)
{
return plpar_hcall_norets(H_SET_DABR, val);
}
#endif /* _PPC64_PLPAR_WRAPPERS_H */

1
include/asm-ppc64/processor.h
View File

@ -433,6 +433,7 @@ struct thread_struct {
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
unsigned long vdso_base; /* base of the vDSO library */
unsigned long dabr; /* Data address breakpoint register */
#ifdef CONFIG_ALTIVEC
/* Complete AltiVec register set */
vector128 vr[32] __attribute((aligned(16)));

92
include/asm-ppc64/ptrace-common.h
View File

@ -11,6 +11,10 @@
#ifndef _PPC64_PTRACE_COMMON_H
#define _PPC64_PTRACE_COMMON_H
#include <linux/config.h>
#include <asm/system.h>
/*
* Set of msr bits that gdb can change on behalf of a process.
*/
@ -69,4 +73,92 @@ static inline void clear_single_step(struct task_struct *task)
clear_ti_thread_flag(task->thread_info, TIF_SINGLESTEP);
}
#ifdef CONFIG_ALTIVEC
/*
* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
* The transfer totals 34 quadword. Quadwords 0-31 contain the
* corresponding vector registers. Quadword 32 contains the vscr as the
* last word (offset 12) within that quadword. Quadword 33 contains the
* vrsave as the first word (offset 0) within the quadword.
*
* This definition of the VMX state is compatible with the current PPC32
* ptrace interface. This allows signal handling and ptrace to use the
* same structures. This also simplifies the implementation of a bi-arch
* (combined (32- and 64-bit) gdb.
*/
/*
* Get contents of AltiVec register state in task TASK
*/
static inline int get_vrregs(unsigned long __user *data,
struct task_struct *task)
{
unsigned long regsize;
/* copy AltiVec registers VR[0] .. VR[31] */
regsize = 32 * sizeof(vector128);
if (copy_to_user(data, task->thread.vr, regsize))
return -EFAULT;
data += (regsize / sizeof(unsigned long));
/* copy VSCR */
regsize = 1 * sizeof(vector128);
if (copy_to_user(data, &task->thread.vscr, regsize))
return -EFAULT;
data += (regsize / sizeof(unsigned long));
/* copy VRSAVE */
if (put_user(task->thread.vrsave, (u32 __user *)data))
return -EFAULT;
return 0;
}
/*
* Write contents of AltiVec register state into task TASK.
*/
static inline int set_vrregs(struct task_struct *task,
unsigned long __user *data)
{
unsigned long regsize;
/* copy AltiVec registers VR[0] .. VR[31] */
regsize = 32 * sizeof(vector128);
if (copy_from_user(task->thread.vr, data, regsize))
return -EFAULT;
data += (regsize / sizeof(unsigned long));
/* copy VSCR */
regsize = 1 * sizeof(vector128);
if (copy_from_user(&task->thread.vscr, data, regsize))
return -EFAULT;
data += (regsize / sizeof(unsigned long));
/* copy VRSAVE */
if (get_user(task->thread.vrsave, (u32 __user *)data))
return -EFAULT;
return 0;
}
#endif
static inline int ptrace_set_debugreg(struct task_struct *task,
unsigned long addr, unsigned long data)
{
/* We only support one DABR and no IABRS at the moment */
if (addr > 0)
return -EINVAL;
/* The bottom 3 bits are flags */
if ((data & ~0x7UL) >= TASK_SIZE)
return -EIO;
/* Ensure translation is on */
if (data && !(data & DABR_TRANSLATION))
return -EIO;
task->thread.dabr = data;
return 0;
}
#endif /* _PPC64_PTRACE_COMMON_H */

128
include/asm-ppc64/ptrace.h
View File

@ -25,56 +25,49 @@
*/
#ifndef __ASSEMBLY__
#define PPC_REG unsigned long
struct pt_regs {
PPC_REG gpr[32];
PPC_REG nip;
PPC_REG msr;
PPC_REG orig_gpr3; /* Used for restarting system calls */
PPC_REG ctr;
PPC_REG link;
PPC_REG xer;
PPC_REG ccr;
PPC_REG softe; /* Soft enabled/disabled */
PPC_REG trap; /* Reason for being here */
PPC_REG dar; /* Fault registers */
PPC_REG dsisr;
PPC_REG result; /* Result of a system call */
unsigned long gpr[32];
unsigned long nip;
unsigned long msr;
unsigned long orig_gpr3; /* Used for restarting system calls */
unsigned long ctr;
unsigned long link;
unsigned long xer;
unsigned long ccr;
unsigned long softe; /* Soft enabled/disabled */
unsigned long trap; /* Reason for being here */
unsigned long dar; /* Fault registers */
unsigned long dsisr;
unsigned long result; /* Result of a system call */
};
#define PPC_REG_32 unsigned int
struct pt_regs32 {
PPC_REG_32 gpr[32];
PPC_REG_32 nip;
PPC_REG_32 msr;
PPC_REG_32 orig_gpr3; /* Used for restarting system calls */
PPC_REG_32 ctr;
PPC_REG_32 link;
PPC_REG_32 xer;
PPC_REG_32 ccr;
PPC_REG_32 mq; /* 601 only (not used at present) */
/* Used on APUS to hold IPL value. */
PPC_REG_32 trap; /* Reason for being here */
PPC_REG_32 dar; /* Fault registers */
PPC_REG_32 dsisr;
PPC_REG_32 result; /* Result of a system call */
unsigned int gpr[32];
unsigned int nip;
unsigned int msr;
unsigned int orig_gpr3; /* Used for restarting system calls */
unsigned int ctr;
unsigned int link;
unsigned int xer;
unsigned int ccr;
unsigned int mq; /* 601 only (not used at present) */
unsigned int trap; /* Reason for being here */
unsigned int dar; /* Fault registers */
unsigned int dsisr;
unsigned int result; /* Result of a system call */
};
#ifdef __KERNEL__
#define instruction_pointer(regs) ((regs)->nip)
#ifdef CONFIG_SMP
extern unsigned long profile_pc(struct pt_regs *regs);
#else
#define profile_pc(regs) instruction_pointer(regs)
#endif
#endif /* __ASSEMBLY__ */
#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
/* Size of dummy stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 128
#define __SIGNAL_FRAMESIZE32 64
#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
#define force_successful_syscall_return() \
@ -89,6 +82,16 @@ extern unsigned long profile_pc(struct pt_regs *regs);
#define TRAP(regs) ((regs)->trap & ~0xF)
#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
/* Size of dummy stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 128
#define __SIGNAL_FRAMESIZE32 64
/*
* Offsets used by 'ptrace' system call interface.
*/
@ -135,17 +138,21 @@ extern unsigned long profile_pc(struct pt_regs *regs);
#define PT_XER 37
#define PT_CCR 38
#define PT_SOFTE 39
#define PT_TRAP 40
#define PT_DAR 41
#define PT_DSISR 42
#define PT_RESULT 43
#define PT_FPR0 48
/* Kernel and userspace will both use this PT_FPSCR value. 32-bit apps will have
* visibility to the asm-ppc/ptrace.h header instead of this one.
/*
* Kernel and userspace will both use this PT_FPSCR value. 32-bit apps will
* have visibility to the asm-ppc/ptrace.h header instead of this one.
*/
#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
#ifdef __KERNEL__
#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
#endif
#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
@ -173,17 +180,34 @@ extern unsigned long profile_pc(struct pt_regs *regs);
#define PTRACE_GETVRREGS 18
#define PTRACE_SETVRREGS 19
/* Additional PTRACE requests implemented on PowerPC. */
#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
#define PPC_PTRACE_PEEKTEXT_3264 0x95 /* Read word at location ADDR on a 64-bit process from a 32-bit process. */
#define PPC_PTRACE_PEEKDATA_3264 0x94 /* Read word at location ADDR on a 64-bit process from a 32-bit process. */
#define PPC_PTRACE_POKETEXT_3264 0x93 /* Write word at location ADDR on a 64-bit process from a 32-bit process. */
#define PPC_PTRACE_POKEDATA_3264 0x92 /* Write word at location ADDR on a 64-bit process from a 32-bit process. */
#define PPC_PTRACE_PEEKUSR_3264 0x91 /* Read a register (specified by ADDR) out of the "user area" on a 64-bit process from a 32-bit process. */
#define PPC_PTRACE_POKEUSR_3264 0x90 /* Write DATA into location ADDR within the "user area" on a 64-bit process from a 32-bit process. */
/*
* While we dont have 64bit book E processors, we need to reserve the
* relevant ptrace calls for 32bit compatibility.
*/
#if 0
#define PTRACE_GETEVRREGS 20
#define PTRACE_SETEVRREGS 21
#endif
/*
* Get or set a debug register. The first 16 are DABR registers and the
* second 16 are IABR registers.
*/
#define PTRACE_GET_DEBUGREG 25
#define PTRACE_SET_DEBUGREG 26
/* Additional PTRACE requests implemented on PowerPC. */
#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
/* Calls to trace a 64bit program from a 32bit program */
#define PPC_PTRACE_PEEKTEXT_3264 0x95
#define PPC_PTRACE_PEEKDATA_3264 0x94
#define PPC_PTRACE_POKETEXT_3264 0x93
#define PPC_PTRACE_POKEDATA_3264 0x92
#define PPC_PTRACE_PEEKUSR_3264 0x91
#define PPC_PTRACE_POKEUSR_3264 0x90
#endif /* _PPC64_PTRACE_H */

3
include/asm-ppc64/system.h
View File

@ -101,6 +101,9 @@ static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif
extern int set_dabr(unsigned long dabr);
extern void _exception(int signr, struct pt_regs *regs, int code,
unsigned long addr);
extern int fix_alignment(struct pt_regs *regs);
extern void bad_page_fault(struct pt_regs *regs, unsigned long address,
int sig);

16
include/linux/crc16.h
View File

@ -1,22 +1,11 @@
/*
* crc16.h - CRC-16 routine
*
* Implements the standard CRC-16, as used with 1-wire devices:
* Implements the standard CRC-16:
* Width 16
* Poly 0x8005 (x^16 + x^15 + x^2 + 1)
* Init 0
*
* For 1-wire devices, the CRC is stored inverted, LSB-first
*
* Example buffer with the CRC attached:
* 31 32 33 34 35 36 37 38 39 C2 44
*
* The CRC over a buffer with the CRC attached is 0xB001.
* So, if (crc16(0, buf, size) == 0xB001) then the buffer is valid.
*
* Refer to "Application Note 937: Book of iButton Standards" for details.
* http://www.maxim-ic.com/appnotes.cfm/appnote_number/937
*
* Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
*
* This source code is licensed under the GNU General Public License,
@ -28,9 +17,6 @@
#include <linux/types.h>
#define CRC16_INIT 0
#define CRC16_VALID 0xb001
extern u16 const crc16_table[256];
extern u16 crc16(u16 crc, const u8 *buffer, size_t len);