qlge: Add data for firmware dump.
Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ron Mercer
David S. Miller
parent
d86458471a
commit
b87babeb40
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@ -75,15 +75,43 @@
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#define TX_DESC_PER_OAL 0
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#endif
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/* Word shifting for converting 64-bit
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* address to a series of 16-bit words.
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* This is used for some MPI firmware
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* mailbox commands.
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*/
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#define LSW(x) ((u16)(x))
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#define MSW(x) ((u16)((u32)(x) >> 16))
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#define LSD(x) ((u32)((u64)(x)))
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#define MSD(x) ((u32)((((u64)(x)) >> 32)))
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/* MPI test register definitions. This register
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* is used for determining alternate NIC function's
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* PCI->func number.
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*/
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enum {
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MPI_TEST_FUNC_PORT_CFG = 0x1002,
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MPI_TEST_NIC1_FUNC_SHIFT = 1,
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MPI_TEST_NIC2_FUNC_SHIFT = 5,
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MPI_TEST_FUNC_PRB_CTL = 0x100e,
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MPI_TEST_FUNC_PRB_EN = 0x18a20000,
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MPI_TEST_FUNC_RST_STS = 0x100a,
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MPI_TEST_FUNC_RST_FRC = 0x00000003,
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MPI_TEST_NIC_FUNC_MASK = 0x00000007,
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MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
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MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
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MPI_TEST_NIC1_FUNC_SHIFT = 1,
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MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
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MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
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MPI_TEST_NIC2_FUNC_SHIFT = 5,
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MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
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MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00,
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MPI_TEST_FC1_FUNCTION_SHIFT = 9,
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MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
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MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
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MPI_TEST_FC2_FUNCTION_SHIFT = 13,
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MPI_NIC_READ = 0x00000000,
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MPI_NIC_REG_BLOCK = 0x00020000,
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MPI_NIC_FUNCTION_SHIFT = 6,
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};
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/*
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@ -464,7 +492,7 @@ enum {
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MDIO_PORT = 0x00000440,
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MDIO_STATUS = 0x00000450,
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/* XGMAC AUX statistics registers */
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XGMAC_REGISTER_END = 0x00000740,
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};
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/*
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@ -505,6 +533,7 @@ enum {
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enum {
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MAC_ADDR_IDX_SHIFT = 4,
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MAC_ADDR_TYPE_SHIFT = 16,
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MAC_ADDR_TYPE_COUNT = 10,
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MAC_ADDR_TYPE_MASK = 0x000f0000,
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MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
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MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
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@ -522,6 +551,30 @@ enum {
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MAC_ADDR_MR = (1 << 30),
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MAC_ADDR_MW = (1 << 31),
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MAX_MULTICAST_ENTRIES = 32,
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/* Entry count and words per entry
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* for each address type in the filter.
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*/
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MAC_ADDR_MAX_CAM_ENTRIES = 512,
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MAC_ADDR_MAX_CAM_WCOUNT = 3,
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MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
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MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
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MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
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MAC_ADDR_MAX_VLAN_WCOUNT = 1,
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MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
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MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
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MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
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MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
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MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
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MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
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MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
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MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
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MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
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MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
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MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
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MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
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MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
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MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
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};
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/*
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@ -592,6 +645,7 @@ enum {
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enum {
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RT_IDX_IDX_SHIFT = 8,
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RT_IDX_TYPE_MASK = 0x000f0000,
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RT_IDX_TYPE_SHIFT = 16,
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RT_IDX_TYPE_RT = 0x00000000,
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RT_IDX_TYPE_RT_INV = 0x00010000,
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RT_IDX_TYPE_NICQ = 0x00020000,
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@ -660,7 +714,89 @@ enum {
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RT_IDX_UNUSED013 = 13,
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RT_IDX_UNUSED014 = 14,
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RT_IDX_PROMISCUOUS_SLOT = 15,
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RT_IDX_MAX_SLOTS = 16,
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RT_IDX_MAX_RT_SLOTS = 8,
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RT_IDX_MAX_NIC_SLOTS = 16,
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};
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/*
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* Serdes Address Register (XG_SERDES_ADDR) bit definitions.
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*/
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enum {
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XG_SERDES_ADDR_RDY = (1 << 31),
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XG_SERDES_ADDR_R = (1 << 30),
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XG_SERDES_ADDR_STS = 0x00001E06,
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XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
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XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
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XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
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/* Serdes coredump definitions. */
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XG_SERDES_XAUI_AN_START = 0x00000000,
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XG_SERDES_XAUI_AN_END = 0x00000034,
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XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
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XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
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XG_SERDES_XFI_AN_START = 0x00001000,
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XG_SERDES_XFI_AN_END = 0x00001034,
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XG_SERDES_XFI_TRAIN_START = 0x10001050,
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XG_SERDES_XFI_TRAIN_END = 0x1000107C,
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XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
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XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
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XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
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XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
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XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
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XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
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XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
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XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
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};
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/*
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* NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions.
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*/
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enum {
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PRB_MX_ADDR_ARE = (1 << 16),
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PRB_MX_ADDR_UP = (1 << 15),
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PRB_MX_ADDR_SWP = (1 << 14),
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/* Module select values. */
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PRB_MX_ADDR_MAX_MODS = 21,
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PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
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PRB_MX_ADDR_MOD_SEL_TBD = 0,
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PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
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PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
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PRB_MX_ADDR_MOD_SEL_FRB = 3,
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PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
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PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
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PRB_MX_ADDR_MOD_SEL_DA1 = 6,
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PRB_MX_ADDR_MOD_SEL_DA2 = 7,
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PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
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PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
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PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
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PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
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PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
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PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
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PRB_MX_ADDR_MOD_SEL_REG = 14,
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PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
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PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
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PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
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PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
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PRB_MX_ADDR_MOD_SEL_MOP = 20,
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/* Bit fields indicating which modules
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* are valid for each clock domain.
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*/
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PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
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PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
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PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
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PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
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PRB_MX_ADDR_VALID_TOTAL = 34,
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/* Clock domain values. */
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PRB_MX_ADDR_CLOCK_SHIFT = 6,
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PRB_MX_ADDR_SYS_CLOCK = 0,
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PRB_MX_ADDR_PCI_CLOCK = 2,
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PRB_MX_ADDR_FC_CLOCK = 5,
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PRB_MX_ADDR_XGM_CLOCK = 6,
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PRB_MX_ADDR_MAX_MUX = 64,
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};
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/*
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@ -1432,7 +1568,7 @@ struct nic_stats {
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u64 rx_nic_fifo_drop;
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};
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/* Address/Length pairs for the coredump. */
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/* Firmware coredump internal register address/length pairs. */
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enum {
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MPI_CORE_REGS_ADDR = 0x00030000,
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MPI_CORE_REGS_CNT = 127,
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@ -1487,7 +1623,7 @@ struct mpi_coredump_segment_header {
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u8 description[16];
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};
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/* Reg dump segment numbers. */
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/* Firmware coredump header segment numbers. */
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enum {
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CORE_SEG_NUM = 1,
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TEST_LOGIC_SEG_NUM = 2,
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@ -1538,6 +1674,67 @@ enum {
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};
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/* There are 64 generic NIC registers. */
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#define NIC_REGS_DUMP_WORD_COUNT 64
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/* XGMAC word count. */
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#define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)
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/* Word counts for the SERDES blocks. */
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#define XG_SERDES_XAUI_AN_COUNT 14
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#define XG_SERDES_XAUI_HSS_PCS_COUNT 33
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#define XG_SERDES_XFI_AN_COUNT 14
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#define XG_SERDES_XFI_TRAIN_COUNT 12
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#define XG_SERDES_XFI_HSS_PCS_COUNT 15
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#define XG_SERDES_XFI_HSS_TX_COUNT 32
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#define XG_SERDES_XFI_HSS_RX_COUNT 32
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#define XG_SERDES_XFI_HSS_PLL_COUNT 32
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/* There are 2 CNA ETS and 8 NIC ETS registers. */
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#define ETS_REGS_DUMP_WORD_COUNT 10
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/* Each probe mux entry stores the probe type plus 64 entries
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* that are each each 64-bits in length. There are a total of
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* 34 (PRB_MX_ADDR_VALID_TOTAL) valid probes.
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*/
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#define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))
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#define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \
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PRB_MX_ADDR_VALID_TOTAL)
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/* Each routing entry consists of 4 32-bit words.
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* They are route type, index, index word, and result.
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* There are 2 route blocks with 8 entries each and
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* 2 NIC blocks with 16 entries each.
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* The totol entries is 48 with 4 words each.
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*/
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#define RT_IDX_DUMP_ENTRIES 48
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#define RT_IDX_DUMP_WORDS_PER_ENTRY 4
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#define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \
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RT_IDX_DUMP_WORDS_PER_ENTRY)
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/* There are 10 address blocks in filter, each with
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* different entry counts and different word-count-per-entry.
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*/
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#define MAC_ADDR_DUMP_ENTRIES \
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((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
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(MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
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(MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
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(MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
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(MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
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(MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
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(MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
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(MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
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(MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
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(MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
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#define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2
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#define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \
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MAC_ADDR_DUMP_WORDS_PER_ENTRY)
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/* Maximum of 4 functions whose semaphore registeres are
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* in the coredump.
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*/
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#define MAX_SEMAPHORE_FUNCTIONS 4
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/* Defines for access the MPI shadow registers. */
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#define RISC_124 0x0003007c
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#define RISC_127 0x0003007f
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#define SHADOW_OFFSET 0xb0000000
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#define SHADOW_REG_SHIFT 20
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struct ql_nic_misc {
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u32 rx_ring_count;
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u32 tx_ring_count;
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@ -1579,6 +1776,199 @@ struct ql_reg_dump {
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u32 ets[8+2];
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};
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struct ql_mpi_coredump {
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/* segment 0 */
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struct mpi_coredump_global_header mpi_global_header;
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/* segment 1 */
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struct mpi_coredump_segment_header core_regs_seg_hdr;
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u32 mpi_core_regs[MPI_CORE_REGS_CNT];
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u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
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/* segment 2 */
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struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
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u32 test_logic_regs[TEST_REGS_CNT];
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/* segment 3 */
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struct mpi_coredump_segment_header rmii_regs_seg_hdr;
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u32 rmii_regs[RMII_REGS_CNT];
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/* segment 4 */
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struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
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u32 fcmac1_regs[FCMAC_REGS_CNT];
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/* segment 5 */
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struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
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u32 fcmac2_regs[FCMAC_REGS_CNT];
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/* segment 6 */
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struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
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u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
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/* segment 7 */
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struct mpi_coredump_segment_header ide_regs_seg_hdr;
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u32 ide_regs[IDE_REGS_CNT];
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/* segment 8 */
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struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
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u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
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/* segment 9 */
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struct mpi_coredump_segment_header smbus_regs_seg_hdr;
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u32 smbus_regs[SMBUS_REGS_CNT];
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/* segment 10 */
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struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
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u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
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/* segment 11 */
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struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
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u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
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/* segment 12 */
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struct mpi_coredump_segment_header i2c_regs_seg_hdr;
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u32 i2c_regs[I2C_REGS_CNT];
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/* segment 13 */
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struct mpi_coredump_segment_header memc_regs_seg_hdr;
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u32 memc_regs[MEMC_REGS_CNT];
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/* segment 14 */
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struct mpi_coredump_segment_header pbus_regs_seg_hdr;
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u32 pbus_regs[PBUS_REGS_CNT];
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/* segment 15 */
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struct mpi_coredump_segment_header mde_regs_seg_hdr;
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u32 mde_regs[MDE_REGS_CNT];
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/* segment 16 */
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struct mpi_coredump_segment_header nic_regs_seg_hdr;
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u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
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/* segment 17 */
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struct mpi_coredump_segment_header nic2_regs_seg_hdr;
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u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
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/* segment 18 */
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struct mpi_coredump_segment_header xgmac1_seg_hdr;
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u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
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/* segment 19 */
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struct mpi_coredump_segment_header xgmac2_seg_hdr;
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u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
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/* segment 20 */
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struct mpi_coredump_segment_header code_ram_seg_hdr;
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u32 code_ram[CODE_RAM_CNT];
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/* segment 21 */
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struct mpi_coredump_segment_header memc_ram_seg_hdr;
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u32 memc_ram[MEMC_RAM_CNT];
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/* segment 22 */
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struct mpi_coredump_segment_header xaui_an_hdr;
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u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
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/* segment 23 */
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struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
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u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
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/* segment 24 */
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struct mpi_coredump_segment_header xfi_an_hdr;
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u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
|
||||
|
||||
/* segment 25 */
|
||||
struct mpi_coredump_segment_header xfi_train_hdr;
|
||||
u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
|
||||
|
||||
/* segment 26 */
|
||||
struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
|
||||
u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
|
||||
|
||||
/* segment 27 */
|
||||
struct mpi_coredump_segment_header xfi_hss_tx_hdr;
|
||||
u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
|
||||
|
||||
/* segment 28 */
|
||||
struct mpi_coredump_segment_header xfi_hss_rx_hdr;
|
||||
u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
|
||||
|
||||
/* segment 29 */
|
||||
struct mpi_coredump_segment_header xfi_hss_pll_hdr;
|
||||
u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
|
||||
|
||||
/* segment 30 */
|
||||
struct mpi_coredump_segment_header misc_nic_seg_hdr;
|
||||
struct ql_nic_misc misc_nic_info;
|
||||
|
||||
/* segment 31 */
|
||||
/* one interrupt state for each CQ */
|
||||
struct mpi_coredump_segment_header intr_states_seg_hdr;
|
||||
u32 intr_states[MAX_RX_RINGS];
|
||||
|
||||
/* segment 32 */
|
||||
/* 3 cam words each for 16 unicast,
|
||||
* 2 cam words for each of 32 multicast.
|
||||
*/
|
||||
struct mpi_coredump_segment_header cam_entries_seg_hdr;
|
||||
u32 cam_entries[(16 * 3) + (32 * 3)];
|
||||
|
||||
/* segment 33 */
|
||||
struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
|
||||
u32 nic_routing_words[16];
|
||||
/* segment 34 */
|
||||
struct mpi_coredump_segment_header ets_seg_hdr;
|
||||
u32 ets[ETS_REGS_DUMP_WORD_COUNT];
|
||||
|
||||
/* segment 35 */
|
||||
struct mpi_coredump_segment_header probe_dump_seg_hdr;
|
||||
u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
|
||||
|
||||
/* segment 36 */
|
||||
struct mpi_coredump_segment_header routing_reg_seg_hdr;
|
||||
u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
|
||||
|
||||
/* segment 37 */
|
||||
struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
|
||||
u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
|
||||
|
||||
/* segment 38 */
|
||||
struct mpi_coredump_segment_header xaui2_an_hdr;
|
||||
u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
|
||||
|
||||
/* segment 39 */
|
||||
struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
|
||||
u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
|
||||
|
||||
/* segment 40 */
|
||||
struct mpi_coredump_segment_header xfi2_an_hdr;
|
||||
u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
|
||||
|
||||
/* segment 41 */
|
||||
struct mpi_coredump_segment_header xfi2_train_hdr;
|
||||
u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
|
||||
|
||||
/* segment 42 */
|
||||
struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
|
||||
u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
|
||||
|
||||
/* segment 43 */
|
||||
struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
|
||||
u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
|
||||
|
||||
/* segment 44 */
|
||||
struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
|
||||
u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
|
||||
|
||||
/* segment 45 */
|
||||
struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
|
||||
u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
|
||||
|
||||
/* segment 50 */
|
||||
/* semaphore register for all 5 functions */
|
||||
struct mpi_coredump_segment_header sem_regs_seg_hdr;
|
||||
u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
|
||||
};
|
||||
|
||||
/*
|
||||
* intr_context structure is used during initialization
|
||||
* to hook the interrupts. It is also used in a single
|
||||
|
|
@ -1735,6 +2125,8 @@ struct ql_adapter {
|
|||
u32 port_link_up;
|
||||
u32 port_init;
|
||||
u32 link_status;
|
||||
struct ql_mpi_coredump *mpi_coredump;
|
||||
u32 core_is_dumped;
|
||||
u32 link_config;
|
||||
u32 led_config;
|
||||
u32 max_frame_size;
|
||||
|
|
@ -1747,6 +2139,7 @@ struct ql_adapter {
|
|||
struct delayed_work mpi_work;
|
||||
struct delayed_work mpi_port_cfg_work;
|
||||
struct delayed_work mpi_idc_work;
|
||||
struct delayed_work mpi_core_to_log;
|
||||
struct completion ide_completion;
|
||||
struct nic_operations *nic_ops;
|
||||
u16 device_id;
|
||||
|
|
|
|||
Loading…
Reference in New Issue