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drm/i915: IVB FBC WaFbcDisableDpfcClockGating 

Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
v4: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Rodrigo Vivi 2013-05-09 14:08:38 -03:00 committed by Daniel Vetter
parent 30ca7c6f97
commit b74ea102b7
1 changed files with 11 additions and 0 deletions
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11
drivers/gpu/drm/i915/intel_pm.c
View File

@ -242,6 +242,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
dpfc_ctl &= ~DPFC_CTL_EN;
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
if (IS_IVYBRIDGE(dev))
/* WaFbcDisableDpfcClockGating */
I915_WRITE(ILK_DSPCLK_GATE_D,
I915_READ(ILK_DSPCLK_GATE_D) &
~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
DRM_DEBUG_KMS("disabled FBC\n");
}
}
@ -270,6 +276,11 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
/* WaFbcAsynchFlipDisableFbcQueue */
I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
/* WaFbcDisableDpfcClockGating */
I915_WRITE(ILK_DSPCLK_GATE_D,
I915_READ(ILK_DSPCLK_GATE_D) |
ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | obj->fence_reg);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);