Merge branch 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, fpu: Merge fpu_save_init() x86-32, fpu: Rewrite fpu_save_init() x86, fpu: Remove PSHUFB_XMM5_* macros x86, fpu: Remove unnecessary ifdefs from i387 code. x86-32, fpu: Remove math_emulate stub x86-64, fpu: Simplify constraints for fxsave/fxtstor x86-64, fpu: Fix %cs value in convert_from_fxsr() x86-64, fpu: Disable preemption when using TS_USEDFPU x86, fpu: Merge __save_init_fpu() x86, fpu: Merge tolerant_fwait() x86, fpu: Merge fpu_init() x86: Use correct type for %cr4 x86, xsave: Disable xsave in i387 emulation mode Fixed up fxsaveq-induced conflict in arch/x86/include/asm/i387.h
This commit is contained in:
Linus Torvalds
commit
b6f7e38dbb
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@ -55,6 +55,12 @@ extern int save_i387_xstate_ia32(void __user *buf);
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extern int restore_i387_xstate_ia32(void __user *buf);
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#endif
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#ifdef CONFIG_MATH_EMULATION
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extern void finit_soft_fpu(struct i387_soft_struct *soft);
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#else
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static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
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#endif
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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static __always_inline __pure bool use_xsaveopt(void)
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@ -67,6 +73,11 @@ static __always_inline __pure bool use_xsave(void)
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return static_cpu_has(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has(X86_FEATURE_FXSR);
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}
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extern void __sanitize_i387_state(struct task_struct *);
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static inline void sanitize_i387_state(struct task_struct *tsk)
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@ -77,19 +88,11 @@ static inline void sanitize_i387_state(struct task_struct *tsk)
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}
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#ifdef CONFIG_X86_64
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/* Ignore delayed exceptions from user space */
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static inline void tolerant_fwait(void)
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{
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asm volatile("1: fwait\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b));
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}
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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int err;
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/* See comment in fxsave() below. */
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asm volatile("1: rex64/fxrstor (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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@ -98,44 +101,10 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err)
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#if 0 /* See comment in fxsave() below. */
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: [fx] "r" (fx), "m" (*fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
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#endif
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: [fx] "R" (fx), "m" (*fx), "0" (0));
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return err;
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}
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/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. The kernel data segment can be sometimes 0 and sometimes
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new user value. Both should be ok.
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Use the PDA as safe address because it should be already in L1. */
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static inline void fpu_clear(struct fpu *fpu)
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{
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struct xsave_struct *xstate = &fpu->state->xsave;
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struct i387_fxsave_struct *fx = &fpu->state->fxsave;
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (use_xsave() &&
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!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
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return;
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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alternative_input(ASM_NOP8 ASM_NOP2,
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" emms\n" /* clear stack tags */
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" fildl %%gs:0", /* load to clear state */
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X86_FEATURE_FXSAVE_LEAK);
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}
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static inline void clear_fpu_state(struct task_struct *tsk)
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{
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fpu_clear(&tsk->thread.fpu);
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}
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static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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{
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int err;
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@ -149,6 +118,7 @@ static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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if (unlikely(err))
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return -EFAULT;
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/* See comment in fxsave() below. */
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asm volatile("1: rex64/fxsave (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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@ -157,11 +127,7 @@ static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err), "=m" (*fx)
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#if 0 /* See comment in fxsave() below. */
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: [fx] "r" (fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "0" (0));
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#endif
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: [fx] "R" (fx), "0" (0));
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if (unlikely(err) &&
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__clear_user(fx, sizeof(struct i387_fxsave_struct)))
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err = -EFAULT;
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@ -175,56 +141,29 @@ static inline void fpu_fxsave(struct fpu *fpu)
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uses any extended registers for addressing, a second REX prefix
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will be generated (to the assembler, rex64 followed by semicolon
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is a separate instruction), and hence the 64-bitness is lost. */
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#ifdef CONFIG_AS_FXSAVEQ
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/* Using "fxsaveq %0" would be the ideal choice, but is only supported
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starting with gas 2.16. */
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__asm__ __volatile__("fxsaveq %0"
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: "=m" (fpu->state->fxsave));
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#elif 0
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#else
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/* Using, as a workaround, the properly prefixed form below isn't
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accepted by any binutils version so far released, complaining that
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the same type of prefix is used twice if an extended register is
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needed for addressing (fix submitted to mainline 2005-11-21). */
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__asm__ __volatile__("rex64/fxsave %0"
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: "=m" (fpu->state->fxsave));
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#else
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/* This, however, we can work around by forcing the compiler to select
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needed for addressing (fix submitted to mainline 2005-11-21).
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asm volatile("rex64/fxsave %0"
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: "=m" (fpu->state->fxsave));
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This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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__asm__ __volatile__("rex64/fxsave (%1)"
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: "=m" (fpu->state->fxsave)
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: "cdaSDb" (&fpu->state->fxsave));
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asm volatile("rex64/fxsave (%[fx])"
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: "=m" (fpu->state->fxsave)
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: [fx] "R" (&fpu->state->fxsave));
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#endif
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}
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static inline void fpu_save_init(struct fpu *fpu)
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{
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if (use_xsave())
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fpu_xsave(fpu);
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else
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fpu_fxsave(fpu);
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fpu_clear(fpu);
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}
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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fpu_save_init(&tsk->thread.fpu);
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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#else /* CONFIG_X86_32 */
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#ifdef CONFIG_MATH_EMULATION
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extern void finit_soft_fpu(struct i387_soft_struct *soft);
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#else
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static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
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#endif
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static inline void tolerant_fwait(void)
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{
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asm volatile("fnclex ; fwait");
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}
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/* perform fxrstor iff the processor has extended states, otherwise frstor */
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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@ -241,6 +180,14 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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return 0;
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}
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static inline void fpu_fxsave(struct fpu *fpu)
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{
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asm volatile("fxsave %[fx]"
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: [fx] "=m" (fpu->state->fxsave));
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}
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#endif /* CONFIG_X86_64 */
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/* We need a safe address that is cheap to find and that is already
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in L1 during context switch. The best choices are unfortunately
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different for UP and SMP */
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@ -256,47 +203,33 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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static inline void fpu_save_init(struct fpu *fpu)
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{
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if (use_xsave()) {
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struct xsave_struct *xstate = &fpu->state->xsave;
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struct i387_fxsave_struct *fx = &fpu->state->fxsave;
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fpu_xsave(fpu);
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
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goto end;
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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/*
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* we can do a simple return here or be paranoid :)
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*/
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goto clear_state;
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if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
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return;
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} else if (use_fxsr()) {
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fpu_fxsave(fpu);
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} else {
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asm volatile("fsave %[fx]; fwait"
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: [fx] "=m" (fpu->state->fsave));
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return;
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}
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/* Use more nops than strictly needed in case the compiler
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varies code */
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alternative_input(
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"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
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"fxsave %[fx]\n"
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"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
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X86_FEATURE_FXSR,
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[fx] "m" (fpu->state->fxsave),
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[fsw] "m" (fpu->state->fxsave.swd) : "memory");
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clear_state:
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if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES))
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asm volatile("fnclex");
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/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. safe_address is a random variable that should be in L1 */
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alternative_input(
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GENERIC_NOP8 GENERIC_NOP2,
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ASM_NOP8 ASM_NOP2,
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"emms\n\t" /* clear stack tags */
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"fildl %[addr]", /* set F?P to defined value */
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"fildl %P[addr]", /* set F?P to defined value */
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X86_FEATURE_FXSAVE_LEAK,
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[addr] "m" (safe_address));
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end:
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;
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}
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static inline void __save_init_fpu(struct task_struct *tsk)
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@ -305,9 +238,6 @@ static inline void __save_init_fpu(struct task_struct *tsk)
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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#endif /* CONFIG_X86_64 */
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static inline int fpu_fxrstor_checking(struct fpu *fpu)
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{
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return fxrstor_checking(&fpu->state->fxsave);
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@ -344,7 +274,10 @@ static inline void __unlazy_fpu(struct task_struct *tsk)
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static inline void __clear_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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tolerant_fwait();
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/* Ignore delayed exceptions from user space */
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asm volatile("1: fwait\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b));
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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stts();
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}
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@ -405,19 +338,6 @@ static inline void irq_ts_restore(int TS_state)
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stts();
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}
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#ifdef CONFIG_X86_64
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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__save_init_fpu(tsk);
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stts();
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}
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#define unlazy_fpu __unlazy_fpu
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#define clear_fpu __clear_fpu
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#else /* CONFIG_X86_32 */
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/*
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* These disable preemption on their own and are safe
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*/
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@ -443,8 +363,6 @@ static inline void clear_fpu(struct task_struct *tsk)
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preempt_enable();
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}
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#endif /* CONFIG_X86_64 */
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|
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/*
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* i387 state interaction
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*/
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||||
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@ -508,7 +426,4 @@ extern void fpu_finit(struct fpu *fpu);
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#endif /* __ASSEMBLY__ */
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|
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#define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
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#define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
|
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|
||||
#endif /* _ASM_X86_I387_H */
|
||||
|
|
|
|||
|
|
@ -604,7 +604,7 @@ extern unsigned long mmu_cr4_features;
|
|||
|
||||
static inline void set_in_cr4(unsigned long mask)
|
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{
|
||||
unsigned cr4;
|
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unsigned long cr4;
|
||||
|
||||
mmu_cr4_features |= mask;
|
||||
cr4 = read_cr4();
|
||||
|
|
@ -614,7 +614,7 @@ static inline void set_in_cr4(unsigned long mask)
|
|||
|
||||
static inline void clear_in_cr4(unsigned long mask)
|
||||
{
|
||||
unsigned cr4;
|
||||
unsigned long cr4;
|
||||
|
||||
mmu_cr4_features &= ~mask;
|
||||
cr4 = read_cr4();
|
||||
|
|
|
|||
|
|
@ -1269,13 +1269,6 @@ void __cpuinit cpu_init(void)
|
|||
clear_all_debug_regs();
|
||||
dbg_restore_debug_regs();
|
||||
|
||||
/*
|
||||
* Force FPU initialization:
|
||||
*/
|
||||
current_thread_info()->status = 0;
|
||||
clear_used_math();
|
||||
mxcsr_feature_mask_init();
|
||||
|
||||
fpu_init();
|
||||
xsave_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -68,19 +68,22 @@ static void __cpuinit init_thread_xstate(void)
|
|||
*/
|
||||
|
||||
if (!HAVE_HWFP) {
|
||||
/*
|
||||
* Disable xsave as we do not support it if i387
|
||||
* emulation is enabled.
|
||||
*/
|
||||
setup_clear_cpu_cap(X86_FEATURE_XSAVE);
|
||||
setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
|
||||
xstate_size = sizeof(struct i387_soft_struct);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cpu_has_fxsr)
|
||||
xstate_size = sizeof(struct i387_fxsave_struct);
|
||||
#ifdef CONFIG_X86_32
|
||||
else
|
||||
xstate_size = sizeof(struct i387_fsave_struct);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
/*
|
||||
* Called at bootup to set up the initial FPU state that is later cloned
|
||||
* into all processes.
|
||||
|
|
@ -88,12 +91,21 @@ static void __cpuinit init_thread_xstate(void)
|
|||
|
||||
void __cpuinit fpu_init(void)
|
||||
{
|
||||
unsigned long oldcr0 = read_cr0();
|
||||
unsigned long cr0;
|
||||
unsigned long cr4_mask = 0;
|
||||
|
||||
set_in_cr4(X86_CR4_OSFXSR);
|
||||
set_in_cr4(X86_CR4_OSXMMEXCPT);
|
||||
if (cpu_has_fxsr)
|
||||
cr4_mask |= X86_CR4_OSFXSR;
|
||||
if (cpu_has_xmm)
|
||||
cr4_mask |= X86_CR4_OSXMMEXCPT;
|
||||
if (cr4_mask)
|
||||
set_in_cr4(cr4_mask);
|
||||
|
||||
write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */
|
||||
cr0 = read_cr0();
|
||||
cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
|
||||
if (!HAVE_HWFP)
|
||||
cr0 |= X86_CR0_EM;
|
||||
write_cr0(cr0);
|
||||
|
||||
if (!smp_processor_id())
|
||||
init_thread_xstate();
|
||||
|
|
@ -104,24 +116,12 @@ void __cpuinit fpu_init(void)
|
|||
clear_used_math();
|
||||
}
|
||||
|
||||
#else /* CONFIG_X86_64 */
|
||||
|
||||
void __cpuinit fpu_init(void)
|
||||
{
|
||||
if (!smp_processor_id())
|
||||
init_thread_xstate();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_X86_32 */
|
||||
|
||||
void fpu_finit(struct fpu *fpu)
|
||||
{
|
||||
#ifdef CONFIG_X86_32
|
||||
if (!HAVE_HWFP) {
|
||||
finit_soft_fpu(&fpu->state->soft);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (cpu_has_fxsr) {
|
||||
struct i387_fxsave_struct *fx = &fpu->state->fxsave;
|
||||
|
|
@ -386,19 +386,17 @@ convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
|
|||
#ifdef CONFIG_X86_64
|
||||
env->fip = fxsave->rip;
|
||||
env->foo = fxsave->rdp;
|
||||
/*
|
||||
* should be actually ds/cs at fpu exception time, but
|
||||
* that information is not available in 64bit mode.
|
||||
*/
|
||||
env->fcs = task_pt_regs(tsk)->cs;
|
||||
if (tsk == current) {
|
||||
/*
|
||||
* should be actually ds/cs at fpu exception time, but
|
||||
* that information is not available in 64bit mode.
|
||||
*/
|
||||
asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos));
|
||||
asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs));
|
||||
savesegment(ds, env->fos);
|
||||
} else {
|
||||
struct pt_regs *regs = task_pt_regs(tsk);
|
||||
|
||||
env->fos = 0xffff0000 | tsk->thread.ds;
|
||||
env->fcs = regs->cs;
|
||||
env->fos = tsk->thread.ds;
|
||||
}
|
||||
env->fos |= 0xffff0000;
|
||||
#else
|
||||
env->fip = fxsave->fip;
|
||||
env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
|
||||
|
|
|
|||
|
|
@ -424,7 +424,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
|
|||
load_TLS(next, cpu);
|
||||
|
||||
/* Must be after DS reload */
|
||||
unlazy_fpu(prev_p);
|
||||
__unlazy_fpu(prev_p);
|
||||
|
||||
/* Make sure cpu is ready for new context */
|
||||
if (preload_fpu)
|
||||
|
|
|
|||
|
|
@ -776,21 +776,10 @@ asmlinkage void math_state_restore(void)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(math_state_restore);
|
||||
|
||||
#ifndef CONFIG_MATH_EMULATION
|
||||
void math_emulate(struct math_emu_info *info)
|
||||
{
|
||||
printk(KERN_EMERG
|
||||
"math-emulation not enabled and no coprocessor found.\n");
|
||||
printk(KERN_EMERG "killing %s.\n", current->comm);
|
||||
force_sig(SIGFPE, current);
|
||||
schedule();
|
||||
}
|
||||
#endif /* CONFIG_MATH_EMULATION */
|
||||
|
||||
dotraplinkage void __kprobes
|
||||
do_device_not_available(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
#ifdef CONFIG_X86_32
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
if (read_cr0() & X86_CR0_EM) {
|
||||
struct math_emu_info info = { };
|
||||
|
||||
|
|
@ -798,12 +787,12 @@ do_device_not_available(struct pt_regs *regs, long error_code)
|
|||
|
||||
info.regs = regs;
|
||||
math_emulate(&info);
|
||||
} else {
|
||||
math_state_restore(); /* interrupts still off */
|
||||
conditional_sti(regs);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
math_state_restore();
|
||||
#endif
|
||||
math_state_restore(); /* interrupts still off */
|
||||
#ifdef CONFIG_X86_32
|
||||
conditional_sti(regs);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -881,18 +870,6 @@ void __init trap_init(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
if (cpu_has_fxsr) {
|
||||
printk(KERN_INFO "Enabling fast FPU save and restore... ");
|
||||
set_in_cr4(X86_CR4_OSFXSR);
|
||||
printk("done.\n");
|
||||
}
|
||||
if (cpu_has_xmm) {
|
||||
printk(KERN_INFO
|
||||
"Enabling unmasked SIMD FPU exception support... ");
|
||||
set_in_cr4(X86_CR4_OSXMMEXCPT);
|
||||
printk("done.\n");
|
||||
}
|
||||
|
||||
set_system_trap_gate(SYSCALL_VECTOR, &system_call);
|
||||
set_bit(SYSCALL_VECTOR, used_vectors);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue