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MIPS: Netlogic: Avoid unnecessary cache flushes 

XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C 2011-08-23 13:35:51 +05:30 committed by Ralf Baechle
parent 11d48aace2
commit b66f953cd0
1 changed files with 2 additions and 3 deletions
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5
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
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@ -25,13 +25,12 @@
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_mips32r1 1