Merge series "ASoC: stm32: i2s: add master clock provider" from Olivier Moysan <olivier.moysan@foss.st.com>:
Add master clock generation support in STM32 I2S driver. Resend of patch https://lkml.org/lkml/2020/9/11/264 Olivier Moysan (2): ASoC: dt-bindings: add mclk provider support to stm32 i2s ASoC: stm32: i2s: add master clock provider .../bindings/sound/st,stm32-i2s.yaml | 4 + sound/soc/stm/stm32_i2s.c | 310 +++++++++++++++--- 2 files changed, 270 insertions(+), 44 deletions(-) -- 2.17.1
This commit is contained in:
Mark Brown
commit
b6040f9b98
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@ -54,6 +54,10 @@ properties:
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resets:
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maxItems: 1
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"#clock-cells":
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description: Configure the I2S device as MCLK clock provider.
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const: 0
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required:
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- compatible
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- "#sound-dai-cells"
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@ -8,6 +8,7 @@
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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@ -196,6 +197,9 @@ enum i2s_datlen {
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#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
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#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
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#define STM32_I2S_NAME_LEN 32
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#define STM32_I2S_RATE_11K 11025
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/**
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* struct stm32_i2s_data - private data of I2S
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* @regmap_conf: I2S register map configuration pointer
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@ -206,6 +210,7 @@ enum i2s_datlen {
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* @dma_data_rx: dma configuration data for tx channel
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* @substream: PCM substream data pointer
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* @i2sclk: kernel clock feeding the I2S clock generator
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* @i2smclk: master clock from I2S mclk provider
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* @pclk: peripheral clock driving bus interface
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* @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
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* @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
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@ -215,6 +220,9 @@ enum i2s_datlen {
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* @irq_lock: prevent race condition with IRQ
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* @mclk_rate: master clock frequency (Hz)
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* @fmt: DAI protocol
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* @divider: prescaler division ratio
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* @div: prescaler div field
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* @odd: prescaler odd field
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* @refcount: keep count of opened streams on I2S
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* @ms_flg: master mode flag.
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*/
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@ -227,6 +235,7 @@ struct stm32_i2s_data {
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struct snd_dmaengine_dai_dma_data dma_data_rx;
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struct snd_pcm_substream *substream;
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struct clk *i2sclk;
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struct clk *i2smclk;
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struct clk *pclk;
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struct clk *x8kclk;
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struct clk *x11kclk;
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@ -236,10 +245,210 @@ struct stm32_i2s_data {
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spinlock_t irq_lock; /* used to prevent race condition with IRQ */
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unsigned int mclk_rate;
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unsigned int fmt;
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unsigned int divider;
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unsigned int div;
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bool odd;
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int refcount;
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int ms_flg;
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};
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struct stm32_i2smclk_data {
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struct clk_hw hw;
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unsigned long freq;
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struct stm32_i2s_data *i2s_data;
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};
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#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
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static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
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unsigned long input_rate,
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unsigned long output_rate)
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{
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unsigned int ratio, div, divider = 1;
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bool odd;
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ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
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/* Check the parity of the divider */
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odd = ratio & 0x1;
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/* Compute the div prescaler */
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div = ratio >> 1;
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/* If div is 0 actual divider is 1 */
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if (div) {
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divider = ((2 * div) + odd);
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dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
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div, odd, divider);
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}
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/* Division by three is not allowed by I2S prescaler */
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if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
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dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
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return -EINVAL;
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}
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if (input_rate % divider)
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dev_dbg(&i2s->pdev->dev,
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"Rate not accurate. requested (%ld), actual (%ld)\n",
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output_rate, input_rate / divider);
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i2s->div = div;
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i2s->odd = odd;
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i2s->divider = divider;
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return 0;
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}
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static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
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{
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u32 cgfr, cgfr_mask;
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cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
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cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
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return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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cgfr_mask, cgfr);
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}
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static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
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unsigned int rate)
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{
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struct platform_device *pdev = i2s->pdev;
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struct clk *parent_clk;
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int ret;
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if (!(rate % STM32_I2S_RATE_11K))
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parent_clk = i2s->x11kclk;
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else
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parent_clk = i2s->x8kclk;
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ret = clk_set_parent(i2s->i2sclk, parent_clk);
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if (ret)
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dev_err(&pdev->dev,
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"Error %d setting i2sclk parent clock\n", ret);
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return ret;
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}
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static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
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struct stm32_i2s_data *i2s = mclk->i2s_data;
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int ret;
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ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
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if (ret)
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return ret;
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mclk->freq = *prate / i2s->divider;
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return mclk->freq;
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}
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static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
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return mclk->freq;
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}
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static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
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struct stm32_i2s_data *i2s = mclk->i2s_data;
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int ret;
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ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
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if (ret)
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return ret;
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ret = stm32_i2s_set_clk_div(i2s);
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if (ret)
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return ret;
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mclk->freq = rate;
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return 0;
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}
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static int stm32_i2smclk_enable(struct clk_hw *hw)
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{
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struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
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struct stm32_i2s_data *i2s = mclk->i2s_data;
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dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
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return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
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}
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static void stm32_i2smclk_disable(struct clk_hw *hw)
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{
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struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
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struct stm32_i2s_data *i2s = mclk->i2s_data;
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dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
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regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
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}
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static const struct clk_ops mclk_ops = {
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.enable = stm32_i2smclk_enable,
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.disable = stm32_i2smclk_disable,
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.recalc_rate = stm32_i2smclk_recalc_rate,
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.round_rate = stm32_i2smclk_round_rate,
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.set_rate = stm32_i2smclk_set_rate,
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};
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static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
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{
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struct clk_hw *hw;
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struct stm32_i2smclk_data *mclk;
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struct device *dev = &i2s->pdev->dev;
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const char *pname = __clk_get_name(i2s->i2sclk);
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char *mclk_name, *p, *s = (char *)pname;
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int ret, i = 0;
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mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
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if (!mclk)
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return -ENOMEM;
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mclk_name = devm_kcalloc(dev, sizeof(char),
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STM32_I2S_NAME_LEN, GFP_KERNEL);
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if (!mclk_name)
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return -ENOMEM;
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/*
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* Forge mclk clock name from parent clock name and suffix.
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* String after "_" char is stripped in parent name.
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*/
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p = mclk_name;
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while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
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*p++ = *s++;
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i++;
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}
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strcat(p, "_mclk");
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mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
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mclk->i2s_data = i2s;
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hw = &mclk->hw;
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dev_dbg(dev, "Register master clock %s\n", mclk_name);
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ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
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if (ret) {
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dev_err(dev, "mclk register fails with error %d\n", ret);
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return ret;
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}
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i2s->i2smclk = hw->clk;
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/* register mclk provider */
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
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}
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static irqreturn_t stm32_i2s_isr(int irq, void *devid)
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{
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struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
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@ -405,18 +614,46 @@ static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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int ret = 0;
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dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
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dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
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freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
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dir ? "output" : "input");
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if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
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i2s->mclk_rate = freq;
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/* MCLK generation is available only in master mode */
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if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
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if (!i2s->i2smclk) {
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dev_dbg(cpu_dai->dev, "No MCLK registered\n");
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return 0;
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}
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/* Enable master clock if master mode and mclk-fs are set */
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return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
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/* Assume shutdown if requested frequency is 0Hz */
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if (!freq) {
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/* Release mclk rate only if rate was actually set */
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if (i2s->mclk_rate) {
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clk_rate_exclusive_put(i2s->i2smclk);
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i2s->mclk_rate = 0;
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}
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return regmap_update_bits(i2s->regmap,
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STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, 0);
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}
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/* If master clock is used, set parent clock now */
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ret = stm32_i2s_set_parent_clock(i2s, freq);
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if (ret)
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return ret;
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ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
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if (ret) {
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dev_err(cpu_dai->dev, "Could not set mclk rate\n");
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return ret;
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}
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ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
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if (!ret)
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i2s->mclk_rate = freq;
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}
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return 0;
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return ret;
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}
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static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
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@ -424,11 +661,10 @@ static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
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{
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned long i2s_clock_rate;
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unsigned int tmp, div, real_div, nb_bits, frame_len;
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unsigned int nb_bits, frame_len;
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unsigned int rate = params_rate(params);
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u32 cgfr;
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int ret;
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u32 cgfr, cgfr_mask;
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bool odd;
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if (!(rate % 11025))
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clk_set_parent(i2s->i2sclk, i2s->x11kclk);
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@ -449,7 +685,10 @@ static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
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* dsp mode : div = i2s_clk / (nb_bits x ws)
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*/
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if (i2s->mclk_rate) {
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tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
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ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
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i2s->mclk_rate);
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if (ret)
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return ret;
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} else {
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frame_len = 32;
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if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
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@ -462,34 +701,13 @@ static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
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return ret;
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nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
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tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
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ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
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(nb_bits * rate));
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if (ret)
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return ret;
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}
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/* Check the parity of the divider */
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odd = tmp & 0x1;
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/* Compute the div prescaler */
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div = tmp >> 1;
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cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
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cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
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real_div = ((2 * div) + odd);
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dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
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i2s_clock_rate, rate);
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dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
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div, odd, real_div);
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if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
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dev_err(cpu_dai->dev, "Wrong divider setting\n");
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return -EINVAL;
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}
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if (!div && !odd)
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dev_warn(cpu_dai->dev, "real divider forced to 1\n");
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ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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cgfr_mask, cgfr);
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ret = stm32_i2s_set_clk_div(i2s);
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if (ret < 0)
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return ret;
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@ -694,9 +912,6 @@ static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
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struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned long flags;
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regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
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clk_disable_unprepare(i2s->i2sclk);
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spin_lock_irqsave(&i2s->irq_lock, flags);
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@ -861,6 +1076,13 @@ static int stm32_i2s_parse_dt(struct platform_device *pdev,
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return PTR_ERR(i2s->x11kclk);
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}
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/* Register mclk provider if requested */
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if (of_find_property(np, "#clock-cells", NULL)) {
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ret = stm32_i2s_add_mclk_provider(i2s);
|
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if (ret < 0)
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return ret;
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}
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/* Get irqs */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
|
|
@ -906,16 +1128,16 @@ static int stm32_i2s_probe(struct platform_device *pdev)
|
|||
if (!i2s)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = stm32_i2s_parse_dt(pdev, i2s);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
i2s->pdev = pdev;
|
||||
i2s->ms_flg = I2S_MS_NOT_SET;
|
||||
spin_lock_init(&i2s->lock_fd);
|
||||
spin_lock_init(&i2s->irq_lock);
|
||||
platform_set_drvdata(pdev, i2s);
|
||||
|
||||
ret = stm32_i2s_parse_dt(pdev, i2s);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = stm32_i2s_dais_init(pdev, i2s);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
Loading…
Reference in New Issue