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Merge remote-tracking branch 'spi/topic/rspi' into spi-pdata 

Conflicts:
	drivers/spi/spi-rspi.c
This commit is contained in:
Mark Brown 2013-08-29 13:59:05 +01:00
parent a1216394e6 8d4d08ce83
commit b5f9a9d511
977 changed files with 10456 additions and 98571 deletions
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17
Documentation/ABI/testing/sysfs-driver-xen-blkback Normal file
View File

@ -0,0 +1,17 @@
What: /sys/module/xen_blkback/parameters/max_buffer_pages
Date: March 2013
KernelVersion: 3.11
Contact: Roger Pau Monné <roger.pau@citrix.com>
Description:
Maximum number of free pages to keep in each block
backend buffer.
What: /sys/module/xen_blkback/parameters/max_persistent_grants
Date: March 2013
KernelVersion: 3.11
Contact: Roger Pau Monné <roger.pau@citrix.com>
Description:
Maximum number of grants to map persistently in
blkback. If the frontend tries to use more than
max_persistent_grants, the LRU kicks in and starts
removing 5% of max_persistent_grants every 100ms.

10
Documentation/ABI/testing/sysfs-driver-xen-blkfront Normal file
View File

@ -0,0 +1,10 @@
What: /sys/module/xen_blkfront/parameters/max
Date: June 2013
KernelVersion: 3.11
Contact: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Description:
Maximum number of segments that the frontend will negotiate
with the backend for indirect descriptors. The default value
is 32 - higher value means more potential throughput but more
memory usage. The backend picks the minimum of the frontend
and its default backend value.

37
Documentation/bcache.txt
View File

@ -46,29 +46,33 @@ you format your backing devices and cache device at the same time, you won't
have to manually attach:
make-bcache -B /dev/sda /dev/sdb -C /dev/sdc
To make bcache devices known to the kernel, echo them to /sys/fs/bcache/register:
bcache-tools now ships udev rules, and bcache devices are known to the kernel
immediately. Without udev, you can manually register devices like this:
echo /dev/sdb > /sys/fs/bcache/register
echo /dev/sdc > /sys/fs/bcache/register
To register your bcache devices automatically, you could add something like
this to an init script:
Registering the backing device makes the bcache device show up in /dev; you can
now format it and use it as normal. But the first time using a new bcache
device, it'll be running in passthrough mode until you attach it to a cache.
See the section on attaching.
echo /dev/sd* > /sys/fs/bcache/register_quiet
The devices show up as:
It'll look for bcache superblocks and ignore everything that doesn't have one.
/dev/bcache<N>
Registering the backing device makes the bcache show up in /dev; you can now
format it and use it as normal. But the first time using a new bcache device,
it'll be running in passthrough mode until you attach it to a cache. See the
section on attaching.
As well as (with udev):
The devices show up at /dev/bcacheN, and can be controlled via sysfs from
/sys/block/bcacheN/bcache:
/dev/bcache/by-uuid/<uuid>
/dev/bcache/by-label/<label>
To get started:
mkfs.ext4 /dev/bcache0
mount /dev/bcache0 /mnt
You can control bcache devices through sysfs at /sys/block/bcache<N>/bcache .
Cache devices are managed as sets; multiple caches per set isn't supported yet
but will allow for mirroring of metadata and dirty data in the future. Your new
cache set shows up as /sys/fs/bcache/<UUID>
@ -80,11 +84,11 @@ must be attached to your cache set to enable caching. Attaching a backing
device to a cache set is done thusly, with the UUID of the cache set in
/sys/fs/bcache:
echo <UUID> > /sys/block/bcache0/bcache/attach
echo <CSET-UUID> > /sys/block/bcache0/bcache/attach
This only has to be done once. The next time you reboot, just reregister all
your bcache devices. If a backing device has data in a cache somewhere, the
/dev/bcache# device won't be created until the cache shows up - particularly
/dev/bcache<N> device won't be created until the cache shows up - particularly
important if you have writeback caching turned on.
If you're booting up and your cache device is gone and never coming back, you
@ -191,6 +195,9 @@ want for getting the best possible numbers when benchmarking.
SYSFS - BACKING DEVICE:
Available at /sys/block/<bdev>/bcache, /sys/block/bcache*/bcache and
(if attached) /sys/fs/bcache/<cset-uuid>/bdev*
attach
Echo the UUID of a cache set to this file to enable caching.
@ -300,6 +307,8 @@ cache_readaheads
SYSFS - CACHE SET:
Available at /sys/fs/bcache/<cset-uuid>
average_key_size
Average data per key in the btree.
@ -390,6 +399,8 @@ trigger_gc
SYSFS - CACHE DEVICE:
Available at /sys/block/<cdev>/bcache
block_size
Minimum granularity of writes - should match hardware sector size.

4
Documentation/cpu-hotplug.txt
View File

@ -267,7 +267,7 @@ Q: If i have some kernel code that needs to be aware of CPU arrival and
A: This is what you would need in your kernel code to receive notifications.
#include <linux/cpu.h>
static int __cpuinit foobar_cpu_callback(struct notifier_block *nfb,
static int foobar_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned long)hcpu;
@ -285,7 +285,7 @@ A: This is what you would need in your kernel code to receive notifications.
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata foobar_cpu_notifer =
static struct notifier_block foobar_cpu_notifer =
{
.notifier_call = foobar_cpu_callback,
};

1
Documentation/devicetree/bindings/clock/imx27-clock.txt
View File

@ -98,6 +98,7 @@ clocks and IDs.
fpm 83
mpll_osc_sel 84
mpll_sel 85
spll_gate 86
Examples:

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -26,6 +26,7 @@ est ESTeem Wireless Modems
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
hisilicon Hisilicon Limited.
hp Hewlett Packard
ibm International Business Machines (IBM)
idt Integrated Device Technologies, Inc.
@ -43,6 +44,7 @@ nxp NXP Semiconductors
onnn ON Semiconductor Corp.
picochip Picochip Ltd
powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc.
qcom Qualcomm, Inc.
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International

42
Documentation/ja_JP/HOWTO
View File

@ -11,14 +11,14 @@ for non English (read: Japanese) speakers and is not intended as a
fork. So if you have any comments or updates for this file, please try
to update the original English file first.
Last Updated: 2011/03/31
Last Updated: 2013/07/19
==================================
これは、
linux-2.6.38/Documentation/HOWTO
linux-3.10/Documentation/HOWTO
の和訳です。
翻訳団体： JF プロジェクト < http://www.linux.or.jp/JF/ >
翻訳日： 2011/3/28
翻訳団体： JF プロジェクト < http://linuxjf.sourceforge.jp/ >
翻訳日： 2013/7/19
翻訳者： Tsugikazu Shibata <tshibata at ab dot jp dot nec dot com>
校正者： 松倉さん <nbh--mats at nifty dot com>
小林 雅典さん (Masanori Kobayasi) <zap03216 at nifty dot ne dot jp>
@ -245,7 +245,7 @@ Linux カーネルソースツリーの中に含まれる、きれいにし、
自己参照方式で、索引がついた web 形式で、ソースコードを参照することが
できます。この最新の素晴しいカーネルコードのリポジトリは以下で見つかり
ます-
http://sosdg.org/~qiyong/lxr/
http://lxr.linux.no/+trees
開発プロセス
-----------------------
@ -253,17 +253,17 @@ Linux カーネルソースツリーの中に含まれる、きれいにし、
Linux カーネルの開発プロセスは現在幾つかの異なるメインカーネル「ブラン
チ」と多数のサブシステム毎のカーネルブランチから構成されます。
これらのブランチとは-
- メインの 2.6.x カーネルツリー
- 2.6.x.y -stable カーネルツリー
- 2.6.x -git カーネルパッチ
- メインの 3.x カーネルツリー
- 3.x.y -stable カーネルツリー
- 3.x -git カーネルパッチ
- サブシステム毎のカーネルツリーとパッチ
- 統合テストのための 2.6.x -next カーネルツリー
- 統合テストのための 3.x -next カーネルツリー
2.6.x カーネルツリー
3.x カーネルツリー
-----------------
2.6.x カーネルは Linus Torvalds によってメンテナンスされ、kernel.org
の pub/linux/kernel/v2.6/ ディレクトリに存在します。この開発プロセスは
3.x カーネルは Linus Torvalds によってメンテナンスされ、kernel.org
の pub/linux/kernel/v3.x/ ディレクトリに存在します。この開発プロセスは
以下のとおり-
- 新しいカーネルがリリースされた直後に、2週間の特別期間が設けられ、
@ -302,20 +302,20 @@ Andrew Morton が Linux-kernel メーリングリストにカーネルリリー
実に認識されたバグの状況によりリリースされるのであり、前もって決めら
れた計画によってリリースされるものではないからです。」
2.6.x.y -stable カーネルツリー
3.x.y -stable カーネルツリー
---------------------------
バージョン番号が4つの数字に分かれているカーネルは -stable カーネルです。
これには、2.6.x カーネルで見つかったセキュリティ問題や重大な後戻りに対
バージョン番号が3つの数字に分かれているカーネルは -stable カーネルです。
これには、3.x カーネルで見つかったセキュリティ問題や重大な後戻りに対
する比較的小さい重要な修正が含まれます。
これは、開発/実験的バージョンのテストに協力することに興味が無く、
最新の安定したカーネルを使いたいユーザに推奨するブランチです。
もし、2.6.x.y カーネルが存在しない場合には、番号が一番大きい 2.6.x が
もし、3.x.y カーネルが存在しない場合には、番号が一番大きい 3.x が
最新の安定版カーネルです。
2.6.x.y は "stable" チーム <stable@kernel.org> でメンテされており、必
3.x.y は "stable" チーム <stable@kernel.org> でメンテされており、必
要に応じてリリースされます。通常のリリース期間は 2週間毎ですが、差し迫っ
た問題がなければもう少し長くなることもあります。セキュリティ関連の問題
の場合はこれに対してだいたいの場合、すぐにリリースがされます。
@ -324,7 +324,7 @@ Andrew Morton が Linux-kernel メーリングリストにカーネルリリー
イルにはどのような種類の変更が -stable ツリーに受け入れ可能か、またリ
リースプロセスがどう動くかが記述されています。
2.6.x -git パッチ
3.x -git パッチ
------------------
git リポジトリで管理されているLinus のカーネルツリーの毎日のスナップ
@ -358,14 +358,14 @@ quilt シリーズとして公開されているパッチキューも使われ
をつけることができます。大部分のこれらの patchwork のサイトは
http://patchwork.kernel.org/ でリストされています。
統合テストのための 2.6.x -next カーネルツリー
統合テストのための 3.x -next カーネルツリー
---------------------------------------------
サブシステムツリーの更新内容がメインラインの 2.6.x ツリーにマージされ
サブシステムツリーの更新内容がメインラインの 3.x ツリーにマージされ
る前に、それらは統合テストされる必要があります。この目的のため、実質的
に全サブシステムツリーからほぼ毎日プルされてできる特別なテスト用のリ
ポジトリが存在します-
http://git.kernel.org/?p=linux/kernel/git/sfr/linux-next.git
http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git
http://linux.f-seidel.de/linux-next/pmwiki/
このやり方によって、-next カーネルは次のマージ機会でどんなものがメイン

36
MAINTAINERS
View File

@ -1642,7 +1642,7 @@ S: Maintained
F: drivers/net/hamradio/baycom*
BCACHE (BLOCK LAYER CACHE)
M: Kent Overstreet <koverstreet@google.com>
M: Kent Overstreet <kmo@daterainc.com>
L: linux-bcache@vger.kernel.org
W: http://bcache.evilpiepirate.org
S: Maintained:
@ -3346,7 +3346,7 @@ F: Documentation/firmware_class/
F: drivers/base/firmware*.c
F: include/linux/firmware.h
FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card)
FLASH ADAPTER DRIVER (IBM Flash Adapter 900GB Full Height PCI Flash Card)
M: Joshua Morris <josh.h.morris@us.ibm.com>
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
S: Maintained
@ -3622,11 +3622,9 @@ F: drivers/isdn/gigaset/
F: include/uapi/linux/gigaset_dev.h
GPIO SUBSYSTEM
M: Grant Likely <grant.likely@linaro.org>
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
L: linux-gpio@vger.kernel.org
T: git git://git.secretlab.ca/git/linux-2.6.git
F: Documentation/gpio.txt
F: drivers/gpio/
F: include/linux/gpio*
@ -4472,8 +4470,6 @@ F: drivers/irqchip/
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
M: Grant Likely <grant.likely@linaro.org>
T: git git://git.secretlab.ca/git/linux-2.6.git irqdomain/next
S: Maintained
F: Documentation/IRQ-domain.txt
F: include/linux/irqdomain.h
@ -4990,7 +4986,7 @@ F: arch/powerpc/platforms/44x/
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
L: linuxppc-dev@lists.ozlabs.org
S: Unmaintained
S: Orphan
F: arch/powerpc/*/*virtex*
F: arch/powerpc/*/*/*virtex*
@ -5886,7 +5882,7 @@ OMAP DEVICE TREE SUPPORT
M: Benoît Cousson <b-cousson@ti.com>
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
L: devicetree-discuss@lists.ozlabs.org (moderated for non-subscribers)
L: devicetree@vger.kernel.org
S: Maintained
F: arch/arm/boot/dts/*omap*
F: arch/arm/boot/dts/*am3*
@ -6050,17 +6046,28 @@ F: drivers/i2c/busses/i2c-ocores.c
OPEN FIRMWARE AND FLATTENED DEVICE TREE
M: Grant Likely <grant.likely@linaro.org>
M: Rob Herring <rob.herring@calxeda.com>
L: devicetree-discuss@lists.ozlabs.org (moderated for non-subscribers)
L: devicetree@vger.kernel.org
W: http://fdt.secretlab.ca
T: git git://git.secretlab.ca/git/linux-2.6.git
S: Maintained
F: Documentation/devicetree
F: drivers/of
F: drivers/of/
F: include/linux/of*.h
F: scripts/dtc
F: scripts/dtc/
K: of_get_property
K: of_match_table
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
M: Rob Herring <rob.herring@calxeda.com>
M: Pawel Moll <pawel.moll@arm.com>
M: Mark Rutland <mark.rutland@arm.com>
M: Stephen Warren <swarren@wwwdotorg.org>
M: Ian Campbell <ian.campbell@citrix.com>
L: devicetree@vger.kernel.org
S: Maintained
F: Documentation/devicetree/
F: arch/*/boot/dts/
F: include/dt-bindings/
OPENRISC ARCHITECTURE
M: Jonas Bonn <jonas@southpole.se>
W: http://openrisc.net
@ -7746,7 +7753,6 @@ F: drivers/clk/spear/
SPI SUBSYSTEM
M: Mark Brown <broonie@kernel.org>
M: Grant Likely <grant.likely@linaro.org>
L: linux-spi@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
Q: http://patchwork.kernel.org/project/spi-devel-general/list/
@ -7812,7 +7818,7 @@ F: drivers/staging/asus_oled/
STAGING - COMEDI
M: Ian Abbott <abbotti@mev.co.uk>
M: Mori Hess <fmhess@users.sourceforge.net>
M: H Hartley Sweeten <hsweeten@visionengravers.com>
S: Odd Fixes
F: drivers/staging/comedi/
@ -9288,7 +9294,7 @@ S: Maintained
F: drivers/net/ethernet/xilinx/xilinx_axienet*
XILINX SYSTEMACE DRIVER
S: Unmaintained
S: Orphan
F: drivers/block/xsysace.c
XILINX UARTLITE SERIAL DRIVER

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 11
SUBLEVEL = 0
EXTRAVERSION = -rc1
EXTRAVERSION = -rc3
NAME = Linux for Workgroups
# *DOCUMENTATION*

1
arch/alpha/Kconfig
View File

@ -15,6 +15,7 @@ config ALPHA
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_IPC_PARSE_VERSION
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select GENERIC_SMP_IDLE_THREAD
select GENERIC_CMOS_UPDATE
select GENERIC_STRNCPY_FROM_USER

86
arch/alpha/include/asm/atomic.h
View File

@ -186,17 +186,24 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
*/
static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
}
return c;
int c, new, old;
smp_mb();
__asm__ __volatile__(
"1: ldl_l %[old],%[mem]\n"
" cmpeq %[old],%[u],%[c]\n"
" addl %[old],%[a],%[new]\n"
" bne %[c],2f\n"
" stl_c %[new],%[mem]\n"
" beq %[new],3f\n"
"2:\n"
".subsection 2\n"
"3: br 1b\n"
".previous"
: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u)
: "memory");
smp_mb();
return old;
}
@ -207,21 +214,56 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
* @u: ...unless v is equal to u.
*
* Atomically adds @a to @v, so long as it was not @u.
* Returns the old value of @v.
* Returns true iff @v was not @u.
*/
static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
{
long c, old;
c = atomic64_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic64_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
long c, tmp;
smp_mb();
__asm__ __volatile__(
"1: ldq_l %[tmp],%[mem]\n"
" cmpeq %[tmp],%[u],%[c]\n"
" addq %[tmp],%[a],%[tmp]\n"
" bne %[c],2f\n"
" stq_c %[tmp],%[mem]\n"
" beq %[tmp],3f\n"
"2:\n"
".subsection 2\n"
"3: br 1b\n"
".previous"
: [tmp] "=&r"(tmp), [c] "=&r"(c)
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u)
: "memory");
smp_mb();
return !c;
}
return c != (u);
/*
* atomic64_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic_t
*
* The function returns the old value of *v minus 1, even if
* the atomic variable, v, was not decremented.
*/
static inline long atomic64_dec_if_positive(atomic64_t *v)
{
long old, tmp;
smp_mb();
__asm__ __volatile__(
"1: ldq_l %[old],%[mem]\n"
" subq %[old],1,%[tmp]\n"
" ble %[old],2f\n"
" stq_c %[tmp],%[mem]\n"
" beq %[tmp],3f\n"
"2:\n"
".subsection 2\n"
"3: br 1b\n"
".previous"
: [old] "=&r"(old), [tmp] "=&r"(tmp)
: [mem] "m"(*v)
: "memory");
smp_mb();
return old - 1;
}
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)

6
arch/alpha/include/asm/param.h
View File

@ -3,7 +3,9 @@
#include <uapi/asm/param.h>
# undef HZ
# define HZ CONFIG_HZ
#define USER_HZ HZ
# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */
# define USER_HZ 1024
# define CLOCKS_PER_SEC USER_HZ /* frequency at which times() counts */
#endif /* _ASM_ALPHA_PARAM_H */

4
arch/alpha/include/asm/spinlock.h
View File

@ -168,8 +168,4 @@ static inline void arch_write_unlock(arch_rwlock_t * lock)
#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
#define arch_spin_relax(lock) cpu_relax()
#define arch_read_relax(lock) cpu_relax()
#define arch_write_relax(lock) cpu_relax()
#endif /* _ALPHA_SPINLOCK_H */

3
arch/alpha/include/asm/unistd.h
View File

@ -3,8 +3,7 @@
#include <uapi/asm/unistd.h>
#define NR_SYSCALLS 506
#define NR_SYSCALLS 508
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_STAT64

7
arch/alpha/include/uapi/asm/param.h
View File

@ -1,13 +1,7 @@
#ifndef _UAPI_ASM_ALPHA_PARAM_H
#define _UAPI_ASM_ALPHA_PARAM_H
/* ??? Gross. I don't want to parameterize this, and supposedly the
hardware ignores reprogramming. We also need userland buy-in to the
change in HZ, since this is visible in the wait4 resources etc. */
#ifndef __KERNEL__
#define HZ 1024
#endif
#define EXEC_PAGESIZE 8192
@ -17,5 +11,4 @@
#define MAXHOSTNAMELEN 64 /* max length of hostname */
#endif /* _UAPI_ASM_ALPHA_PARAM_H */

2
arch/alpha/include/uapi/asm/unistd.h
View File

@ -467,5 +467,7 @@
#define __NR_sendmmsg 503
#define __NR_process_vm_readv 504
#define __NR_process_vm_writev 505
#define __NR_kcmp 506
#define __NR_finit_module 507
#endif /* _UAPI_ALPHA_UNISTD_H */

399
arch/alpha/kernel/entry.S
View File

@ -12,11 +12,32 @@
.text
.set noat
.cfi_sections .debug_frame
/* Stack offsets. */
#define SP_OFF 184
#define SWITCH_STACK_SIZE 320
.macro CFI_START_OSF_FRAME func
.align 4
.globl \func
.type \func,@function
\func:
.cfi_startproc simple
.cfi_return_column 64
.cfi_def_cfa $sp, 48
.cfi_rel_offset 64, 8
.cfi_rel_offset $gp, 16
.cfi_rel_offset $16, 24
.cfi_rel_offset $17, 32
.cfi_rel_offset $18, 40
.endm
.macro CFI_END_OSF_FRAME func
.cfi_endproc
.size \func, . - \func
.endm
/*
* This defines the normal kernel pt-regs layout.
*
@ -27,100 +48,158 @@
* the palcode-provided values are available to the signal handler.
*/
#define SAVE_ALL \
subq $sp, SP_OFF, $sp; \
stq $0, 0($sp); \
stq $1, 8($sp); \
stq $2, 16($sp); \
stq $3, 24($sp); \
stq $4, 32($sp); \
stq $28, 144($sp); \
lda $2, alpha_mv; \
stq $5, 40($sp); \
stq $6, 48($sp); \
stq $7, 56($sp); \
stq $8, 64($sp); \
stq $19, 72($sp); \
stq $20, 80($sp); \
stq $21, 88($sp); \
ldq $2, HAE_CACHE($2); \
stq $22, 96($sp); \
stq $23, 104($sp); \
stq $24, 112($sp); \
stq $25, 120($sp); \
stq $26, 128($sp); \
stq $27, 136($sp); \
stq $2, 152($sp); \
stq $16, 160($sp); \
stq $17, 168($sp); \
.macro SAVE_ALL
subq $sp, SP_OFF, $sp
.cfi_adjust_cfa_offset SP_OFF
stq $0, 0($sp)
stq $1, 8($sp)
stq $2, 16($sp)
stq $3, 24($sp)
stq $4, 32($sp)
stq $28, 144($sp)
.cfi_rel_offset $0, 0
.cfi_rel_offset $1, 8
.cfi_rel_offset $2, 16
.cfi_rel_offset $3, 24
.cfi_rel_offset $4, 32
.cfi_rel_offset $28, 144
lda $2, alpha_mv
stq $5, 40($sp)
stq $6, 48($sp)
stq $7, 56($sp)
stq $8, 64($sp)
stq $19, 72($sp)
stq $20, 80($sp)
stq $21, 88($sp)
ldq $2, HAE_CACHE($2)
stq $22, 96($sp)
stq $23, 104($sp)
stq $24, 112($sp)
stq $25, 120($sp)
stq $26, 128($sp)
stq $27, 136($sp)
stq $2, 152($sp)
stq $16, 160($sp)
stq $17, 168($sp)
stq $18, 176($sp)
.cfi_rel_offset $5, 40
.cfi_rel_offset $6, 48
.cfi_rel_offset $7, 56
.cfi_rel_offset $8, 64
.cfi_rel_offset $19, 72
.cfi_rel_offset $20, 80
.cfi_rel_offset $21, 88
.cfi_rel_offset $22, 96
.cfi_rel_offset $23, 104
.cfi_rel_offset $24, 112
.cfi_rel_offset $25, 120
.cfi_rel_offset $26, 128
.cfi_rel_offset $27, 136
.endm
#define RESTORE_ALL \
lda $19, alpha_mv; \
ldq $0, 0($sp); \
ldq $1, 8($sp); \
ldq $2, 16($sp); \
ldq $3, 24($sp); \
ldq $21, 152($sp); \
ldq $20, HAE_CACHE($19); \
ldq $4, 32($sp); \
ldq $5, 40($sp); \
ldq $6, 48($sp); \
ldq $7, 56($sp); \
subq $20, $21, $20; \
ldq $8, 64($sp); \
beq $20, 99f; \
ldq $20, HAE_REG($19); \
stq $21, HAE_CACHE($19); \
stq $21, 0($20); \
99:; \
ldq $19, 72($sp); \
ldq $20, 80($sp); \
ldq $21, 88($sp); \
ldq $22, 96($sp); \
ldq $23, 104($sp); \
ldq $24, 112($sp); \
ldq $25, 120($sp); \
ldq $26, 128($sp); \
ldq $27, 136($sp); \
ldq $28, 144($sp); \
.macro RESTORE_ALL
lda $19, alpha_mv
ldq $0, 0($sp)
ldq $1, 8($sp)
ldq $2, 16($sp)
ldq $3, 24($sp)
ldq $21, 152($sp)
ldq $20, HAE_CACHE($19)
ldq $4, 32($sp)
ldq $5, 40($sp)
ldq $6, 48($sp)
ldq $7, 56($sp)
subq $20, $21, $20
ldq $8, 64($sp)
beq $20, 99f
ldq $20, HAE_REG($19)
stq $21, HAE_CACHE($19)
stq $21, 0($20)
99: ldq $19, 72($sp)
ldq $20, 80($sp)
ldq $21, 88($sp)
ldq $22, 96($sp)
ldq $23, 104($sp)
ldq $24, 112($sp)
ldq $25, 120($sp)
ldq $26, 128($sp)
ldq $27, 136($sp)
ldq $28, 144($sp)
addq $sp, SP_OFF, $sp
.cfi_restore $0
.cfi_restore $1
.cfi_restore $2
.cfi_restore $3
.cfi_restore $4
.cfi_restore $5
.cfi_restore $6
.cfi_restore $7
.cfi_restore $8
.cfi_restore $19
.cfi_restore $20
.cfi_restore $21
.cfi_restore $22
.cfi_restore $23
.cfi_restore $24
.cfi_restore $25
.cfi_restore $26
.cfi_restore $27
.cfi_restore $28
.cfi_adjust_cfa_offset -SP_OFF
.endm
.macro DO_SWITCH_STACK
bsr $1, do_switch_stack
.cfi_adjust_cfa_offset SWITCH_STACK_SIZE
.cfi_rel_offset $9, 0
.cfi_rel_offset $10, 8
.cfi_rel_offset $11, 16
.cfi_rel_offset $12, 24
.cfi_rel_offset $13, 32
.cfi_rel_offset $14, 40
.cfi_rel_offset $15, 48
/* We don't really care about the FP registers for debugging. */
.endm
.macro UNDO_SWITCH_STACK
bsr $1, undo_switch_stack
.cfi_restore $9
.cfi_restore $10
.cfi_restore $11
.cfi_restore $12
.cfi_restore $13
.cfi_restore $14
.cfi_restore $15
.cfi_adjust_cfa_offset -SWITCH_STACK_SIZE
.endm
/*
* Non-syscall kernel entry points.
*/
.align 4
.globl entInt
.ent entInt
entInt:
CFI_START_OSF_FRAME entInt
SAVE_ALL
lda $8, 0x3fff
lda $26, ret_from_sys_call
bic $sp, $8, $8
mov $sp, $19
jsr $31, do_entInt
.end entInt
CFI_END_OSF_FRAME entInt
.align 4
.globl entArith
.ent entArith
entArith:
CFI_START_OSF_FRAME entArith
SAVE_ALL
lda $8, 0x3fff
lda $26, ret_from_sys_call
bic $sp, $8, $8
mov $sp, $18
jsr $31, do_entArith
.end entArith
CFI_END_OSF_FRAME entArith
.align 4
.globl entMM
.ent entMM
entMM:
CFI_START_OSF_FRAME entMM
SAVE_ALL
/* save $9 - $15 so the inline exception code can manipulate them. */
subq $sp, 56, $sp
.cfi_adjust_cfa_offset 56
stq $9, 0($sp)
stq $10, 8($sp)
stq $11, 16($sp)
@ -128,6 +207,13 @@ entMM:
stq $13, 32($sp)
stq $14, 40($sp)
stq $15, 48($sp)
.cfi_rel_offset $9, 0
.cfi_rel_offset $10, 8
.cfi_rel_offset $11, 16
.cfi_rel_offset $12, 24
.cfi_rel_offset $13, 32
.cfi_rel_offset $14, 40
.cfi_rel_offset $15, 48
addq $sp, 56, $19
/* handle the fault */
lda $8, 0x3fff
@ -142,28 +228,33 @@ entMM:
ldq $14, 40($sp)
ldq $15, 48($sp)
addq $sp, 56, $sp
.cfi_restore $9
.cfi_restore $10
.cfi_restore $11
.cfi_restore $12
.cfi_restore $13
.cfi_restore $14
.cfi_restore $15
.cfi_adjust_cfa_offset -56
/* finish up the syscall as normal. */
br ret_from_sys_call
.end entMM
CFI_END_OSF_FRAME entMM
.align 4
.globl entIF
.ent entIF
entIF:
CFI_START_OSF_FRAME entIF
SAVE_ALL
lda $8, 0x3fff
lda $26, ret_from_sys_call
bic $sp, $8, $8
mov $sp, $17
jsr $31, do_entIF
.end entIF
CFI_END_OSF_FRAME entIF
.align 4
.globl entUna
.ent entUna
entUna:
CFI_START_OSF_FRAME entUna
lda $sp, -256($sp)
.cfi_adjust_cfa_offset 256
stq $0, 0($sp)
.cfi_rel_offset $0, 0
.cfi_remember_state
ldq $0, 256($sp) /* get PS */
stq $1, 8($sp)
stq $2, 16($sp)
@ -195,6 +286,32 @@ entUna:
stq $28, 224($sp)
mov $sp, $19
stq $gp, 232($sp)
.cfi_rel_offset $1, 1*8
.cfi_rel_offset $2, 2*8
.cfi_rel_offset $3, 3*8
.cfi_rel_offset $4, 4*8
.cfi_rel_offset $5, 5*8
.cfi_rel_offset $6, 6*8
.cfi_rel_offset $7, 7*8
.cfi_rel_offset $8, 8*8
.cfi_rel_offset $9, 9*8
.cfi_rel_offset $10, 10*8
.cfi_rel_offset $11, 11*8
.cfi_rel_offset $12, 12*8
.cfi_rel_offset $13, 13*8
.cfi_rel_offset $14, 14*8
.cfi_rel_offset $15, 15*8
.cfi_rel_offset $19, 19*8
.cfi_rel_offset $20, 20*8
.cfi_rel_offset $21, 21*8
.cfi_rel_offset $22, 22*8
.cfi_rel_offset $23, 23*8
.cfi_rel_offset $24, 24*8
.cfi_rel_offset $25, 25*8
.cfi_rel_offset $26, 26*8
.cfi_rel_offset $27, 27*8
.cfi_rel_offset $28, 28*8
.cfi_rel_offset $29, 29*8
lda $8, 0x3fff
stq $31, 248($sp)
bic $sp, $8, $8
@ -228,16 +345,45 @@ entUna:
ldq $28, 224($sp)
ldq $gp, 232($sp)
lda $sp, 256($sp)
.cfi_restore $1
.cfi_restore $2
.cfi_restore $3
.cfi_restore $4
.cfi_restore $5
.cfi_restore $6
.cfi_restore $7
.cfi_restore $8
.cfi_restore $9
.cfi_restore $10
.cfi_restore $11
.cfi_restore $12
.cfi_restore $13
.cfi_restore $14
.cfi_restore $15
.cfi_restore $19
.cfi_restore $20
.cfi_restore $21
.cfi_restore $22
.cfi_restore $23
.cfi_restore $24
.cfi_restore $25
.cfi_restore $26
.cfi_restore $27
.cfi_restore $28
.cfi_restore $29
.cfi_adjust_cfa_offset -256
call_pal PAL_rti
.end entUna
.align 4
.ent entUnaUser
entUnaUser:
.cfi_restore_state
ldq $0, 0($sp) /* restore original $0 */
lda $sp, 256($sp) /* pop entUna's stack frame */
.cfi_restore $0
.cfi_adjust_cfa_offset -256
SAVE_ALL /* setup normal kernel stack */
lda $sp, -56($sp)
.cfi_adjust_cfa_offset 56
stq $9, 0($sp)
stq $10, 8($sp)
stq $11, 16($sp)
@ -245,6 +391,13 @@ entUnaUser:
stq $13, 32($sp)
stq $14, 40($sp)
stq $15, 48($sp)
.cfi_rel_offset $9, 0
.cfi_rel_offset $10, 8
.cfi_rel_offset $11, 16
.cfi_rel_offset $12, 24
.cfi_rel_offset $13, 32
.cfi_rel_offset $14, 40
.cfi_rel_offset $15, 48
lda $8, 0x3fff
addq $sp, 56, $19
bic $sp, $8, $8
@ -257,20 +410,25 @@ entUnaUser:
ldq $14, 40($sp)
ldq $15, 48($sp)
lda $sp, 56($sp)
.cfi_restore $9
.cfi_restore $10
.cfi_restore $11
.cfi_restore $12
.cfi_restore $13
.cfi_restore $14
.cfi_restore $15
.cfi_adjust_cfa_offset -56
br ret_from_sys_call
.end entUnaUser
CFI_END_OSF_FRAME entUna
.align 4
.globl entDbg
.ent entDbg
entDbg:
CFI_START_OSF_FRAME entDbg
SAVE_ALL
lda $8, 0x3fff
lda $26, ret_from_sys_call
bic $sp, $8, $8
mov $sp, $16
jsr $31, do_entDbg
.end entDbg
CFI_END_OSF_FRAME entDbg
/*
* The system call entry point is special. Most importantly, it looks
@ -285,8 +443,12 @@ entDbg:
.align 4
.globl entSys
.globl ret_from_sys_call
.ent entSys
.type entSys, @function
.cfi_startproc simple
.cfi_return_column 64
.cfi_def_cfa $sp, 48
.cfi_rel_offset 64, 8
.cfi_rel_offset $gp, 16
entSys:
SAVE_ALL
lda $8, 0x3fff
@ -300,6 +462,9 @@ entSys:
stq $17, SP_OFF+32($sp)
s8addq $0, $5, $5
stq $18, SP_OFF+40($sp)
.cfi_rel_offset $16, SP_OFF+24
.cfi_rel_offset $17, SP_OFF+32
.cfi_rel_offset $18, SP_OFF+40
blbs $3, strace
beq $4, 1f
ldq $27, 0($5)
@ -310,6 +475,7 @@ entSys:
stq $31, 72($sp) /* a3=0 => no error */
.align 4
.globl ret_from_sys_call
ret_from_sys_call:
cmovne $26, 0, $18 /* $18 = 0 => non-restartable */
ldq $0, SP_OFF($sp)
@ -324,10 +490,12 @@ ret_to_user:
and $17, _TIF_WORK_MASK, $2
bne $2, work_pending
restore_all:
.cfi_remember_state
RESTORE_ALL
call_pal PAL_rti
ret_to_kernel:
.cfi_restore_state
lda $16, 7
call_pal PAL_swpipl
br restore_all
@ -356,7 +524,6 @@ $ret_success:
stq $0, 0($sp)
stq $31, 72($sp) /* a3=0 => no error */
br ret_from_sys_call
.end entSys
/*
* Do all cleanup when returning from all interrupts and system calls.
@ -370,7 +537,7 @@ $ret_success:
*/
.align 4
.ent work_pending
.type work_pending, @function
work_pending:
and $17, _TIF_NOTIFY_RESUME | _TIF_SIGPENDING, $2
bne $2, $work_notifysig
@ -387,23 +554,22 @@ $work_resched:
$work_notifysig:
mov $sp, $16
bsr $1, do_switch_stack
DO_SWITCH_STACK
jsr $26, do_work_pending
bsr $1, undo_switch_stack
UNDO_SWITCH_STACK
br restore_all
.end work_pending
/*
* PTRACE syscall handler
*/
.align 4
.ent strace
.type strace, @function
strace:
/* set up signal stack, call syscall_trace */
bsr $1, do_switch_stack
DO_SWITCH_STACK
jsr $26, syscall_trace_enter /* returns the syscall number */
bsr $1, undo_switch_stack
UNDO_SWITCH_STACK
/* get the arguments back.. */
ldq $16, SP_OFF+24($sp)
@ -431,9 +597,9 @@ ret_from_straced:
$strace_success:
stq $0, 0($sp) /* save return value */
bsr $1, do_switch_stack
DO_SWITCH_STACK
jsr $26, syscall_trace_leave
bsr $1, undo_switch_stack
UNDO_SWITCH_STACK
br $31, ret_from_sys_call
.align 3
@ -447,26 +613,31 @@ $strace_error:
stq $0, 0($sp)
stq $1, 72($sp) /* a3 for return */
bsr $1, do_switch_stack
DO_SWITCH_STACK
mov $18, $9 /* save old syscall number */
mov $19, $10 /* save old a3 */
jsr $26, syscall_trace_leave
mov $9, $18
mov $10, $19
bsr $1, undo_switch_stack
UNDO_SWITCH_STACK
mov $31, $26 /* tell "ret_from_sys_call" we can restart */
br ret_from_sys_call
.end strace
CFI_END_OSF_FRAME entSys
/*
* Save and restore the switch stack -- aka the balance of the user context.
*/
.align 4
.ent do_switch_stack
.type do_switch_stack, @function
.cfi_startproc simple
.cfi_return_column 64
.cfi_def_cfa $sp, 0
.cfi_register 64, $1
do_switch_stack:
lda $sp, -SWITCH_STACK_SIZE($sp)
.cfi_adjust_cfa_offset SWITCH_STACK_SIZE
stq $9, 0($sp)
stq $10, 8($sp)
stq $11, 16($sp)
@ -510,10 +681,14 @@ do_switch_stack:
stt $f0, 312($sp) # save fpcr in slot of $f31
ldt $f0, 64($sp) # dont let "do_switch_stack" change fp state.
ret $31, ($1), 1
.end do_switch_stack
.cfi_endproc
.size do_switch_stack, .-do_switch_stack
.align 4
.ent undo_switch_stack
.type undo_switch_stack, @function
.cfi_startproc simple
.cfi_def_cfa $sp, 0
.cfi_register 64, $1
undo_switch_stack:
ldq $9, 0($sp)
ldq $10, 8($sp)
@ -558,7 +733,8 @@ undo_switch_stack:
ldt $f30, 304($sp)
lda $sp, SWITCH_STACK_SIZE($sp)
ret $31, ($1), 1
.end undo_switch_stack
.cfi_endproc
.size undo_switch_stack, .-undo_switch_stack
/*
* The meat of the context switch code.
@ -566,17 +742,18 @@ undo_switch_stack:
.align 4
.globl alpha_switch_to
.ent alpha_switch_to
.type alpha_switch_to, @function
.cfi_startproc
alpha_switch_to:
.prologue 0
bsr $1, do_switch_stack
DO_SWITCH_STACK
call_pal PAL_swpctx
lda $8, 0x3fff
bsr $1, undo_switch_stack
UNDO_SWITCH_STACK
bic $sp, $8, $8
mov $17, $0
ret
.end alpha_switch_to
.cfi_endproc
.size alpha_switch_to, .-alpha_switch_to
/*
* New processes begin life here.

2
arch/alpha/kernel/irq_alpha.c
View File

@ -236,7 +236,7 @@ void __init
init_rtc_irq(void)
{
irq_set_chip_and_handler_name(RTC_IRQ, &dummy_irq_chip,
handle_simple_irq, "RTC");
handle_percpu_irq, "RTC");
setup_irq(RTC_IRQ, &timer_irqaction);
}

15
arch/alpha/kernel/smp.c
View File

@ -116,7 +116,7 @@ wait_boot_cpu_to_stop(int cpuid)
/*
* Where secondaries begin a life of C.
*/
void __cpuinit
void
smp_callin(void)
{
int cpuid = hard_smp_processor_id();
@ -194,7 +194,7 @@ wait_for_txrdy (unsigned long cpumask)
* Send a message to a secondary's console. "START" is one such
* interesting message. ;-)
*/
static void __cpuinit
static void
send_secondary_console_msg(char *str, int cpuid)
{
struct percpu_struct *cpu;
@ -264,9 +264,10 @@ recv_secondary_console_msg(void)
if (cnt <= 0 || cnt >= 80)
strcpy(buf, "<<< BOGUS MSG >>>");
else {
cp1 = (char *) &cpu->ipc_buffer[11];
cp1 = (char *) &cpu->ipc_buffer[1];
cp2 = buf;
strcpy(cp2, cp1);
memcpy(cp2, cp1, cnt);
cp2[cnt] = '\0';
while ((cp2 = strchr(cp2, '\r')) != 0) {
*cp2 = ' ';
@ -285,7 +286,7 @@ recv_secondary_console_msg(void)
/*
* Convince the console to have a secondary cpu begin execution.
*/
static int __cpuinit
static int
secondary_cpu_start(int cpuid, struct task_struct *idle)
{
struct percpu_struct *cpu;
@ -356,7 +357,7 @@ secondary_cpu_start(int cpuid, struct task_struct *idle)
/*
* Bring one cpu online.
*/
static int __cpuinit
static int
smp_boot_one_cpu(int cpuid, struct task_struct *idle)
{
unsigned long timeout;
@ -472,7 +473,7 @@ smp_prepare_boot_cpu(void)
{
}
int __cpuinit
int
__cpu_up(unsigned int cpu, struct task_struct *tidle)
{
smp_boot_one_cpu(cpu, tidle);

8
arch/alpha/kernel/sys_dp264.c
View File

@ -190,9 +190,6 @@ static struct irq_chip clipper_irq_type = {
static void
dp264_device_interrupt(unsigned long vector)
{
#if 1
printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
#else
unsigned long pld;
unsigned int i;
@ -210,12 +207,7 @@ dp264_device_interrupt(unsigned long vector)
isa_device_interrupt(vector);
else
handle_irq(16 + i);
#if 0
TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
tmp = TSUNAMI_cchip->dir0.csr;
#endif
}
#endif
}
static void

3
arch/alpha/kernel/sys_marvel.c
View File

@ -317,8 +317,9 @@ marvel_init_irq(void)
}
static int
marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin)
{
struct pci_dev *dev = (struct pci_dev *)cdev;
struct pci_controller *hose = dev->sysdata;
struct io7_port *io7_port = hose->sysdata;
struct io7 *io7 = io7_port->io7;

2
arch/alpha/kernel/systbls.S
View File

@ -524,6 +524,8 @@ sys_call_table:
.quad sys_sendmmsg
.quad sys_process_vm_readv
.quad sys_process_vm_writev /* 505 */
.quad sys_kcmp
.quad sys_finit_module
.size sys_call_table, . - sys_call_table
.type sys_call_table, @object

4
arch/alpha/kernel/time.c
View File

@ -105,9 +105,7 @@ void arch_irq_work_raise(void)
static inline __u32 rpcc(void)
{
__u32 result;
asm volatile ("rpcc %0" : "=r"(result));
return result;
return __builtin_alpha_rpcc();
}
int update_persistent_clock(struct timespec now)

12
arch/alpha/kernel/traps.c
View File

@ -32,7 +32,7 @@
static int opDEC_fix;
static void __cpuinit
static void
opDEC_check(void)
{
__asm__ __volatile__ (
@ -66,8 +66,8 @@ dik_show_regs(struct pt_regs *regs, unsigned long *r9_15)
{
printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n",
regs->pc, regs->r26, regs->ps, print_tainted());
print_symbol("pc is at %s\n", regs->pc);
print_symbol("ra is at %s\n", regs->r26 );
printk("pc is at %pSR\n", (void *)regs->pc);
printk("ra is at %pSR\n", (void *)regs->r26);
printk("v0 = %016lx t0 = %016lx t1 = %016lx\n",
regs->r0, regs->r1, regs->r2);
printk("t2 = %016lx t3 = %016lx t4 = %016lx\n",
@ -132,9 +132,7 @@ dik_show_trace(unsigned long *sp)
continue;
if (tmp >= (unsigned long) &_etext)
continue;
printk("[<%lx>]", tmp);
print_symbol(" %s", tmp);
printk("\n");
printk("[<%lx>] %pSR\n", tmp, (void *)tmp);
if (i > 40) {
printk(" ...");
break;
@ -1059,7 +1057,7 @@ give_sigbus:
return;
}
void __cpuinit
void
trap_init(void)
{
/* Tell PAL-code what global pointer we want in the kernel. */

3
arch/arm/Kconfig
View File

@ -1600,8 +1600,7 @@ config LOCAL_TIMERS
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if SOC_OMAP5
default 512 if ARCH_KEYSTONE
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
default 288 if ARCH_SUNXI

22
arch/arm/boot/dts/atlas6.dtsi
View File

@ -485,6 +485,12 @@
sirf,function = "usp0";
};
};
usp0_uart_nostreamctrl_pins_a: usp0@1 {
usp0 {
sirf,pins = "usp0_uart_nostreamctrl_grp";
sirf,function = "usp0_uart_nostreamctrl";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
@ -515,16 +521,16 @@
sirf,function = "pulse_count";
};
};
cko0_rst_pins_a: cko0_rst@0 {
cko0_rst {
sirf,pins = "cko0_rstgrp";
sirf,function = "cko0_rst";
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_rst_pins_a: cko1_rst@0 {
cko1_rst {
sirf,pins = "cko1_rstgrp";
sirf,function = "cko1_rst";
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};

2
arch/arm/boot/dts/imx28-apx4devkit.dts
View File

@ -147,7 +147,7 @@
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
};
pcf8563: rtc@51 {

2
arch/arm/boot/dts/imx28-evk.dts
View File

@ -195,7 +195,7 @@
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
};
at24@51 {

2
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -184,7 +184,7 @@
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&saif0>;
};
eeprom: eeprom@51 {

1
arch/arm/boot/dts/imx28.dtsi
View File

@ -837,6 +837,7 @@
compatible = "fsl,imx28-saif";
reg = <0x80042000 0x2000>;
interrupts = <59 80>;
#clock-cells = <0>;
clocks = <&clks 53>;
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";

13
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -61,6 +61,16 @@
mux-int-port = <2>;
mux-ext-port = <3>;
};
clocks {
clk_26M: codec_clock {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <26000000>;
gpios = <&gpio4 26 1>;
};
};
};
&esdhc1 {
@ -229,6 +239,7 @@
MX51_PAD_EIM_A27__GPIO2_21 0x5
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
>;
};
};
@ -255,7 +266,7 @@
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <26000000>;
clocks = <&clk_26M>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};

2
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -27,7 +27,7 @@
backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000 0 0>;
pwms = <&pwm2 0 50000>;
brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
default-brightness-level = <10>;
enable-gpios = <&gpio7 7 0>;

32
arch/arm/boot/dts/imx53.dtsi
View File

@ -725,15 +725,15 @@
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
@ -748,8 +748,8 @@
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
@ -766,17 +766,17 @@
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
>;
};
@ -785,8 +785,8 @@
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
>;
};
};
@ -794,8 +794,8 @@
uart5 {
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
>;
};
};

16
arch/arm/boot/dts/prima2.dtsi
View File

@ -515,16 +515,16 @@
sirf,function = "pulse_count";
};
};
cko0_rst_pins_a: cko0_rst@0 {
cko0_rst {
sirf,pins = "cko0_rstgrp";
sirf,function = "cko0_rst";
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_rst_pins_a: cko1_rst@0 {
cko1_rst {
sirf,pins = "cko1_rstgrp";
sirf,function = "cko1_rst";
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};

10
arch/arm/boot/dts/stih416-pinctrl.dtsi
View File

@ -166,6 +166,15 @@
reg = <0x9000 0x100>;
st,bank-name = "PIO31";
};
serial2-oe {
pinctrl_serial2_oe: serial2-1 {
st,pins {
output-enable = <&PIO11 3 ALT2 OUT>;
};
};
};
};
pin-controller-rear {
@ -218,7 +227,6 @@
st,pins {
tx = <&PIO17 4 ALT2 OUT>;
rx = <&PIO17 5 ALT2 IN>;
output-enable = <&PIO11 3 ALT2 OUT>;
};
};
};

2
arch/arm/boot/dts/stih416.dtsi
View File

@ -79,7 +79,7 @@
interrupts = <0 197 0>;
clocks = <&CLK_S_ICN_REG_0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
};
/* SBC_UART1 */

6
arch/arm/boot/dts/twl4030.dtsi
View File

@ -47,6 +47,12 @@
regulator-max-microvolt = <3150000>;
};
vmmc2: regulator-vmmc2 {
compatible = "ti,twl4030-vmmc2";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
};
vusb1v5: regulator-vusb1v5 {
compatible = "ti,twl4030-vusb1v5";
};

8
arch/arm/boot/dts/vf610.dtsi
View File

@ -442,8 +442,8 @@
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <0 78 0x04>;
clocks = <&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>,
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
@ -453,8 +453,8 @@
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <0 79 0x04>;
clocks = <&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>,
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";

1
arch/arm/common/edma.c
View File

@ -26,7 +26,6 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/edma.h>
#include <linux/err.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_dma.h>

4
arch/arm/common/mcpm_platsmp.c
View File

@ -19,7 +19,7 @@
#include <asm/smp.h>
#include <asm/smp_plat.h>
static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned int mpidr, pcpu, pcluster, ret;
extern void secondary_startup(void);
@ -40,7 +40,7 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i
return 0;
}
static void __cpuinit mcpm_secondary_init(unsigned int cpu)
static void mcpm_secondary_init(unsigned int cpu)
{
mcpm_cpu_powered_up();
}

2
arch/arm/configs/da8xx_omapl_defconfig
View File

@ -102,6 +102,8 @@ CONFIG_SND_SOC=m
CONFIG_SND_DAVINCI_SOC=m
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_XFS_FS=m

2
arch/arm/configs/davinci_all_defconfig
View File

@ -162,6 +162,8 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=m
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_XFS_FS=m

6
arch/arm/configs/multi_v7_defconfig
View File

@ -53,6 +53,7 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_OMAP_OCP2SCP=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
@ -61,6 +62,7 @@ CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
CONFIG_SUN4I_EMAC=y
CONFIG_NET_CALXEDA_XGMAC=y
CONFIG_KS8851=y
CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y
CONFIG_MDIO_SUN4I=y
@ -89,6 +91,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_SIRF=y
CONFIG_I2C_TEGRA=y
CONFIG_SPI=y
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_PL022=y
CONFIG_SPI_SIRF=y
CONFIG_SPI_TEGRA114=y
@ -111,11 +114,12 @@ CONFIG_FB_SIMPLE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_AB8500_USB=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_OMAP_USB2=y

7
arch/arm/configs/nhk8815_defconfig
View File

@ -1,6 +1,8 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@ -48,7 +50,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND=y
@ -94,8 +95,10 @@ CONFIG_I2C_GPIO=y
CONFIG_I2C_NOMADIK=y
CONFIG_DEBUG_GPIO=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_MMC=y
CONFIG_MMC_CLKGATE=y
CONFIG_MMC_UNSAFE_RESUME=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y

2
arch/arm/include/asm/arch_timer.h
View File

@ -89,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void)
return cval;
}
static inline void __cpuinit arch_counter_set_user_access(void)
static inline void arch_counter_set_user_access(void)
{
u32 cntkctl;

1
arch/arm/kernel/head-common.S
View File

@ -149,7 +149,6 @@ ENDPROC(lookup_processor_type)
* r5 = proc_info pointer in physical address space
* r9 = cpuid (preserved)
*/
__CPUINIT
__lookup_processor_type:
adr r3, __lookup_processor_type_data
ldmia r3, {r4 - r6}

1
arch/arm/kernel/head-nommu.S
View File

@ -87,7 +87,6 @@ ENTRY(stext)
ENDPROC(stext)
#ifdef CONFIG_SMP
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.

1
arch/arm/kernel/head.S
View File

@ -343,7 +343,6 @@ __turn_mmu_on_loc:
.long __turn_mmu_on_end
#if defined(CONFIG_SMP)
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.

4
arch/arm/kernel/hw_breakpoint.c
View File

@ -1020,7 +1020,7 @@ out_mdbgen:
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
}
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
static int dbg_reset_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata dbg_reset_nb = {
static struct notifier_block dbg_reset_nb = {
.notifier_call = dbg_reset_notify,
};

6
arch/arm/kernel/perf_event_cpu.c
View File

@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
* junk values out of them.
*/
static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
void *hcpu)
{
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;
@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
static struct notifier_block cpu_pmu_hotplug_notifier = {
.notifier_call = cpu_pmu_notify,
};

3
arch/arm/kernel/psci_smp.c
View File

@ -46,8 +46,7 @@
extern void secondary_startup(void);
static int __cpuinit psci_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (psci_ops.cpu_on)
return psci_ops.cpu_on(cpu_logical_map(cpu),

18
arch/arm/kernel/smp.c
View File

@ -58,7 +58,7 @@ struct secondary_data secondary_data;
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
volatile int pen_release = -1;
enum ipi_msg_type {
IPI_WAKEUP,
@ -86,7 +86,7 @@ static unsigned long get_arch_pgd(pgd_t *pgd)
return pgdir >> ARCH_PGD_SHIFT;
}
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
int ret;
@ -138,7 +138,7 @@ void __init smp_init_cpus(void)
smp_ops.smp_init_cpus();
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
int boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (smp_ops.smp_boot_secondary)
return smp_ops.smp_boot_secondary(cpu, idle);
@ -170,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu)
/*
* __cpu_disable runs on the processor to be shutdown.
*/
int __cpuinit __cpu_disable(void)
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
int ret;
@ -216,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died);
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed, or it is timed out.
*/
void __cpuinit __cpu_die(unsigned int cpu)
void __cpu_die(unsigned int cpu)
{
if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
pr_err("CPU%u: cpu didn't die\n", cpu);
@ -306,7 +306,7 @@ void __ref cpu_die(void)
* Called by both boot and secondaries to move global data into
* per-processor storage.
*/
static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
static void smp_store_cpu_info(unsigned int cpuid)
{
struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
@ -322,7 +322,7 @@ static void percpu_timer_setup(void);
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
*/
asmlinkage void __cpuinit secondary_start_kernel(void)
asmlinkage void secondary_start_kernel(void)
{
struct mm_struct *mm = &init_mm;
unsigned int cpu;
@ -521,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
{
}
static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
static void broadcast_timer_setup(struct clock_event_device *evt)
{
evt->name = "dummy_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT |
@ -550,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops)
}
#endif
static void __cpuinit percpu_timer_setup(void)
static void percpu_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);

6
arch/arm/kernel/smp_twd.c
View File

@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init);
#endif
static void __cpuinit twd_calibrate_rate(void)
static void twd_calibrate_rate(void)
{
unsigned long count;
u64 waitjiffies;
@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np)
/*
* Setup the local clock events for a CPU.
*/
static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
static int twd_timer_setup(struct clock_event_device *clk)
{
struct clock_event_device **this_cpu_clk;
int cpu = smp_processor_id();
@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
return 0;
}
static struct local_timer_ops twd_lt_ops __cpuinitdata = {
static struct local_timer_ops twd_lt_ops = {
.setup = twd_timer_setup,
.stop = twd_timer_stop,
};

2
arch/arm/lib/delay.c
View File

@ -86,7 +86,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
}
}
unsigned long __cpuinit calibrate_delay_is_known(void)
unsigned long calibrate_delay_is_known(void)
{
delay_calibrated = true;
return lpj_fine;

2
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -505,7 +505,7 @@ static struct vpbe_output dm365evm_vpbe_outputs[] = {
/*
* Amplifiers on the board
*/
struct ths7303_platform_data ths7303_pdata = {
static struct ths7303_platform_data ths7303_pdata = {
.ch_1 = 3,
.ch_2 = 3,
.ch_3 = 3,

2
arch/arm/mach-davinci/dm355.c
View File

@ -860,7 +860,7 @@ static struct platform_device dm355_vpbe_display = {
},
};
struct venc_platform_data dm355_venc_pdata = {
static struct venc_platform_data dm355_venc_pdata = {
.setup_pinmux = dm355_vpbe_setup_pinmux,
.setup_clock = dm355_venc_setup_clock,
};

2
arch/arm/mach-davinci/dm365.c
View File

@ -1349,7 +1349,7 @@ static struct platform_device dm365_vpbe_display = {
},
};
struct venc_platform_data dm365_venc_pdata = {
static struct venc_platform_data dm365_venc_pdata = {
.setup_pinmux = dm365_vpbe_setup_pinmux,
.setup_clock = dm365_venc_setup_clock,
};

1
arch/arm/mach-exynos/Kconfig
View File

@ -92,6 +92,7 @@ config SOC_EXYNOS5440
bool "SAMSUNG EXYNOS5440"
default y
depends on ARCH_EXYNOS5
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_HAS_OPP
select HAVE_ARM_ARCH_TIMER
select AUTO_ZRELADDR

2
arch/arm/mach-exynos/Makefile
View File

@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_S5P_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o

26
arch/arm/mach-exynos/common.c
View File

@ -58,7 +58,6 @@ static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
static void exynos5_map_io(void);
static void exynos5440_map_io(void);
static int exynos_init(void);
static struct cpu_table cpu_ids[] __initdata = {
@ -95,7 +94,6 @@ static struct cpu_table cpu_ids[] __initdata = {
}, {
.idcode = EXYNOS5440_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5440_map_io,
.init = exynos_init,
.name = name_exynos5440,
},
@ -149,11 +147,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
@ -268,20 +261,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
},
};
static struct map_desc exynos5440_iodesc0[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
.length = SZ_512K,
.type = MT_DEVICE,
},
};
@ -388,11 +367,6 @@ static void __init exynos5_map_io(void)
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}
static void __init exynos5440_map_io(void)
{
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}
void __init exynos_init_time(void)
{
of_clk_init(NULL);

1
arch/arm/mach-exynos/common.h
View File

@ -97,6 +97,5 @@ struct exynos_pmu_conf {
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void s3c_cpu_resume(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

1
arch/arm/mach-exynos/cpuidle.c
View File

@ -25,6 +25,7 @@
#include <mach/regs-pmu.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include "common.h"

2
arch/arm/mach-exynos/headsmp.S
View File

@ -13,8 +13,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

5
arch/arm/mach-exynos/include/mach/memory.h
View File

@ -15,8 +15,13 @@
#define PLAT_PHYS_OFFSET UL(0x40000000)
#ifndef CONFIG_ARM_LPAE
/* Maximum of 256MiB in one bank */
#define MAX_PHYSMEM_BITS 32
#define SECTION_SIZE_BITS 28
#else
#define MAX_PHYSMEM_BITS 36
#define SECTION_SIZE_BITS 31
#endif
#endif /* __ASM_ARCH_MEMORY_H */

4
arch/arm/mach-exynos/platsmp.c
View File

@ -75,7 +75,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
static void exynos_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -90,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);

6
arch/arm/mach-exynos/pm.c
View File

@ -217,6 +217,9 @@ static __init int exynos_pm_drvinit(void)
struct clk *pll_base;
unsigned int tmp;
if (soc_is_exynos5440())
return 0;
s3c_pm_init();
/* All wakeup disable */
@ -340,6 +343,9 @@ static struct syscore_ops exynos_pm_syscore_ops = {
static __init int exynos_pm_syscore_init(void)
{
if (soc_is_exynos5440())
return 0;
register_syscore_ops(&exynos_pm_syscore_ops);
return 0;
}

2
arch/arm/mach-footbridge/dc21285.c
View File

@ -276,8 +276,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
sys->mem_offset = DC21285_PCI_MEM;
pci_ioremap_io(0, DC21285_PCI_IO);
pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);

7
arch/arm/mach-highbank/highbank.c
View File

@ -115,6 +115,7 @@ static int highbank_platform_notifier(struct notifier_block *nb,
{
struct resource *res;
int reg = -1;
u32 val;
struct device *dev = __dev;
if (event != BUS_NOTIFY_ADD_DEVICE)
@ -141,10 +142,10 @@ static int highbank_platform_notifier(struct notifier_block *nb,
return NOTIFY_DONE;
if (of_property_read_bool(dev->of_node, "dma-coherent")) {
writel(0xff31, sregs_base + reg);
val = readl(sregs_base + reg);
writel(val | 0xff01, sregs_base + reg);
set_dma_ops(dev, &arm_coherent_dma_ops);
} else
writel(0, sregs_base + reg);
}
return NOTIFY_OK;
}

2
arch/arm/mach-highbank/platsmp.c
View File

@ -24,7 +24,7 @@
extern void secondary_startup(void);
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));

5
arch/arm/mach-imx/clk-imx6q.c
View File

@ -199,7 +199,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *vdo_axi_sels[] = { "axi", "ahb", };
static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@ -392,7 +393,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels));
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));

2
arch/arm/mach-imx/clk-vf610.c
View File

@ -183,6 +183,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));

2
arch/arm/mach-imx/mx27.h
View File

@ -135,7 +135,7 @@
#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)

2
arch/arm/mach-imx/platsmp.c
View File

@ -53,7 +53,7 @@ void imx_scu_standby_enable(void)
writel_relaxed(val, scu_base);
}
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
imx_enable_cpu(cpu, true);

2
arch/arm/mach-keystone/keystone.c
View File

@ -49,7 +49,7 @@ static const char *keystone_match[] __initconst = {
NULL,
};
void keystone_restart(char mode, const char *cmd)
void keystone_restart(enum reboot_mode mode, const char *cmd)
{
u32 val;

2
arch/arm/mach-keystone/platsmp.c
View File

@ -21,7 +21,7 @@
#include "keystone.h"
static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu,
static int keystone_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
unsigned long start = virt_to_phys(&secondary_startup);

2
arch/arm/mach-msm/headsmp.S
View File

@ -11,8 +11,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* MSM specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

6
arch/arm/mach-msm/platsmp.c
View File

@ -38,7 +38,7 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
static void __cpuinit msm_secondary_init(unsigned int cpu)
static void msm_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -54,7 +54,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static __cpuinit void prepare_cold_cpu(unsigned int cpu)
static void prepare_cold_cpu(unsigned int cpu)
{
int ret;
ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
@ -73,7 +73,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
"address\n");
}
static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
static int cold_boot_done;

4
arch/arm/mach-msm/timer.c
View File

@ -139,7 +139,7 @@ static struct clocksource msm_clocksource = {
};
#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
static int msm_local_timer_setup(struct clock_event_device *evt)
{
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
@ -164,7 +164,7 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
disable_percpu_irq(evt->irq);
}
static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
static struct local_timer_ops msm_local_timer_ops = {
.setup = msm_local_timer_setup,
.stop = msm_local_timer_stop,
};

2
arch/arm/mach-mvebu/coherency.c
View File

@ -28,7 +28,7 @@
#include <asm/cacheflush.h>
#include "armada-370-xp.h"
unsigned long __cpuinitdata coherency_phys_base;
unsigned long coherency_phys_base;
static void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

2
arch/arm/mach-mvebu/headsmp.S
View File

@ -21,8 +21,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* Armada XP specific entry point for secondary CPUs.
* We add the CPU to the coherency fabric and then jump to secondary

5
arch/arm/mach-mvebu/platsmp.c
View File

@ -71,13 +71,12 @@ void __init set_secondary_cpus_clock(void)
}
}
static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
static void armada_xp_secondary_init(unsigned int cpu)
{
armada_xp_mpic_smp_cpu_init();
}
static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
pr_info("Booting CPU %d\n", cpu);

2
arch/arm/mach-omap2/Kconfig
View File

@ -62,7 +62,7 @@ config SOC_OMAP5
select HAVE_SMP
select COMMON_CLK
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181
select ARM_ERRATA_798181 if SMP
config SOC_AM33XX
bool "AM33XX support"

23
arch/arm/mach-omap2/board-generic.c
View File

@ -15,6 +15,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
#include <linux/clk.h>
#include <asm/mach/arch.h>
@ -35,6 +36,21 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
{ }
};
/*
* Create alias for USB host PHY clock.
* Remove this when clock phandle can be provided via DT
*/
static void __init legacy_init_ehci_clk(char *clkname)
{
int ret;
ret = clk_add_alias("main_clk", NULL, clkname, NULL);
if (ret) {
pr_err("%s:Failed to add main_clk alias to %s :%d\n",
__func__, clkname, ret);
}
}
static void __init omap_generic_init(void)
{
omap_sdrc_init(NULL, NULL);
@ -45,10 +61,15 @@ static void __init omap_generic_init(void)
* HACK: call display setup code for selected boards to enable omapdss.
* This will be removed when omapdss supports DT.
*/
if (of_machine_is_compatible("ti,omap4-panda"))
if (of_machine_is_compatible("ti,omap4-panda")) {
omap4_panda_display_init_of();
legacy_init_ehci_clk("auxclk3_ck");
}
else if (of_machine_is_compatible("ti,omap4-sdp"))
omap_4430sdp_display_init_of();
else if (of_machine_is_compatible("ti,omap5-uevm"))
legacy_init_ehci_clk("auxclk1_ck");
}
#ifdef CONFIG_SOC_OMAP2420

2
arch/arm/mach-omap2/omap-headsmp.S
View File

@ -20,8 +20,6 @@
#include "omap44xx.h"
__CPUINIT
/* Physical address needed since MMU not enabled yet on secondary core */
#define AUX_CORE_BOOT0_PA 0x48281800

2
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -291,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* @cpu : CPU ID
* @power_state: CPU low power state.
*/
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int cpu_state = 0;

4
arch/arm/mach-omap2/omap-smp.c
View File

@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void)
return scu_base;
}
static void __cpuinit omap4_secondary_init(unsigned int cpu)
static void omap4_secondary_init(unsigned int cpu)
{
/*
* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;

2
arch/arm/mach-omap2/omap-wakeupgen.c
View File

@ -323,7 +323,7 @@ static void irq_save_secure_context(void)
#endif
#ifdef CONFIG_HOTPLUG_CPU
static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
static int irq_cpu_hotplug_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;

2
arch/arm/mach-prima2/headsmp.S
View File

@ -9,8 +9,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're

4
arch/arm/mach-prima2/platsmp.c
View File

@ -44,7 +44,7 @@ void __init sirfsoc_map_scu(void)
scu_base = (void __iomem *)SIRFSOC_VA(base);
}
static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
@ -65,7 +65,7 @@ static struct of_device_id rsc_ids[] = {
{},
};
static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
struct device_node *np;

17
arch/arm/mach-pxa/em-x270.c
View File

@ -477,16 +477,24 @@ static int em_x270_usb_hub_init(void)
/* USB Hub power-on and reset */
gpio_direction_output(usb_hub_reset, 1);
gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
regulator_enable(em_x270_usb_ldo);
err = regulator_enable(em_x270_usb_ldo);
if (err)
goto err_free_rst_gpio;
gpio_set_value(usb_hub_reset, 0);
gpio_set_value(usb_hub_reset, 1);
regulator_disable(em_x270_usb_ldo);
regulator_enable(em_x270_usb_ldo);
err = regulator_enable(em_x270_usb_ldo);
if (err)
goto err_free_rst_gpio;
gpio_set_value(usb_hub_reset, 0);
gpio_set_value(GPIO9_USB_VBUS_EN, 1);
return 0;
err_free_rst_gpio:
gpio_free(usb_hub_reset);
err_free_vbus_gpio:
gpio_free(GPIO9_USB_VBUS_EN);
err_free_usb_ldo:
@ -592,7 +600,7 @@ err_irq:
return err;
}
static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
@ -600,10 +608,11 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)
int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
regulator_enable(em_x270_sdio_ldo);
return regulator_enable(em_x270_sdio_ldo);
} else {
regulator_disable(em_x270_sdio_ldo);
}
return 0;
}
static void em_x270_mci_exit(struct device *dev, void *data)

3
arch/arm/mach-pxa/mainstone.c
View File

@ -408,7 +408,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
return err;
}
static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
@ -420,6 +420,7 @@ static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
printk(KERN_DEBUG "%s: off\n", __func__);
MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
}
return 0;
}
static void mainstone_mci_exit(struct device *dev, void *data)

3
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -335,7 +335,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
return err;
}
static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data *p_d = dev->platform_data;
u8 val;
@ -348,6 +348,7 @@ static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
val &= ~PCM990_CTRL_MMC2PWR;
pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
return 0;
}
static void pcm990_mci_exit(struct device *dev, void *data)

4
arch/arm/mach-pxa/poodle.c
View File

@ -258,7 +258,7 @@ err_free_2:
return err;
}
static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
static int poodle_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
@ -270,6 +270,8 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
gpio_set_value(POODLE_GPIO_SD_PWR, 0);
}
return 0;
}
static void poodle_mci_exit(struct device *dev, void *data)

4
arch/arm/mach-pxa/spitz.c
View File

@ -598,7 +598,7 @@ static inline void spitz_spi_init(void) {}
* NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
* give the card a chance to fully insert/eject.
*/
static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
static int spitz_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
@ -606,6 +606,8 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
else
spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
return 0;
}
static struct pxamci_platform_data spitz_mci_platform_data = {

3
arch/arm/mach-pxa/stargate2.c
View File

@ -734,9 +734,10 @@ static int stargate2_mci_init(struct device *dev,
*
* Very simple control. Either it is on or off and is controlled by
* a gpio pin */
static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
static int stargate2_mci_setpower(struct device *dev, unsigned int vdd)
{
gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
return 0;
}
static void stargate2_mci_exit(struct device *dev, void *data)

2
arch/arm/mach-s3c24xx/Kconfig
View File

@ -208,7 +208,7 @@ config S3C24XX_GPIO_EXTRA128
config S3C24XX_PLL
bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
depends on ARM_S3C24XX
depends on ARM_S3C24XX_CPUFREQ
help
Compile in support for changing the PLL frequency from the
S3C24XX series CPUfreq driver. The PLL takes time to settle

69
arch/arm/mach-s3c24xx/clock-s3c2410.c
View File

@ -119,66 +119,101 @@ static struct clk init_clocks_off[] = {
}
};
static struct clk init_clocks[] = {
{
static struct clk clk_lcd = {
.name = "lcd",
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC,
}, {
};
static struct clk clk_gpio = {
.name = "gpio",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO,
}, {
};
static struct clk clk_usb_host = {
.name = "usb-host",
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH,
}, {
};
static struct clk clk_usb_device = {
.name = "usb-device",
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD,
}, {
};
static struct clk clk_timers = {
.name = "timers",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT,
}, {
};
struct clk s3c24xx_clk_uart0 = {
.name = "uart",
.devname = "s3c2410-uart.0",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0,
}, {
};
struct clk s3c24xx_clk_uart1 = {
.name = "uart",
.devname = "s3c2410-uart.1",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1,
}, {
};
struct clk s3c24xx_clk_uart2 = {
.name = "uart",
.devname = "s3c2410-uart.2",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2,
}, {
};
static struct clk clk_rtc = {
.name = "rtc",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC,
}, {
};
static struct clk clk_watchdog = {
.name = "watchdog",
.parent = &clk_p,
.ctrlbit = 0,
}, {
};
static struct clk clk_usb_bus_host = {
.name = "usb-bus-host",
.parent = &clk_usb_bus,
}, {
};
static struct clk clk_usb_bus_gadget = {
.name = "usb-bus-gadget",
.parent = &clk_usb_bus,
},
};
static struct clk *init_clocks[] = {
&clk_lcd,
&clk_gpio,
&clk_usb_host,
&clk_usb_device,
&clk_timers,
&s3c24xx_clk_uart0,
&s3c24xx_clk_uart1,
&s3c24xx_clk_uart2,
&clk_rtc,
&clk_watchdog,
&clk_usb_bus_host,
&clk_usb_bus_gadget,
};
/* s3c2410_baseclk_add()
@ -195,7 +230,6 @@ int __init s3c2410_baseclk_add(void)
{
unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
struct clk *clkp;
struct clk *xtal;
int ret;
int ptr;
@ -207,8 +241,9 @@ int __init s3c2410_baseclk_add(void)
/* register clocks from clock array */
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
struct clk *clkp = init_clocks[ptr];
/* ensure that we note the clock state */
clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;

3
arch/arm/mach-s3c24xx/clock-s3c2440.c
View File

@ -166,6 +166,9 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
};

1
arch/arm/mach-shmobile/headsmp-scu.S
View File

@ -23,7 +23,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
/*
* Boot code for secondary CPUs.
*

2
arch/arm/mach-shmobile/headsmp.S
View File

@ -14,8 +14,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup

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